CY23EP09 2.5 V or 3.3 V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer Functional Description Features ■ 10 MHz to 220 MHz maximum operating range ■ Zero input-output propagation delay, adjustable by loading on CLKOUT pin ■ Multiple low-skew outputs — 45 ps typical output-output skew — One input drives nine outputs, grouped as 4 + 4 + 1 ■ 25 ps typical cycle-to-cycle jitter ■ 15 ps typical period jitter ■ Standard and High drive strength options ■ Available in space-saving 16-pin 150-mil small outline integrated circuit (SOIC) or 4.4-mm thin shrunk small outline package (TSSOP) packages ■ 3.3 V or 2.5 V operation ■ Industrial temperature available The CY23EP09 is a 2.5 V or 3.3 V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3 V (2.5 V), and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The phase-locked loop (PLL) feedback is on-chip and is obtained from the CLKOUT pad. There are two banks of four outputs each, which can be controlled by the Select inputs as shown in the “Select Input Decoding” table on page 4. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The PLL enters a power-down mode when there are no rising edges on the REF input (less than ~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 A of current draw. In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The part behaves like a non-zero delay buffer in this mode, and the outputs are not tri-stated. The CY23EP09 is available in different configurations, as shown in the Ordering Information table. The CY23EP09-1 is the base part. The CY23EP09-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5 V input-tolerant applications Block Diagram PLL MUX REF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 S2 Select Input Decoding CLKB2 CLKB3 S1 CLKB4 Cypress Semiconductor Corporation Document #: 38-07760 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 1, 2011 [+] Feedback CY23EP09 Contents Pin Configuration ............................................................. 3 Pin Definition .................................................................... 4 Select Input Decoding ...................................................... 4 Zero Delay and Skew Control .......................................... 4 Absolute Maximum Conditions ....................................... 5 Operating Conditions ....................................................... 5 3.3 V DC Electrical Specifications ................................... 5 2.5 V DC Electrical Specifications ................................... 6 3.3 V and 2.5 V AC Electrical Specifications .................. 6 Switching Waveforms ...................................................... 8 Test Circuits ...................................................................... 8 Document #: 38-07760 Rev. *C Supplemental Parametric Information ............................ 9 Ordering Code Definition ........................................... 13 Package Drawing and Dimensions ............................... 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 Page 2 of 17 [+] Feedback CY23EP09 Pin Configuration Top View Document #: 38-07760 Rev. *C REF CLKA1 1 16 2 15 CLKA2 VDD 3 14 4 13 GND CLKB1 CLKB2 S2 5 12 6 11 7 10 8 9 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Page 3 of 17 [+] Feedback CY23EP09 Pin Definition Pin Signal Description 1 REF[1] Input reference frequency 2 CLKA1[2] Buffered clock output, Bank A 3 CLKA2[2] Buffered clock output, Bank A 4 VDD 3.3 V or 2.5 V supply 5 GND Ground 6 CLKB1[2] Buffered clock output, Bank B 7 CLKB2[2] Buffered clock output, Bank B 8 S2 [3] Select input, bit 2 9 S1[3] Select input, bit 1 10 CLKB3[2] Buffered clock output, Bank B 11 CLKB4[2] Buffered clock output, Bank B 12 GND Ground 13 VDD 3.3 V or 2.5 V supply 14 CLKA3[2] Buffered clock output, Bank A 15 CLKA4[2] Buffered clock output, Bank A 16 CLKOUT[2] Buffered output, internal feedback on this pin Select Input Decoding CLOCK B1–B4 CLKOUT[4] S2 S1 CLOCK A1–A4 Output Source PLL Shutdown 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. The output driving the CLKOUT pin will be driving a total load of 5 pF plus any additional load externally connected to this pin. For applications requiring zero input-output delay, the total load on each output pin (including CLKOUT) must be the same. If input-output delay adjustments are required, the CLKOUT load may be changed to vary the delay between the REF input and remaining outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305 and CY2309 as PCI and SDRAM Buffers”. Notes 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document #: 38-07760 Rev. *C Page 4 of 17 [+] Feedback CY23EP09 Absolute Maximum Conditions Storage temperature................................... –65 °C to 150 °C Junction temperature.................................................. 150 °C Supply voltage to ground potential .................–0.5 V to 4.6 V Static discharge voltage (per MIL-STD-883, Method 3015............................. > 2000 V DC input voltage .....................................VSS – 0.5 V to 4.6 V Operating Conditions Min Max Unit VDD3.3 Parameter 3.3 V supply voltage Description 3.0 3.6 V VDD2.5 2.5 V supply voltage 2.3 2.7 V TA Operating temperature (ambient temperature)—commercial 0 70 °C Operating temperature (ambient temperature)—industrial CL[5] –40 85 °C Load capacitance, <100 MHz, 3.3 V – 30 pF Load capacitance, <100 MHz, 2.5 V with High drive – 30 pF Load capacitance, <133.3 MHz, 3.3 V – 22 pF Load capacitance, <133.3 MHz, 2.5 V with High drive – 22 pF Load capacitance, <133.3 MHz, 2.5 V with Standard drive – 15 pF Load capacitance, >133.3 MHz, 3.3 V – 15 pF Load capacitance, >133.3 MHz, 2.5 V with High drive – 15 pF CIN Input capacitance[6] – BW Closed-loop bandwidth (typical), 3.3 V 1–1.5 MHz Closed-loop bandwidth (typical), 2.5 V 0.8 MHz Output impedance (typical), 3.3 V High drive 29 Output impedance (typical), 3.3 V Standard drive 41 Output impedance (typical), 2.5 V High drive 37 ROUT Output impedance (typical), 2.5 V Standard drive tPU Power-up time for all VDD’s to reach minimum specified voltage (power ramps must be monotonic) Theta Ja[7] Dissipation, Junction to ambient, 16-pin SOIC Theta Jc[7] 5 41 0.01 pF 50 95 ms °C/W Dissipation, Junction to ambient, 16-pin TSSOP 70 °C/W Dissipation, Junction to case, 16-pin SOIC 58 °C/W Dissipation, Junction to case, 16-pin TSSOP 48 °C/W 3.3 V DC Electrical Specifications Parameter Description VDD Supply voltage VIL Input LOW voltage VIH Input HIGH voltage IIL Input leakage current IIH VOL Test Conditions Min Max Unit 3.0 3.6 V – 0.8 V 2.0 VDD+0.3 V 0 < VIN < VIL – ±10 A Input HIGH current VIN = VDD – 100 A Output LOW voltage IOL = 8 mA (standard drive) IOL = 12 mA (High drive) – – 0.4 0.4 V V VOH Output HIGH voltage IOH = –8 mA (standard drive) IOH = –12 mA (High drive) 2.4 2.4 – – V V IDD (PD mode) Power down supply current REF = 0 MHz (Commercial) – 12 A REF = 0 MHz (Industrial) – 25 A Unloaded outputs, 66-MHz REF – 30 mA IDD Supply current Notes 5. Applies to Test Circuit #1. 6. Applies to both REF Clock and internal feedback path on CLKOUT. 7. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1. Document #: 38-07760 Rev. *C Page 5 of 17 [+] Feedback CY23EP09 2.5 V DC Electrical Specifications Parameter Description Test Conditions Min Max Unit 2.3 2.7 V VDD Supply voltage VIL Input LOW voltage – 0.7 V VIH Input HIGHvoltage 1.7 VDD+ 0.3 V IIL Input leakage current 0<VIN < VDD – 10 A IIH Input HIGH current VIN = VDD – 100 A VOL Output LOW voltage IOL = 8 mA (Standard drive) IOL = 12 mA (High drive) – – 0.5 0.5 V V VOH Output HIGH voltage IOH = –8 mA (Standard drive) IOH = –12 mA (High drive) VDD – 0.6 VDD – 0.6 – – V V IDD (PD mode) Power down supply current REF = 0 MHz (Commercial) – 12 A REF = 0 MHz (Industrial) – 25 A Unloaded outputs, 66-MHz REF – 45 mA IDD Supply current 3.3 V and 2.5 V AC Electrical Specifications Parameter 1/t1 TIDC t2 t1 t3,t4 t3, t4 Description Test Conditions frequency[8] Maximum (input/output) Input duty cycle Output duty cycle[9] Rise, fall time (3.3V)[9] Rise, fall time (2.5 V)[9] [9] t5 Output to output skew t6 Delay, REF rising edge to CLKOUT rising edge[9] Min Typ Max Unit 3.3 V High drive 10 – 220 MHz 3.3 V Standard drive 10 – 167 MHz 2.5 V High drive 10 – 200 MHz 2.5 V Standard drive 10 – 133 MHz <133.3 MHz 25 – 75 % >133.3 MHz 40 – 60 % <133.3 MHz 47 – 53 % >133.3 MHz 45 – 55 % Std drive, CL = 30 pF, <100 MHz – – 1.6 ns Std drive, CL = 22 pF, <133.3 MHz – – 1.6 ns Std drive, CL = 15 pF, <167 MHz – – 0.6 ns High drive, CL = 30 pF, <100 MHz – – 1.2 ns High drive, CL = 22 pF, <133.3 MHz – – 1.2 ns High drive, CL = 15 pF, >133.3 MHz – – 0.5 ns Std drive, CL = 15 pF, <133.33 MHz – – 1.5 ns High drive, CL = 30 pF, <100 MHz – – 2.1 ns High drive, CL = 22 pF, <133.3 MHz – – 1.3 ns High drive, CL = 15 pF, >133.3 MHz – – 1.2 ns All outputs equally loaded, 3.3 V supply, 2.5 supply standard drive – 45 100 ps – – 110 ps 1.5 – 4.4 ns All outputs equally loaded, 2.5 V supply high drive PLL Bypass mode PLL enabled @ 3.3 V –100 – 100 ps PLL enabled @2.5 V –200 – 200 ps Notes 8. For the given maximum loading conditions. See CL in Operating Conditions Table. 9. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07760 Rev. *C Page 6 of 17 [+] Feedback CY23EP09 3.3 V and 2.5 V AC Electrical Specifications (continued) Parameter t7 Description Part to part skew [10] tLOCK PLL lock time[10] TJCC[10,11] Cycle-to-cycle jitter, peak TPER[10,11] Period jitter, peak Test Conditions Min Typ Max Unit Measured at VDD/2. Any output to any output, 3.3 V supply – – ±150 ps Measured at VDD/2. Any output to any output, 2.5 V supply – – ±300 ps Stable power supply, valid clocks presented on REF and CLKOUT pins – – 1.0 ms 3.3 V supply, >66 MHz, <15 pF – 25 55 ps 3.3 V supply, >66 MHz, <30 pF, standard drive – 65 125 ps 3.3 V supply, >66 MHz, <30 pF, high drive – 53 100 ps 2.5 V supply, >66 MHz, <15 pF, standard drive – 35 95 ps 2.5 V supply, >66 MHz, <15 pF, high drive – 30 65 ps 2.5 V supply, >66 MHz, <30 pF, high drive – 75 145 ps S2:S1 = 1:0 mode, 3.3 V, <15 pF, standard drive – 16 – ps S2:S1 = 1:0 mode, 3.3 V, <15 pF, high drive – 14 – ps S2:S1 = 1:0 mode, 2.5 V, <15 pF, standard drive – 23 – ps S2:S1 = 1:0 mode, 2.5 V, <15 pF, high drive – 22 – ps 3.3 V supply, 66–100 MHz, <15 pF – 20 75 ps 3.3 V supply, >100 MHz, <15 pF – 15 45 ps 3.3 V supply, >66 MHz, <30 pF, standard drive – 40 100 ps 3.3 V supply, >66 MHz, <30 pF, high drive – 30 70 ps 2.5 V supply, >66 MHz, <15 pF, standard drive – 25 60 ps 2.5 V supply, 66–100 MHz, <15 pF, high drive – 25 60 ps 2.5 V supply, >100 MHz, <15 pF, high drive – 15 45 ps S2:S1 = 1:0 mode, 3.3 V, <15 pF, standard drive – 28 – ps S2:S1 = 1:0 mode, 3.3 V, <15 pF, high drive – 24 – ps S2:S1 = 1:0 mode, 2.5 V, <15 pF, standard drive – 40 – ps S2:S1 = 1:0 mode, 2.5 V, <15 pF, high drive – 37 – ps Notes 10. Parameter is guaranteed by design and characterization. Not 100% tested in production. 11. Typical jitter is measured at 3.3 V or 2.5 V, 29 °C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be found in the application note “Understanding Data Sheet Jitter Specifications for Cypress Clock Products.” Document #: 38-07760 Rev. *C Page 7 of 17 [+] Feedback CY23EP09 Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 All Outputs Rise/Fall Time t3 OUTPUT 3.3V(2.5V) 2.0V(1.8V) 0.8V(0.6V) OUTPUT 2.0V(1.8V) 0.8V(0.6V) 0V t4 Output-Output Skew VDD/2 VDD/2 OUTPUT t5 Input-Output Propagation Delay INPUT VDD/2 VDD/2 CLKOUT t6 Part-Part Skew VDD/2 Any output, Part 1 or 2 VDD/2 Any output, Part 1 or 2 t7 Test Circuits Test Circuit # 1 V DD CLK 0.1 F OUTPUTS C LOAD V DD 0.1 F Document #: 38-07760 Rev. *C GND GND Page 8 of 17 [+] Feedback CY23EP09 Supplemental Parametric Information Delay REF Input to CLKA/B (ps) Figure 1. 2.5 V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay Versus Loading Difference between CLKOUT and CLKA/CLKB 1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -1200 S tandard D rive H igh D rive -20 -10 0 10 20 Load C LK O U T- Load C LK A/B (pF) Data is shown for 66 MHz. Delay is a weak function of frequency. Figure 2. 3.3 V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay Versus Loading Difference betwee CLKOUT and CLKA/CLKB 1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -1200 S tandard D rive H igh D rive -20 -10 0 10 20 Load C LK O U T- Load C LK A /B (pF) Data is shown for 66 MHz. Delay is a weak function of frequency. Document #: 38-07760 Rev. *C Page 9 of 17 [+] Feedback CY23EP09 Figure 3. 3.6 V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature 200 175 150 125 100 15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 30pF, -45C, Standard Drive 30pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive 75 50 25 33 66 100 133 166 200 233 Frequency (MHz) Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF. Figure 4. 2.7 V Measured Supply Current Versus Frequency, Drive Strength, Loading, and Temperature. 120 100 80 15pF, -45C, Standard Drive 60 15pF, 90C, Standard Drive 15pF, -45C, High Drive 40 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive 20 33 66 100 133 166 200 Frequency (MHz) Note that the 30-pF high-drive data above 100bMHz is beyond the data sheet specification of 22 pF. Document #: 38-07760 Rev. *C Page 10 of 17 [+] Feedback CY23EP09 Figure 5. Typical 3.3 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading 350 15 15 30 30 300 250 pF, pF, pF, pF, S ta n d a rd D riv e H ig h D riv e S ta n d a rd D riv e H ig h D riv e 200 150 100 50 0 0 50 100 150 200 250 F r e q u e n c y (M H z ) Figure 6. Typical 2.5 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading 350 1 5 p F , S t a n d a r d D r iv e 1 5 p F , H ig h D r iv e 3 0 p F , H ig h D r iv e 300 250 200 150 100 50 0 0 20 40 60 80 100 120 140 160 180 200 F re q u e n c y (M H z ) Figure 7. Typical 3.3 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading 250 15 15 30 30 200 pF, pF, pF, pF, S t a n d a r d D r iv e H ig h D r iv e S t a n d a r d D r iv e H ig h D r iv e 150 100 50 0 0 50 100 150 200 250 F re q u e n c y (M H z ) Figure 8. Typical 2.5 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading 250 1 5 p F , S t a n d a r d D r iv e 1 5 p F , H ig h D r iv e 3 0 p F , H ig h D r iv e 200 150 100 50 0 0 50 100 150 200 250 F re q u e n c y (M H z ) Document #: 38-07760 Rev. *C Page 11 of 17 [+] Feedback CY23EP09 Figure 9. Typical Phase-noise Data at 100 MHz (top) and 156.25 MHz (bottom) across VDD and Drive Strength[12] SSB Phase Noise (dBc/Hz) -90 2.5V, Standard Drive 2.5V, High Drive -100 3.3V, Standard Drive 3.3V, High Drive -110 -120 2.5V, Standard Drive 2.5V, High Drive -130 100 MHz -140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) 1.E+06 1.E+07 1.E+08 SSB Phase Noise (dBc/Hz) -90 2.5V, High Drive 3.3V, High Drive -100 -110 3.3V, Standard Drive 2.5V, Standard Drive -120 -130 156.25 MHz -140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) 1.E+06 1.E+07 1.E+08 Note 12. Typical jitter is measured at 3.3 V or 2.5 V, 29 °C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be found in the application note “Understanding Data Sheet Jitter Specifications for Cypress Clock Products.” Document #: 38-07760 Rev. *C Page 12 of 17 [+] Feedback CY23EP09 Ordering Information Ordering Code Package Type Operating Range Lead-free CY23EP09SXC-1 16-pin 150-mil SOIC Commercial CY23EP09SXC-1T 16-pin 150-mil SOIC – Tape and Reel Commercial CY23EP09SXI-1 16-pin 150-mil SOIC – Industrial CY23EP09SXI-1T 16-pin 150-mil SOIC – Tape and Reel Industrial CY23EP09SXC-1H 16-pin 150-mil SOIC Commercial CY23EP09SXC-1HT 16-pin 150-mil SOIC – Tape and Reel Commercial CY23EP09SXI-1H 16-pin 150-mil SOIC Industrial CY23EP09SXI-1HT 16-pin 150-mil SOIC – Tape and Reel Industrial CY23EP09ZXC-1H 16-pin 4.4-mm TSSOP Commercial CY23EP09ZXC-1HT 16-pin 4.4-mm TSSOP – Tape and Reel Commercial CY23EP09ZXI-1H 16-pin 4.4-mm TSSOP Industrial CY23EP09ZXI-1HT 16-pin 4.4-mm TSSOP – Tape and Reel Industrial Ordering Code Definition CY 23EP09 S(X) C 1 (H) (T) Tape and reel Output Drive: 1=standard drive, 1H=high drive Temperature Grade: I = Industrial, C = Commercial Package: S=SOIC, leaded Z=TSSOP, leaded SX=SOIC, Pb-free ZX=TSSOP, Pb-free Base device part number CY23EP09 = 9-output zero delay buffer Company ID: CY=Cypress Document #: 38-07760 Rev. *C Page 13 of 17 [+] Feedback CY23EP09 Package Drawing and Dimensions 16-Lead (150-Mil) SOIC S16 51-85068-*C 16-lead TSSOP 4.40 MM Body Z16.173 51-85091-*C Document #: 38-07760 Rev. *C Page 14 of 17 [+] Feedback CY23EP09 Acronyms Acronym Description PCI Personal computer interconnect PLL phase locked loop SDRAM Synchronous dynamic random access memory SOIC Small outline integrated circuit TSSOP Thin small outline package ZDB Zero delay buffer Document Conventions Units of Measure Symbol Units of Measure °C degree celsius µA micro amperes mA milli amperes ms milli seconds MHz mega hertz ns nano seconds pF pico farad ps pico seconds V volts Document #: 38-07760 Rev. *C Page 15 of 17 [+] Feedback CY23EP09 Document History Page Document Title: CY23EP09 2.5 V or 3.3 V, 10-220-MHz, Low Jitter, 9-Output Zero Delay Buffer Document Number: 38-07760 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 345446 See ECN RGL New data sheet *A 355777 See ECN RGL Updated part to part skew to agree with latest char results *B 401036 See ECN RGL Added PLL-bypass jitter Added Phase-noise graph Added 2.5V Delay vs. Load graph Removed Preliminary *C 3270178 06/01/2011 BASH Document #: 38-07760 Rev. *C Updated as per Template Updated package diagram 51-85068 and 51-85091. Added Acronyms and Units of Measure table Page 16 of 17 [+] Feedback CY23EP09 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07760 Rev. *C Revised June 1, 2011 Page 17 of 17 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback