Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY54/74FCT827T 10-Bit Buffer SCCS034 - September 1994 - Revised March 2000 • Sink current • Function, pinout, and drive compatible with FCT, F, and AM29827 logic • FCT-C speed at 4.4 ns max. (Com’l) FCT-A speed at 5.0 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature • ESD > 2000V • Matched rise and fall times • Fully compatible with TTL input and output logic levels Functional Description The FCT827T 10-bit bus driver provides high-performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NAND-ed output enables for maximum control flexibility. The FCT827T is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All outputs are designed for low-capacitance bus loading in the high-impedance state and are designed with a power-off disable feature to allow for live insertion of boards. Pin Configurations LCC/PLCC Top View D7 D6 D5 NC D4 Logic Block Diagram Source current 64 mA (Com’l), 32 mA (Mil) 32 mA (Com’l), 12 mA (Mil) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 D0 D1 D2 D3 D4 D5 D6 D7 D8 11 10 9 8 7 6 5 12 4 13 3 14 2 1 15 16 28 17 27 18 26 19 20 21 22 23 24 25 D1 D0 OE1 NC VCC Y0 Y1 Y7 Y6 Y5 NC Y4 Y3 Y2 D8 D9 GND NC OE2 Y9 Y8 D3 D2 Features D9 OE1 OE2 SOIC/QSOP Top View OE1 1 24 VCC D0 D1 2 23 Y0 3 22 Y1 D2 4 21 Y2 D3 5 20 Y3 D4 6 19 Y4 D5 7 18 Y5 D6 8 17 Y6 D7 9 16 D8 10 Y7 Y8 D9 11 15 14 GND 12 13 Y9 OE2 Function Table[1] Inputs Outputs OE1 OE2 D Y Function L L L L L H L H Transparent H X X H X X Z Z Three-State Note: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care Copyright © 2000, Texas Instruments Incorporated CY54/74FCT827T Maximum Ratings[2, 3] Power Dissipation .......................................................... 0.5W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied .............................................–65°C to +135°C Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V Commercial DC Input Voltage............................................ –0.5V to +7.0V [4] Military DC Output Voltage ......................................... –0.5V to +7.0V Ambient Temperature VCC All –40°C to + 85°C 5V ± 5% All –55°C to +125°C 5V ± 10% Range DC Output Current (Maximum Sink Current/Pin).......120 mA Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage VOL Output LOW Voltage Test Conditions Min. Typ.[5] Max. Unit VCC= Min., IOH= –32 mA Com’l 2.0 V VCC= Min., IOH= –15 mA Com’l 2.4 3.3 V VCC= Min., IOH= –12 mA Mil 2.4 3.3 V VCC= Min., IOL= 64 mA Com’l 0.3 0.55 V VCC= Min., IOL= 32 mA Mil 0.3 0.55 V VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage VH Hysteresis[6] All inputs 0.2 VIK Input Clamp Diode Voltage VCC= Min., IIN= –18 mA –0.7 II Input HIGH Current IIH 0.8 V V –1.2 V VCC= Max., VIN= VCC 5 µA Input HIGH Current VCC= Max., VIN= 2.7V ±1 µA IIL Input LOW Current VCC= Max., VIN= 0.5V ±1 µA IOZH Off State HIGH-Level Output Current VCC = Max., VOUT = 2.7V 10 µA IOZL Off State LOW-Level Output Current VCC = Max., VOUT = 0.5V –10 µA IOS Output Short Circuit Current[7] VCC= Max., VOUT= 0.0V –225 mA IOFF Power-Off Disable VCC= 0V, VOUT= 4.5V ±1 µA –60 –120 Capacitance[6] Parameter Description Typ.[5] Max. Unit CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Notes: 2. Unless otherwise noted, these limits are over the operating free-air temperature range. 3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 4. TA is the “instant on” case temperature. 5. Typical values are at VCC=5.0V, TA=+25˚C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 2 CY54/74FCT827T Power Supply Characteristics Parameter ICC Description Quiescent Power Supply Current Test Conditions VCC=Max., VIN≤0.2V, VIN≥VCC–0.2V Typ.[5] Max. Unit 0.1 0.2 mA 0.5 2.0 mA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max., VIN=3.4V, f1=0, Outputs Open ICCD Dynamic Power Supply Current[9] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, OE1 or OE2=GND, VIN≤0.2V or VIN≥VCC–0.2V 0.06 0.12 mA/MHz IC Total Power Supply Current[10] VCC=Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=10 MHz, OE1 or OE2=GND, VIN≤0.2V or VIN≥VCC–0.2V 0.7 1.4 mA VCC=Max.,50% Duty Cycle, Outputs Open, One Bit Toggling at f1=10 MHz, OE1 or OE2=GND, VIN=3.4V or VIN=GND 1.0 2.4 mA VCC=Max., 50% Duty Cycle, Outputs Open, Ten Bits Toggling at f1=2.5 MHz, OE1 or OE2=GND, VIN≤0.2V or VIN≥VCC–0.2V 1.6 3.2[11] mA VCC=Max., 50% Duty Cycle, Outputs Open, Ten Bits Toggling at f1=2.5 MHz, OE1 or OE2=GND,VIN=3.4V or VIN=GND 4.1 13.2[11] mA [8] Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 3 CY54/74FCT827T Switching Characteristics Over the Operating Range[12] FCT827AT Military Parameter Description Commercial Test Load Min. Max. Min. Fig. Max. Unit No.[13] tPLH tPHL Propagation Delay D to Y CL=50 pF RL=500Ω 1.5 9.0 1.5 8.0 ns 1, 3 tPLH tPHL Propagation Delay D to Y[12] CL=300 pF RL=500Ω 1.5 17.0 1.5 15.0 ns 1, 3 tPZH tPZL Output Enable Time OE to Y CL=50 pF RL=500Ω 1.5 13.0 1.5 12.0 ns 1, 7, 8 tPZH tPZL Output Enable Time OE to Y[12] CL=300 pF RL=500Ω 1.5 25.0 1.5 23.0 ns 1, 7, 8 tPHZ tPHL Output Disable Time OE to Y[12] CL=5 pF RL=500Ω 1.5 9.0 1.5 9.0 ns 1, 7, 8 tPHZ tPHL Output Disable Time OE to Y CL=50 pF RL=500Ω 1.5 10.0 1.5 10.0 ns 1, 7, 8 FCT827CT Commercial Parameter Description Test Load Min. Max. Unit Fig. No.[13] tPLH tPHL Propagation Delay D to Y CL=50 pF RL=500Ω 1.5 4.4 ns 1, 3 tPLH tPHL Propagation Delay D to Y[12] CL=300 pF RL=500Ω 1.5 10.0 ns 1, 3 tPZH tPZL Output Enable Time OE to Y CL=50 pF RL=500Ω 1.5 7.0 ns 1, 7, 8 tPZH tPZL Output Enable Time OE to Y[12] CL=300 pF RL=500Ω 1.5 14.0 ns 1, 7, 8 tPHZ tPHL Output Disable Time OE to Y[12] CL=5 pF RL=500Ω 1.5 5.7 ns 1, 7, 8 tPHZ tPHL Output Disable Time OE to Y CL=50 pF RL=500Ω 1.5 6.0 ns 1, 7, 8 Ordering Information Speed (ns) 4.4 8.0 9.0 Ordering Code Package Name Package Type CY74FCT827CTQCT Q13 24-Lead (150-Mil) QSOP CY74FCT827CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT827ATQCT Q13 24-Lead (150-Mil) QSOP CY74FCT827ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY54FCT827ATLMB L64 28-Square Leadless Chip Carrier Notes: 12. Minimum limits are specified but not tested on Propagation Delays. 13. See “Parameter Measurement Information” in the General Information section. Document #: 38-00326-A 4 Operating Range Commercial Commercial Military CY54/74FCT827T Package Diagrams 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 24-Lead Quarter Size Outline Q13 5 CY54/74FCT827T Package Diagrams (continued) 24-Lead (300-Mil) Molded SOIC S13 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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