Microsemi IO107PDB1 Proasic3 flash family fpgas with optional soft arm support Datasheet

Revision 15
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
Advanced I/O
High Capacity
• 15 K to 1 M System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM®-enabled ProASIC®3 devices)
via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents
Low Power
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
• 1 Kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in ProASIC3 FPGAs
• M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor
Available with or without Debug
ProASIC3 Devices
Cortex-M1 Devices 2
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP 3
Integrated PLL in CCCs
VersaNet Globals 4
I/O Banks
Maximum User I/Os
Package Pins
QFN
CS
VQFP
TQFP
PQFP
FBGA
A3P0151
A3P030
A3P060
A3P125
15,000
128
384
–
–
1
–
–
6
2
49
30,000
256
768
–
–
1
–
–
6
2
81
60,000
512
1,536
18
4
1
Yes
1
18
2
96
125,000
1,024
3,072
36
8
1
Yes
1
18
2
133
A3P250
M1A3P250
250,000
2,048
6,144
36
8
1
Yes
1
18
4
157
QN68
QN48, QN68,
QN1327
QN1327
QN1327
QN1327
VQ100
TQ144
PQ208
FG144
VQ100
VQ100
CS121
VQ100
TQ144
FG144
A3P400
M1A3P400
400,000
–
9,216
54
12
1
Yes
1
18
4
194
A3P600
M1A3P600
600,000
–
13,824
108
24
1
Yes
1
18
4
235
A3P1000
M1A3P1000
1,000,000
–
24,576
144
32
1
Yes
1
18
4
300
PQ208
PQ208
FG144/256 5 FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the Cortex-M1 product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.
7. Package not available.
† A3P015 and A3P030 devices do not support this feature.
July 2014
© 2014 Microsemi Corporation
‡ Supported only by A3P015 and A3P030 devices.
I
ProASIC3 Flash Family FPGAs
I/Os Per Package 1
ProASIC3
Devices
A3P0152
A3P030
A3P060
A3P125
Cortex-M1
Devices
A3P250 3
A3P400 3
A3P600
A3P1000
M1A3P250 3,5
M1A3P400 3
M1A3P600
M1A3P1000
–
–
49
49
–
–
–
–
–
QN132
–
81
80
84
87
19
CS121
–
–
96
–
–
VQ100
–
77
71
71
TQ144
–
–
91
PQ208
–
–
FG144
–
FG2565,6
FG4846
QN68
7
Differential I/O Pairs
Differential I/O Pairs
–
Single-Ended I/O4
Single-Ended I/O4
–
Differential I/O Pairs
Single-Ended I/O
34
Single-Ended I/O4
Single-Ended I/O
–
Differential I/O Pairs
Single-Ended I/O
QN48
Single-Ended I/O4
Package
Single-Ended I/O
I/O Type
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
68
13
–
–
–
–
–
100
–
–
–
–
–
–
–
–
–
133
151
34
151
34
154
35
154
35
–
96
97
97
24
97
25
97
25
97
25
–
–
–
–
157
38
178
38
177
43
177
44
–
–
–
–
–
–
194
38
235
60
300
74
–
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User Guide to
ensure complying with design and board migration requirements.
2. A3P015 is not recommended for new designs.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to
the ProASIC3 FPGA Fabric Users Guide for position assignments of the 15 LVPECL pairs.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1A3P250 device does not support FG256 package.
6. FG256 and FG484 are footprint-compatible packages.
7. Package not available.
Table 1 • ProASIC3 FPGAs Package Sizes Dimensions
CS121
QN48
QN68
QN132 *
VQ100
TQ144
PQ208
FG144
FG256
FG484
6×6
6×6
8×8
8×8
14 × 14
20 × 20
28 × 28
13 × 13
17 × 17
23 × 23
Nominal Area
(mm2)
36
36
64
64
196
400
784
169
289
529
Pitch (mm)
0.5
0.4
0.4
0.5
0.5
0.5
0.5
1.0
1.0
1.0
Height (mm)
0.99
0.90
0.90
0.75
1.00
1.40
3.40
1.45
1.60
2.23
Package
Length × Width
(mm × mm)
Note: * Package not available
II
R evis i o n 15
ProASIC3 Flash Family FPGAs
ProASIC3 Ordering Information
.
A3P1000
_
1
FG
G
Y
144
I
Application (Temperature Range)
Blank = Commercial (0°C to +85°C Junction Temperature)
I = Industrial (–40°C to +100°C Junction Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging (some packages also halogen-free)
Package Type
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
TQ = Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade CS = Chip Scale Package (0.5 mm pitch)
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3 Devices
A3P015 =
A3P030 =
A3P060 =
A3P125 =
A3P250 =
A3P400 =
A3P600 =
A3P1000 =
15,000 System Gates (A3P015 is not recommended for new designs.)
30,000 System Gates
60,000 System Gates
125,000 System Gates
250,000 System Gates
400,000 System Gates
600,000 System Gates
1,000,000 System Gates
ProASIC3 Devices with Cortex-M1
M1A3P250 =
M1A3P400 =
M1A3P600 =
M1A3P1000 =
250,000 System Gates
400,000 System Gates
600,000 System Gates
1,000,000 System Gates
ProASIC3 Device Status
ProASIC3 Devices
Status
Cortex-M1 Devices
Status
Production
M1A3P250
Production
A3P400
Production
M1A3P400
Production
A3P600
Production
M1A3P600
Production
A3P1000
Production
M1A3P1000
Production
A3P015
Not recommended for new designs.
A3P030
Production
A3P060
Production
A3P125
Production
A3P250
R ev i si o n 1 5
III
ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
Package
A3P0151
A3P030
A3P060
A3P125
Cortex-M1 Devices
QN48
A3P250
A3P400
A3P600
A3P1000
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
–
C, I
–
–
–
–
–
–
C, I
C, I
–
–
–
–
–
–
QN132
–
C, I
C, I
C, I
C, I
–
–
–
CS121
–
–
C, I
–
–
–
–
–
VQ100
–
C, I
C, I
C, I
C, I
–
–
–
TQ144
–
–
C, I
C, I
–
–
–
–
PQ208
–
–
–
C, I
C, I
C, I
C, I
C, I
FG144
–
–
C, I
C, I
C, I
C, I
C, I
C, I
FG256
–
–
–
–
C, I
C, I
C, I
C, I
FG484
–
–
–
–
–
C, I
C, I
C, I
QN68
2
Notes:
1. A3P015 is not recommended for new designs.
2. Package not available
C = Commercial temperature range: 0°C to 85°C junction temperature
I = Industrial temperature range: –40°C to 100°C junction temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
1
I2
Std.
–1
–2






Notes:
1. C = Commercial temperature range: 0°C to 85°C junction temperature
2. I = Industrial temperature range: –40°C to 100°C junction temperature
References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi representative for device availability: http://www.microsemi.com/soc/contact/default.aspx.
A3P015 and A3P030
The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.
Devices Not Recommended For New Designs
A3P015 is not recommended for new designs.
IV
R evis i o n 15
ProASIC3 Flash Family FPGAs
Table of Contents
ProASIC3 DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-3
3-4
3-4
Package Pin Assignments
QN48 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
QN68 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
QN132 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CS121 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
VQ100 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
TQ144 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
PQ208 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
FG144 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
FG256 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
FG484 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
R ev i si o n 1 5
V
2 – ProASIC3 DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 •
Symbol
Absolute Maximum Ratings
Parameter
Limits
Units
VCC
DC core supply voltage
–0.3 to 1.65
V
VJTAG
JTAG DC voltage
–0.3 to 3.75
V
VPUMP
Programming voltage
–0.3 to 3.75
V
VCCPLL Analog power supply (PLL)
–0.3 to 1.65
V
VCCI
DC I/O output buffer supply voltage
–0.3 to 3.75
V
VMV
DC I/O input buffer supply voltage
–0.3 to 3.75
V
VI
I/O input voltage
–0.3 V to 3.6 V
V
(when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
TSTG 2
Storage temperature
–65 to +150
°C
TJ 2
Junction temperature
+125
°C
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-2.
2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on
page 3-1 for further information.
3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
R ev i si o n 1 5
2-1
ProASIC3 Flash Family FPGAs
Table 2-2 •
Recommended Operating Conditions 1
Parameters 1
Symbol
TJ
Commercial
Junction temperature
3
0 to 85
VCC
1.5 V DC core supply voltage
VJTAG
JTAG DC voltage
VPUMP
Programming voltage
VCCI and
VMV 5
Industrial
-40 to 100
2
Units
°C
1.425 to 1.575
1.425 to 1.575
V
1.4 to 3.6
1.4 to 3.6
V
3.15 to 3.45
3.15 to 3.45
V
0 to 3.6
0 to 3.6
V
Analog power supply (PLL)
1.425 to 1.575
1.425 to 1.575
V
1.5 V DC supply voltage
1.425 to 1.575
1.425 to 1.575
V
1.8 V DC supply voltage
1.7 to 1.9
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
2.3 to 2.7
V
3.0 to 3.3
3.0 to 3.3
V
2.7 to 3.6
2.7 to 3.6
V
2.375 to 2.625
2.375 to 2.625
V
3.0 to 3.6
3.0 to 3.6
V
Programming Mode
Operation 4
VCCPLL
2
3.3 V DC supply voltage
3.3 V wide range DC supply
voltage 6
LVDS/B-LVDS/M-LVDS differential I/O
LVPECL differential I/O
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. Software Default Junction Temperature Range in the Libero SoC software is set to 0°C to +70°C for commercial, and 40°C to +85°C for industrial. To ensure targeted reliability standards are met across the full range of junction
temperatures, Microsemi recommends using custom settings for temperature range before running timing and power
analysis tools. For more information regarding custom settings, refer to the New Project Dialog Box in the Libero SoC
Online Help.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-18 on page 2-18.
4. VPUMP can be left floating during operation (not programming mode).
5. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the
corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information.
6. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
Table 2-3 •
Product
Grade
Flash Programming Limits – Retention, Storage and Operating Temperature1
Programming Program Retention
Cycles
(biased/unbiased)
Maximum Storage
Temperature TSTG (°C)2
Maximum Operating
Junction Temperature TJ (°C)2
Commercial
500
20 years
110
100
Industrial
500
20 years
110
100
1.
2.
This is a stress rating only; functional operation at any condition other than those indicated is not implied.
These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
Table 2-4 •
Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or Undershoot
Duration as a Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot2
2.7 V or less
10%
1.4 V
5%
1.49 V
3V
10%
1.1 V
5%
1.19 V
VCCI and VMV
3.3 V
10%
0.79 V
5%
0.88 V
R ev i si o n 1 5
2-2
ProASIC3 Flash Family FPGAs
Table 2-4 •
Overshoot and Undershoot Limits 1 (continued)
VCCI and VMV
Average VCCI–GND Overshoot or Undershoot
Duration as a Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot2
10%
0.45 V
5%
0.54 V
3.6 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges.
In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown
in Figure 2-1 on page 2-4.
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
•
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4
for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation
R ev i si o n 1 5
2-3
ProASIC3 Flash Family FPGAs
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
Region 1: I/O Buffers are OFF
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
VCC = 1.425 V
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
Activation trip point:
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
Figure 2-1 •
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCCI
I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction to be higher than the ambient temperature.
EQ can be used to calculate junction temperature.
TJ = Junction Temperature = ΔT + TA
where:
TA = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P
θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal resistivity is
θja. The thermal characteristics for θja are shown for two air flow rates.
R ev i si o n 1 5
2-4
ProASIC3 Flash Family FPGAs
The absolute maximum junction temperature is 100°C. EQ 1 shows a sample calculation of the absolute
maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still
air.
Max. junction temp. (°C) – Max. ambient temp. (°C) 100°C – 70°C
·
Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------- = 1.463 W
20.5°C/W
θ ja (°C/W)
EQ 1
Table 2-5 •
Package Thermal Resistivities
θja
Package Type
Device
Pin Count
θjc
Quad Flat No Lead
A3P030
132
0.4
21.4
16.8
15.3
°C/W
A3P060
132
0.3
21.2
16.6
15.0
°C/W
A3P125
132
0.2
21.1
16.5
14.9
°C/W
A3P250
132
0.1
21.0
16.4
14.8
°C/W
Very Thin Quad Flat Pack (VQFP)
All devices
100
10.0
35.3
29.4
27.1
°C/W
Thin Quad Flat Pack (TQFP)
All devices
144
11.0
33.5
28.0
25.7
°C/W
Plastic Quad Flat Pack (PQFP)
All devices
208
8.0
26.1
22.5
20.8
°C/W
PQFP with embedded heatspreader
All devices
208
3.8
16.2
13.3
11.9
°C/W
Fine Pitch Ball Grid Array (FBGA)
See note*
144
3.8
26.9
22.9
21.5
°C/W
note*
256
3.8
26.6
22.8
21.5
°C/W
*
484
3.2
20.5
17.0
15.9
°C/W
A3P1000
144
6.3
31.6
26.2
24.2
°C/W
A3P1000
256
6.6
28.1
24.4
22.7
°C/W
A3P1000
484
8.0
23.3
19.0
16.7
°C/W
See
See note
Still Air 200 ft./min.
500 ft./min. Units
Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal
information will be available in future revisions of the datasheet.
R ev i si o n 1 5
2-5
ProASIC3 Flash Family FPGAs
Temperature and Voltage Derating Factors
Table 2-6 •
Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C, VCC = 1.425 V)
Junction Temperature (°C)
Array Voltage VCC
(V)
–40°C
0°C
25°C
70°C
85°C
100°C
1.425
0.88
0.93
0.95
1.00
1.02
1.04
1.500
0.83
0.88
0.90
0.95
0.96
0.98
1.575
0.80
0.84
0.87
0.91
0.93
0.94
Calculating Power Dissipation
Quiescent Supply Current
Table 2-7 •
Quiescent Supply Current Characteristics
A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
Typical (25°C)
2 mA
2 mA
2 mA
2 mA
3 mA
3 mA
5 mA
8 mA
Max. (Commercial)
10 mA
10 mA
10 mA
10 mA
20 mA
20 mA
30 mA
50 mA
Max. (Industrial)
15 mA
15 mA
15 mA
15 mA
30 mA
30 mA
45 mA
75 mA
Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static
contribution, which is shown in Table 2-11 and Table 2-12 on page 2-8.
Power per I/O Pin
Table 2-8 •
Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks
VMV (V)
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
16.22
3
3.3 V LVCMOS Wide Range
3.3
–
16.22
2.5 V LVCMOS
2.5
–
5.12
1.8 V LVCMOS
1.8
–
2.13
1.5 V LVCMOS (JESD8-11)
1.5
–
1.45
3.3 V PCI
3.3
–
18.11
3.3 V PCI-X
3.3
–
18.11
LVDS
2.5
2.26
1.20
LVPECL
3.3
5.72
1.87
Single-Ended
Differential
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
R ev i si o n 1 5
2-6
ProASIC3 Flash Family FPGAs
Table 2-9 •
Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
VMV (V)
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
16.23
3
3.3 V LVCMOS Wide Range
3.3
–
16.23
2.5 V LVCMOS
2.5
–
5.14
1.8 V LVCMOS
1.8
–
2.13
1.5 V LVCMOS (JESD8-11)
1.5
–
1.48
3.3 V PCI
3.3
–
18.13
3.3 V PCI-X
3.3
–
18.13
Single-Ended
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
VMV (V)
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
3.3 V LVTTL / 3.3 V LVCMOS
3.3
–
17.24
3.3 V LVCMOS Wide Range3
3.3
–
17.24
2.5 V LVCMOS
2.5
–
5.19
1.8 V LVCMOS
1.8
–
2.18
1.5 V LVCMOS (JESD8-11)
1.5
–
1.52
Single-Ended
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
R ev i si o n 1 5
2-7
ProASIC3 Flash Family FPGAs
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Advanced I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC3 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
–
468.67
4
35
3.3
–
468.67
2.5 V LVCMOS
35
2.5
–
267.48
1.8 V LVCMOS
35
1.8
–
149.46
1.5 V LVCMOS
(JESD8-11)
35
1.5
–
103.12
3.3 V PCI
10
3.3
–
201.02
3.3 V PCI-X
10
3.3
–
201.02
LVDS
–
2.5
7.74
88.92
LVPECL
–
3.3
19.54
166.52
Single-Ended
3.3 V LVCMOS Wide Range
Differential
Notes:
1.
2.
3.
4.
Dynamic power consumption is given for standard load and software default drive strength and output slew.
PDC3 is the static power (where applicable) measured on VCCI.
PAC10 is the total dynamic power measured on VCC and VCCI.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1
Applicable to Standard Plus I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC3 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
–
452.67
3.3 V LVCMOS Wide Range4
35
3.3
–
452.67
2.5 V LVCMOS
35
2.5
–
258.32
1.8 V LVCMOS
35
1.8
–
133.59
1.5 V LVCMOS (JESD8-11)
35
1.5
–
92.84
3.3 V PCI
10
3.3
–
184.92
3.3 V PCI-X
10
3.3
–
184.92
Single-Ended
Notes:
1.
2.
3.
4.
Dynamic power consumption is given for standard load and software default drive strength and output slew.
PDC3 is the static power (where applicable) measured on VMV.
PAC10 is the total dynamic power measured on VCC and VMV.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
R ev i si o n 1 5
2-8
ProASIC3 Flash Family FPGAs
Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings 1
Applicable to Standard I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC3 (mW) 2
Dynamic Power
PAC10 (µW/MHz) 3
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
–
431.08
4
35
3.3
–
431.08
2.5 V LVCMOS
35
2.5
–
247.36
1.8 V LVCMOS
35
1.8
–
128.46
1.5 V LVCMOS (JESD8-11)
35
1.5
–
89.46
Single-Ended
3.3 V LVCMOS Wide Range
Notes:
1.
2.
3.
4.
Dynamic power consumption is given for standard load and software default drive strength and output slew.
PDC3 is the static power (where applicable) measured on VCCI.
PAC10 is the total dynamic power measured on VCC and VCCI.
All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
R ev i si o n 1 5
2-9
ProASIC3 Flash Family FPGAs
Power Consumption of Various Internal Resources
Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices
A3P015
A3P030
A3P060
A3P125
A3P250
A3P400
Definition
A3P600
Parameter
A3P1000
Device Specific Dynamic Contributions
(µW/MHz)
PAC1
Clock contribution of a Global Rib
14.50 12.80 12.80 11.00 11.00 9.30
9.30 9.30
PAC2
Clock contribution of a Global Spine
2.48
0.41 0.41
PAC3
Clock contribution of a VersaTile row
0.81
PAC4
Clock contribution of a VersaTile used as a
sequential module
0.12
PAC5
First contribution of a VersaTile used as a
sequential module
0.07
PAC6
Second contribution of a VersaTile used as a
sequential module
0.29
PAC7
Contribution of a VersaTile used as a
combinatorial Module
0.29
PAC8
Average contribution of a routing net
0.70
PAC9
Contribution of an I/O input pin (standard
dependent)
See Table 2-8 on page 2-6 through
Table 2-10 on page 2-7.
PAC10
Contribution of an I/O output pin (standard
dependent)
See Table 2-11 on page 2-8 through
Table 2-13 on page 2-9.
PAC11
Average contribution of a RAM block during a
read operation
25.00
PAC12
Average contribution of a RAM block during a
write operation
30.00
PAC13
Dynamic contribution for PLL
2.60
1.85
1.35
1.58
0.81
0.81
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
R ev i si o n 1 5
2- 10
ProASIC3 Flash Family FPGAs
Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices
PDC1
Array static power in Active mode
PDC2
I/O input pin static power (standard-dependent)
See Table 2-8 on page 2-6 through
Table 2-10 on page 2-7.
PDC3
I/O output pin static power (standard-dependent)
See Table 2-11 on page 2-8 through
Table 2-13 on page 2-9.
PDC4
Static PLL contribution
PDC5
Bank quiescent power (VCCI-dependent)
A3P015
A3P030
A3P060
A3P125
A3P250
A3P400
Parameter
A3P600
Device Specific Static Power (mW)
A3P1000
Definition
See Table 2-7 on page 2-6.
2.55 mW
See Table 2-7 on page 2-6.
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
•
The number of PLLs as well as the number and the frequency of each output clock generated
•
The number of combinatorial and sequential cells used in the design
•
The internal clock frequencies
•
The number and the standard of I/O pins used in the design
•
The number of RAM blocks used in the design
•
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on
page 2-13.
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on
page 2-13.
•
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide.
R ev i si o n 1 5
2- 11
ProASIC3 Flash Family FPGAs
NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide.
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
β1 is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-13.
FCLK is the global clock signal frequency.
R ev i si o n 1 5
2- 12
ProASIC3 Flash Family FPGAs
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-13.
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
Bit 0 (LSB) = 100%
–
Bit 1
= 50%
–
Bit 2
= 25%
–
…
–
Bit 7 (MSB) = 0.78125%
–
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation
Component
α1
α2
Definition
Guideline
Toggle rate of VersaTile outputs
10%
I/O buffer toggle rate
10%
Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation
Component
β1
β2
β3
1.
Definition
Guideline
I/O output buffer enable rate
100%
RAM enable rate for read operations
12.5%
RAM enable rate for write operations
12.5%
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
R ev i si o n 1 5
2- 13
ProASIC3 Flash Family FPGAs
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Combinational Cell
Y
LVPECL (Applicable to
Advanced I/O Banks Only)L
Y
tPD = 0.56 ns
tPD = 0.49 ns
tDP = 1.34 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
LVTTL Output drive strength = 12 mA
High slew rate
tDP = 2.64 ns (Advanced I/O Banks)
tPD = 0.87 ns
I/O Module
(Non-Registered)
Combinational Cell
I/O Module
(Registered)
Y
LVTTL Output drive strength = 8 mA
High slew rate
tDP = 3.66 ns (Advanced I/O Banks)
tPY = 1.05 ns
LVPECL
(Applicable
to Advanced
I/O Banks only)
D
tPD = 0.47 ns
Q
I/O Module
(Non-Registered)
Combinational Cell
Y
tICLKQ = 0.24 ns
tISUD = 0.26 ns
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
tDP = 3.97 ns (Advanced I/O Banks)
tPD = 0.47 ns
Input LVTTL
Clock
Register Cell
tPY = 0.76 ns (Advanced I/O Banks)
D
Y
Q
I/O Module
(Non-Registered)
LVDS,
BLVDS,
M-LVDS
(Applicable for
Advanced I/O
Banks only)
Figure 2-2 •
D
Q
D
tPD = 0.47 ns
Q
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
tDP = 2.64 ns
(Advanced I/O Banks)
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tPY = 1.20 ns
I/O Module
(Registered)
Combinational Cell Register Cell
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tOCLKQ = 0.59 ns
tOSUD = 0.31 ns
Input LVTTL
Clock
Input LVTTL
Clock
tPY = 0.76 ns
(Advanced I/O Banks)
tPY = 0.76 ns
(Advanced I/O Banks)
Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case
VCC = 1.425 V
R ev i si o n 1 5
2- 14
ProASIC3 Flash Family FPGAs
tPY
tDIN
D
PAD
Q
DIN
Y
CLK
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
To Array
I/O Interface
VIH
PAD
Vtrip
Vtrip
VIL
VCC
50%
50%
Y
GND
tPY
(F)
tPY
(R)
VCC
50%
DIN
GND
50%
tDIN
tDIN
(R)
Figure 2-3 •
(F)
Input Buffer Timing Model and Delays (Example)
R ev i si o n 1 5
2- 15
ProASIC3 Flash Family FPGAs
tDOUT
tDP
D Q
D
PAD
DOUT
Std
Load
CLK
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
(R)
D
50%
tDOUT
VCC
(F)
50%
0V
VCC
DOUT
50%
50%
0V
VOH
Vtrip
Vtrip
VOL
PAD
tDP
(R)
Figure 2-4 •
tDP
(F)
Output Buffer Model and Delays (Example)
R ev i si o n 1 5
2- 16
ProASIC3 Flash Family FPGAs
tEOUT
D
Q
CLK
E
tZL, tZH, tHZ, tLZ, tZLS, tZHS
EOUT
D
Q
PAD
DOUT
CLK
D
tEOUT = MAX(tEOUT(r), tEOUT(f))
I/O Interface
VCC
D
VCC
50%
tEOUT (F)
50%
E
tEOUT (R)
VCC
50%
EOUT
tZL
PAD
50%
50%
tHZ
Vtrip
tZH
50%
tLZ
VCCI
90% VCCI
Vtrip
VOL
10% VCCI
VCC
D
VCC
E
50%
tEOUT (R)
50%
tEOUT (F)
VCC
EOUT
PAD
50%
tZLS
VOH
Vtrip
Figure 2-5 •
50%
50%
tZHS
Vtrip
VOL
Tristate Output Buffer Timing Model and Delays (Example)
R ev i si o n 1 5
2- 17
ProASIC3 Flash Family FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
Equiv.
Software
Default
Drive
Drive Strength Slew Min.
I/O Standard Strength Option2 Rate V
VIL
VIH
VOL
VOH
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
IOL1 IOH1
mA mA
3.3 V LVTTL /
3.3 V
LVCMOS
12 mA
12 mA
High –0.3
0.8
2
3.6
0.4
2.4
12
12
3.3 V
LVCMOS
Wide Range3
100 µA
12 mA
High –0.3
0.8
2
3.6
0.2
VCCI – 0.2
0.1
0.1
2.5 V
LVCMOS
12 mA
12 mA
High –0.3
0.7
1.7
2.7
0.7
1.7
12
12
1.8 V
LVCMOS
12 mA
12 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI – 0.45
12
12
1.5 V
LVCMOS
12 mA
12 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI
12
12
3.3 V PCI
3.3 V PCI-X
Per PCI specifications
Per PCI-X specifications
Notes:
1. Currents are measured at 85°C junction temperature.
2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the
equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
R ev i si o n 1 5
2- 18
ProASIC3 Flash Family FPGAs
Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
Equiv.
Software
Default
Drive
Drive Strength Slew Min.
I/O Standard Strength Option2 Rate
V
VIL
VIH
VOL
VOH
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2.4
IOL1 IOH1
mA mA
3.3 V LVTTL / 12 mA
3.3 V
LVCMOS
12 mA
High –0.3
0.8
2
3.6
0.4
100 µA
3.3 V
LVCMOS
Wide Range3
12 mA
High –0.3
0.8
2
3.6
0.2
2.5 V
LVCMOS
12 mA
12 mA
High –0.3
0.7
1.7
2.7
0.7
1.7
12
12
1.8 V
LVCMOS
8 mA
8 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI –
0.45
8
8
1.5 V
LVCMOS
4 mA
4 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI
4
4
3.3 V PCI
3.3 V PCI-X
12
12
VCCI – 0.2 0.1
0.1
Per PCI specifications
Per PCI-X specifications
Notes:
1. Currents are measured at 85°C junction temperature.
2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the
equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
R ev i si o n 1 5
2- 19
ProASIC3 Flash Family FPGAs
Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard I/O Banks
Equiv.
Software
Default
Drive
Drive Strength Slew Min.
I/O Standard Strength Option2 Rate V
3.3 V LVTTL /
3.3 V
LVCMOS
8 mA
VIL
VIH
VOL
VOH
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
IOL1 IOH1
mA mA
8 mA
High –0.3
0.8
2
3.6
0.4
2.4
8
8
100 µA
3.3 V
LVCMOS
Wide Range3
8 mA
High –0.3
0.8
2
3.6
0.2
VCCI – 0.2
0.1
0.1
2.5 V
LVCMOS
8 mA
8 mA
High –0.3
0.7
1.7
2.7
0.7
1.7
8
8
1.8 V
LVCMOS
4 mA
4 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45
VCCI – 0.45
4
4
1.5 V
LVCMOS
2 mA
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.25 * VCCI 0.75 * VCCI
2
2
Notes:
1. Currents are measured at 85°C junction temperature.
2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the
equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-21 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL3
IIH4
IIL3
IIH4
DC I/O Standards
µA
µA
µA
µA
3.3 V LVTTL / 3.3 V LVCMOS
10
10
15
15
3.3 V LVCMOS Wide Range
10
10
15
15
2.5 V LVCMOS
10
10
15
15
1.8 V LVCMOS
10
10
15
15
1.5 V LVCMOS
10
10
15
15
3.3 V PCI
10
10
15
15
3.3 V PCI-X
10
10
15
15
Notes:
1. Commercial range (0°C < TA < 70°C)
2. Industrial range (–40°C < TA < 85°C)
3. IIL is the input leakage current per I/O pin over recommended operation conditions where
–0.3V < VIN <VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
R ev i si o n 1 5
2- 20
ProASIC3 Flash Family FPGAs
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-22 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip)
3.3 V LVTTL / 3.3 V LVCMOS
1.4 V
3.3 V LVCMOS Wide Range
1.4 V
2.5 V LVCMOS
1.2 V
1.8 V LVCMOS
0.90 V
1.5 V LVCMOS
0.75 V
3.3 V PCI
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V PCI-X
0.285 * VCCI (RR)
0.615 * VCCI (FF)
Table 2-23 • I/O AC Parameter Definitions
Parameter
Parameter Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer
tDOUT
Data to Output Buffer delay through the I/O interface
tEOUT
Enable to Output Buffer Tristate Control delay through the I/O interface
tDIN
Input Buffer to Data delay through the I/O interface
tHZ
Enable to Pad delay through the Output Buffer—High to Z
tZH
Enable to Pad delay through the Output Buffer—Z to High
tLZ
Enable to Pad delay through the Output Buffer—Low to Z
tZL
Enable to Pad delay through the Output Buffer—Z to Low
tZHS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
R ev i si o n 1 5
2- 21
ProASIC3 Flash Family FPGAs
1.8 V LVCMOS
12 mA
12 mA High 35
–
0.45 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns
1.5 V LVCMOS
12 mA
12 mA High 35
–
Units
0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns
tZHS (ns)
–
tZLS (ns)
12 mA 12 mA High 35
tHZ (ns)
2.5 V LVCMOS
tLZ (ns)
0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74 ns
tZH (ns)
–
tZL (ns)
100 µA 12 mA High 35
tE O U T (ns)
3.3 V LVCMOS
Wide Range2
tPY (ns)
0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns
tDIN (ns)
–
tDP (ns)
12 mA High 35
tDOUT (ns)
External Resistor (Ω)
12 mA
Slew Rate
3.3 V LVTTL /
3.3 V LVCMOS
I/O Standard
Drive Strength
Capacitive Load (pF)
Equiv. Software Default
Drive Strength Option1
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
Advanced I/O Banks
0.45 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns
4
3.3 V PCI
Per
PCI
spec
–
High 10 25
3.3 V PCI-X
Per
PCI-X
spec
–
High 10 25 4 0.45 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
LVDS
24 mA
–
High
–
–
0.45 1.37 0.03 1.20
–
–
–
–
–
–
–
ns
LVPECL
24 mA
–
High
–
–
0.45 1.34 0.03 1.05
–
–
–
–
–
–
–
ns
0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for
connectivity. This resistor is not required during normal operation.
R ev i si o n 1 5
2- 22
ProASIC3 Flash Family FPGAs
Units
tZHS (ns)
tZLS (ns)
tHZ (ns)
tLZ (ns)
tZH (ns)
tZL (ns)
tE O U T (ns)
tPY (ns)
tDIN (ns)
tDP (ns)
tDOUT (ns)
External Resistor
Capacitive Load (pF)
Slew Rate
Equiv. Software Default
Drive Strength Option1
I/O Standard
Drive Strength
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
Standard Plus I/O Banks
3.3 V LVTTL / 12 mA 12 mA High 35
3.3 V LVCMOS
–
0.45 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns
3.3 V LVCMOS 100 µA 12 mA High 35
Wide Range2
–
0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46 ns
2.5 V LVCMOS 12 mA 12 mA High 35
–
0.45 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns
1.8 V LVCMOS
8 mA
8 mA High 35
–
0.45 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns
1.5 V LVCMOS
4 mA
4 mA High 35
–
0.45 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns
25 4
0.45 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns
3.3 V PCI
Per
PCI
spec
–
High 10
3.3 V PCI-X
Per
PCI-X
spec
–
High 10 25 4 0.45 1.72 0.03 0.62 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for
connectivity. This resistor is not required during normal operation.
R ev i si o n 1 5
2- 23
ProASIC3 Flash Family FPGAs
35
–
0.45 5.09 0.03 1.13 0.32 5.09 4.25 2.77
3.11
ns
2.5 V LVCMOS
8 mA
8 mA
High
35
–
0.45 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91
ns
1.8 V LVCMOS
4 mA
4 mA
High
35
–
0.45 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85
ns
1.5 V LVCMOS
2 mA
2 mA
High
35
–
0.45 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83
ns
Units
High
tHZ (ns)
3.3 V LVCMOS 100 µA 8 mA
Wide Range2
tLZ (ns)
ns
tZH (ns)
0.45 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01
tZL (ns)
–
tE O U T (ns)
External Resistor
35
tPY (ns)
Capacitive Load (pF)
High
tDIN (ns)
Slew Rate
8 mA
3.3 V LVTTL /
3.3 V LVCMOS
tDP (ns)
Equiv. Software Default
Drive Strength Option1
8 mA
I/O Standard
tDOUT (ns)
Drive Strength
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
Standard I/O Banks
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 24
ProASIC3 Flash Family FPGAs
I/O DC Characteristics
Table 2-27 • Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
CIN
Input capacitance
VIN = 0, f = 1.0 MHz
–
8
pF
CINCLK
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
–
8
pF
Table 2-28 • I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI/PCI-X
Drive Strength
RPULL-DOWN (Ω)2
RPULL-UP (Ω)3
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
Per PCI/PCI-X
specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
R ev i si o n 1 5
2- 25
ProASIC3 Flash Family FPGAs
Table 2-29 • I/O Output Buffer Maximum Resistances 1
Applicable to Standard Plus I/O Banks
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI/PCI-X
Drive Strength
RPULL-DOWN (Ω)2
RPULL-UP (Ω)3
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
25
75
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
2 mA
200
224
4 mA
100
112
Per PCI/PCI-X
specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
R ev i si o n 1 5
2- 26
ProASIC3 Flash Family FPGAs
Table 2-30 • I/O Output Buffer Maximum Resistances1
Applicable to Standard I/O Banks
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
4
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Drive Strength
RPULL-DOWN
(Ω)2
RPULL-UP
(Ω)3
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
2 mA
200
225
4 mA
100
112
2 mA
200
224
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
R(WEAK PULL-UP)1
(Ω)
R(WEAK PULL-DOWN)2
(Ω)
VCCI
Min.
Max.
Min.
Max.
3.3 V
10 k
45 k
10 k
45 k
3.3 V (wide range I/Os)
10 k
45 k
10 k
45 k
2.5 V
11 k
55 k
12 k
74 k
1.8 V
18 k
70 k
17 k
110 k
1.5 V
19 k
90 k
19 k
140 k
Notes:
1. R(WEAK PULL-UP-MAX) = (VCCIMAX – VOHspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)
R ev i si o n 1 5
2- 27
ProASIC3 Flash Family FPGAs
Table 2-32 • I/O Short Currents IOSH/IOSL
Applicable to Advanced I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI/PCI-X
2
Drive Strength
IOSL (mA)1
IOSH (mA)1
2 mA
27
25
4 mA
27
25
6 mA
54
51
8 mA
54
51
12 mA
109
103
16 mA
127
132
24 mA
181
268
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
18
16
4 mA
18
16
6 mA
37
32
8 mA
37
32
12 mA
74
65
16 mA
87
83
24 mA
124
169
2 mA
11
9
4 mA
22
17
6 mA
44
35
8 mA
51
45
12 mA
74
91
16 mA
74
91
2 mA
16
13
4 mA
33
25
6 mA
39
32
8 mA
55
66
12 mA
55
66
Per PCI/PCI-X
specification
109
103
Notes:
1. TJ = 100°C
2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected
for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as
specified in the JESD8-B specification.
R ev i si o n 1 5
2- 28
ProASIC3 Flash Family FPGAs
Table 2-33 • I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range2
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI/PCI-X
Drive Strength
IOSL (mA)1
IOSH (mA)1
2 mA
27
25
4 mA
27
25
6 mA
54
51
8 mA
54
51
12 mA
109
103
16 mA
109
103
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
18
16
4 mA
18
16
6 mA
37
32
8 mA
37
32
12 mA
74
65
2 mA
11
9
4 mA
22
17
6 mA
44
35
8 mA
44
35
2 mA
16
13
4 mA
33
25
Per PCI/PCI-X
specification
109
103
Notes:
1. TJ = 100°C
2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength
selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide
range as specified in the JESD8-B specification.
R ev i si o n 1 5
2- 29
ProASIC3 Flash Family FPGAs
Table 2-34 • I/O Short Currents IOSH/IOSL
Applicable to Standard I/O Banks
Drive Strength
IOSL (mA)1
IOSH (mA)1
2 mA
27
25
4 mA
27
25
6 mA
54
51
3.3 V LVTTL / 3.3 V LVCMOS
8 mA
54
51
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
18
16
4 mA
18
16
6 mA
37
32
8 mA
37
32
1.8 V LVCMOS
2 mA
11
9
4 mA
22
17
1.5 V LVCMOS
2 mA
16
13
3.3 V LVCMOS Wide Range2
2.5 V LVCMOS
Notes:
1. TJ = 100°C
2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected
for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as
specified in the JESD-8B specification.
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-35 • Duration of Short Circuit Event Before Failure
Temperature
Time before Failure
–40°C
> 20 years
0°C
> 20 years
25°C
> 20 years
70°C
5 years
85°C
2 years
100°C
0.5 years
Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (min.)
Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS
No requirement
10 ns *
20 years (110°C)
LVDS/B-LVDS/
M-LVDS/LVPECL
No requirement
10 ns *
10 years (100°C)
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum
value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.
Microsemi recommends signal integrity evaluation/characterization of the system to ensure that
there is no excessive noise coupling into input signals.
R ev i si o n 1 5
2- 30
ProASIC3 Flash Family FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-37 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.8
2
3.6
0.4
2.4
2
2
27
25
10
10
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
4
27
25
10
10
6 mA
–0.3
0.8
2
3.6
0.4
2.4
6
6
54
51
10
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
8
54
51
10
10
12 mA
–0.3
0.8
2
3.6
0.4
2.4
12 12
109
103
10
10
16 mA
–0.3
0.8
2
3.6
0.4
2.4
16 16
127
132
10
10
24 mA
–0.3
0.8
2
3.6
0.4
2.4
24 24
181
268
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-38 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
µA4 µA4
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA
mA
Max.
mA3
Max.
mA3
2 mA
–0.3
0.8
2
3.6
0.4
2.4
2
2
27
25
10
10
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
4
27
25
10
10
6 mA
–0.3
0.8
2
3.6
0.4
2.4
6
6
54
51
10
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
8
54
51
10
10
12 mA
–0.3
0.8
2
3.6
0.4
2.4
12
12
109
103
10
10
16 mA
–0.3
0.8
2
3.6
0.4
2.4
16
16
109
103
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R ev i si o n 1 5
2- 31
ProASIC3 Flash Family FPGAs
Table 2-39 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.8
2
3.6
0.4
2.4
2
2
25
27
10
10
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
4
25
27
10
10
6 mA
–0.3
0.8
2
3.6
0.4
2.4
6
6
51
54
10
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
8
51
54
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R = 1 kΩ
Test Point
Enable Path
Test Point
Datapath
Figure 2-6 •
35 pF
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
AC Loading
Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
3.3
1.4
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
R ev i si o n 1 5
2- 32
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
7.66
0.04
1.02
0.43
7.80
6.59
2.65
2.61
10.03
8.82
ns
–1
0.56
6.51
0.04
0.86
0.36
6.63
5.60
2.25
2.22
8.54
7.51
ns
–2
0.49
5.72
0.03
0.76
0.32
5.82
4.92
1.98
1.95
7.49
6.59
ns
Std.
0.66
4.91
0.04
1.02
0.43
5.00
4.07
2.99
3.20
7.23
6.31
ns
–1
0.56
4.17
0.04
0.86
0.36
4.25
3.46
2.54
2.73
6.15
5.36
ns
–2
0.49
3.66
0.03
0.76
0.32
3.73
3.04
2.23
2.39
5.40
4.71
ns
Std.
0.66
4.91
0.04
1.02
0.43
5.00
4.07
2.99
3.20
7.23
6.31
ns
–1
0.56
4.17
0.04
0.86
0.36
4.25
3.46
2.54
2.73
6.15
5.36
ns
–2
0.49
3.66
0.03
0.76
0.32
3.73
3.04
2.23
2.39
5.40
4.71
ns
Std.
0.66
3.53
0.04
1.02
0.43
3.60
2.82
3.21
3.58
5.83
5.06
ns
–1
0.56
3.00
0.04
0.86
0.36
3.06
2.40
2.73
3.05
4.96
4.30
ns
–2
0.49
2.64
0.03
0.76
0.32
2.69
2.11
2.40
2.68
4.36
3.78
ns
Std.
0.66
3.33
0.04
1.02
0.43
3.39
2.56
3.26
3.68
5.63
4.80
ns
–1
0.56
2.83
0.04
0.86
0.36
2.89
2.18
2.77
3.13
4.79
4.08
ns
–2
0.49
2.49
0.03
0.76
0.32
2.53
1.91
2.44
2.75
4.20
3.58
ns
Std.
0.66
3.08
0.04
1.02
0.43
3.13
2.12
3.32
4.06
5.37
4.35
ns
–1
0.56
2.62
0.04
0.86
0.36
2.66
1.80
2.83
3.45
4.57
3.70
ns
–2
0.49
2.30
0.03
0.76
0.32
2.34
1.58
2.48
3.03
4.01
3.25
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 33
ProASIC3 Flash Family FPGAs
Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
10.26
0.04
1.02
0.43
10.45
8.90
2.64
2.46
12.68
11.13
ns
–1
0.56
8.72
0.04
0.86
0.36
8.89
7.57
2.25
2.09
10.79
9.47
ns
–2
0.49
7.66
0.03
0.76
0.32
7.80
6.64
1.98
1.83
9.47
8.31
ns
Std.
0.66
7.27
0.04
1.02
0.43
7.41
6.28
2.98
3.04
9.65
8.52
ns
–1
0.56
6.19
0.04
0.86
0.36
6.30
5.35
2.54
2.59
8.20
7.25
ns
–2
0.49
5.43
0.03
0.76
0.32
5.53
4.69
2.23
2.27
7.20
6.36
ns
Std.
0.66
7.27
0.04
1.02
0.43
7.41
6.28
2.98
3.04
9.65
8.52
ns
–1
0.56
6.19
0.04
0.86
0.36
6.30
5.35
2.54
2.59
8.20
7.25
ns
–2
0.49
5.43
0.03
0.76
0.32
5.53
4.69
2.23
2.27
7.20
6.36
ns
Std.
0.66
5.58
0.04
1.02
0.43
5.68
4.87
3.21
3.42
7.92
7.11
ns
–1
0.56
4.75
0.04
0.86
0.36
4.84
4.14
2.73
2.91
6.74
6.05
ns
–2
0.49
4.17
0.03
0.76
0.32
4.24
3.64
2.39
2.55
5.91
5.31
ns
Std.
0.66
5.21
0.04
1.02
0.43
5.30
4.56
3.26
3.51
7.54
6.80
ns
–1
0.56
4.43
0.04
0.86
0.36
4.51
3.88
2.77
2.99
6.41
5.79
ns
–2
0.49
3.89
0.03
0.76
0.32
3.96
3.41
2.43
2.62
5.63
5.08
ns
Std.
0.66
4.85
0.04
1.02
0.43
4.94
4.54
3.32
3.88
7.18
6.78
ns
–1
0.56
4.13
0.04
0.86
0.36
4.20
3.87
2.82
3.30
6.10
5.77
ns
–2
0.49
3.62
0.03
0.76
0.32
3.69
3.39
2.48
2.90
5.36
5.06
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 34
ProASIC3 Flash Family FPGAs
Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
16 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
7.20
0.04
1.00
0.43
7.34
6.29
2.27
2.34
9.57
8.52
ns
–1
0.56
6.13
0.04
0.85
0.36
6.24
5.35
1.93
1.99
8.14
7.25
ns
–2
0.49
5.38
0.03
0.75
0.32
5.48
4.69
1.70
1.75
7.15
6.36
ns
Std.
0.66
4.50
0.04
1.00
0.43
4.58
3.82
2.58
2.88
6.82
6.05
ns
–1
0.56
3.83
0.04
0.85
0.36
3.90
3.25
2.19
2.45
5.80
5.15
ns
–2
0.49
3.36
0.03
0.75
0.32
3.42
2.85
1.92
2.15
5.09
4.52
ns
Std.
0.66
4.50
0.04
1.00
0.43
4.58
3.82
2.58
2.88
6.82
6.05
ns
–1
0.56
3.83
0.04
0.85
0.36
3.90
3.25
2.19
2.45
5.80
5.15
ns
–2
0.49
3.36
0.03
0.75
0.32
3.42
2.85
1.92
2.15
5.09
4.52
ns
Std.
0.66
3.16
0.04
1.00
0.43
3.22
2.58
2.79
3.22
5.45
4.82
ns
–1
0.56
2.69
0.04
0.85
0.36
2.74
2.20
2.37
2.74
4.64
4.10
ns
–2
0.49
2.36
0.03
0.75
0.32
2.40
1.93
2.08
2.41
4.07
3.60
ns
Std.
0.66
3.16
0.04
1.00
0.43
3.22
2.58
2.79
3.22
5.45
4.82
ns
–1
0.56
2.69
0.04
0.85
0.36
2.74
2.20
2.37
2.74
4.64
4.10
ns
–2
0.49
2.36
0.03
0.75
0.32
2.40
1.93
2.08
2.41
4.07
3.60
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 35
ProASIC3 Flash Family FPGAs
Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
16 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
9.68
0.04
1.00
0.43
9.86
8.42
2.28
2.21
12.09
10.66
ns
–1
0.56
8.23
0.04
0.85
0.36
8.39
7.17
1.94
1.88
10.29
9.07
ns
–2
0.49
7.23
0.03
0.75
0.32
7.36
6.29
1.70
1.65
9.03
7.96
ns
Std.
0.66
6.70
0.04
1.00
0.43
6.82
5.89
2.58
2.74
9.06
8.12
ns
–1
0.56
5.70
0.04
0.85
0.36
5.80
5.01
2.20
2.33
7.71
6.91
ns
–2
0.49
5.00
0.03
0.75
0.32
5.10
4.40
1.93
2.05
6.76
6.06
ns
Std.
0.66
6.70
0.04
1.00
0.43
6.82
5.89
2.58
2.74
9.06
8.12
ns
–1
0.56
5.70
0.04
0.85
0.36
5.80
5.01
2.20
2.33
7.71
6.91
ns
–2
0.49
5.00
0.03
0.75
0.32
5.10
4.40
1.93
2.05
6.76
6.06
ns
Std.
0.66
5.05
0.04
1.00
0.43
5.14
4.51
2.79
3.08
7.38
6.75
ns
–1
0.56
4.29
0.04
0.85
0.36
4.37
3.84
2.38
2.62
6.28
5.74
ns
–2
0.49
3.77
0.03
0.75
0.32
3.84
3.37
2.09
2.30
5.51
5.04
ns
Std.
0.66
5.05
0.04
1.00
0.43
5.14
4.51
2.79
3.08
7.38
6.75
ns
–1
0.56
4.29
0.04
0.85
0.36
4.37
3.84
2.38
2.62
6.28
5.74
ns
–2
0.49
3.77
0.03
0.75
0.32
3.84
3.37
2.09
2.30
5.51
5.04
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Speed
Grade
tDOUT
tDP
tDIN
Std.
0.66
7.07
0.04
–1
0.56
6.01
0.04
–2
0.49
5.28
0.03
Std.
0.66
7.07
–1
0.56
–2
0.49
Std.
–1
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
1.00
0.43
7.20
6.23
2.07
2.15
ns
0.85
0.36
6.12
5.30
1.76
1.83
ns
0.75
0.32
5.37
4.65
1.55
1.60
ns
0.04
1.00
0.43
7.20
6.23
2.07
2.15
ns
6.01
0.04
0.85
0.36
6.12
5.30
1.76
1.83
ns
5.28
0.03
0.75
0.32
5.37
4.65
1.55
1.60
ns
0.66
4.41
0.04
1.00
0.43
4.49
3.75
2.39
2.69
ns
0.56
3.75
0.04
0.85
0.36
3.82
3.19
2.04
2.29
ns
–2
0.49
3.29
0.03
0.75
0.32
3.36
2.80
1.79
2.01
ns
Std.
0.66
4.41
0.04
1.00
0.43
4.49
3.75
2.39
2.69
ns
–1
0.56
3.75
0.04
0.85
0.36
3.82
3.19
2.04
2.29
ns
–2
0.49
3.29
0.03
0.75
0.32
3.36
2.80
1.79
2.01
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 36
ProASIC3 Flash Family FPGAs
Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.66
9.46
0.04
1.00
0.43
9.64
8.54
2.07
2.04
ns
–1
0.56
8.05
0.04
0.85
0.36
8.20
7.27
1.76
1.73
ns
–2
0.49
7.07
0.03
0.75
0.32
7.20
6.38
1.55
1.52
ns
Std.
0.66
9.46
0.04
1.00
0.43
9.64
8.54
2.07
2.04
ns
–1
0.56
8.05
0.04
0.85
0.36
8.20
7.27
1.76
1.73
ns
–2
0.49
7.07
0.03
0.75
0.32
7.20
6.38
1.55
1.52
ns
Std.
0.66
6.57
0.04
1.00
0.43
6.69
5.98
2.40
2.57
ns
–1
0.56
5.59
0.04
0.85
0.36
5.69
5.09
2.04
2.19
ns
–2
0.49
4.91
0.03
0.75
0.32
5.00
4.47
1.79
1.92
ns
Std.
0.66
6.57
0.04
1.00
0.43
6.69
5.98
2.40
2.57
ns
–1
0.56
5.59
0.04
0.85
0.36
5.69
5.09
2.04
2.19
ns
–2
0.49
4.91
0.03
0.75
0.32
5.00
4.47
1.79
1.92
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 37
ProASIC3 Flash Family FPGAs
3.3 V LVCMOS Wide Range
Table 2-47 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V
Equiv.
LVCMOS
Software
Wide Range Default
Drive
Drive
Strength
Strength
Option1
Min.
V
Max.
V
Min.
V
100 µA
2 mA
–0.3
0.8
100 µA
4 mA
–0.3
100 µA
6 mA
100 µA
100 µA
100 µA
100 µA
IOSL
IOSH
IIL2 IIH3
Max.
mA4
Max.
mA4
µA5 µA5
VDD – 0.2 100 100
25
27
10 10
0.2
VDD – 0.2 100 100
25
27
10 10
3.6
0.2
VDD – 0.2 100 100
51
54
10 10
2
3.6
0.2
VDD – 0.2 100 100
51
54
10 10
2
3.6
0.2
VDD – 0.2 100 100
103
109
10 10
0.8
2
3.6
0.2
VDD – 0.2 100 100
132
127
10 10
0.8
2
3.6
0.2
VDD – 0.2 100 100
268
181
10 10
VIL
VIH
VOL
VOH
Max.
V
Max.
V
Min.
V
2
3.6
0.2
0.8
2
3.6
–0.3
0.8
2
8 mA
–0.3
0.8
12 mA
–0.3
0.8
16 mA
–0.3
24 mA
–0.3
IOL IOH
µA
µA
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 85°C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
Table 2-48 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVCMOS
Wide Range
Equiv.
Software
Default
Drive
Strength
Option1
Min.
V
Max.
V
100 µA
2 mA
–0.3
0.8
2
100 µA
4 mA
–0.3
0.8
100 µA
6 mA
–0.3
100 µA
8 mA
100 µA
12 mA
100 μA
16 mA
Drive Strength
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL2 IIH3
Min. Max.
V
V
Max.
V
Min.
V
µA
Max.
mA4
Max.
mA4
µA5 µA5
3.6
0.2
VDD – 0.2
100 100
25
27
10 10
2
3.6
0.2
VDD – 0.2
100 100
25
27
10 10
0.8
2
3.6
0.2
VDD – 0.2
100 100
51
54
10 10
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100 100
51
54
10 10
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100 100
103
109
10 10
–0.3
0.8
2
3.6
0.2
VDD – 0.2
100 100
103
109
10 10
VIL
µA
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 85°C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
R ev i si o n 1 5
2- 38
ProASIC3 Flash Family FPGAs
Table 2-49 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
3.3 V
LVCMOS
Wide Range
Drive
Strength
Equiv.
Software
VIL
Default
Drive
Strength Min. Max.
V
V
Option1
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL2 IIH3
Min.
V
µA µA
Max.
mA4
Max.
mA4
µA5 µA5
Min.
V
Max.
V
Max.
V
100 µA
2 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
25
27
10 10
100 µA
4 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
25
27
10 10
100 µA
6 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
51
54
10 10
100 µA
8 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
51
54
10 10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 85°C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
R ev i si o n 1 5
2- 39
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Equiv.
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
4 mA
Std.
6 mA
8 mA
12 mA
16 mA
24 mA
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
0.60
11.84 0.04 1.02
0.43
11.84 10.00 4.10 4.04 15.23 13.40
ns
–1
0.51
10.07 0.04 0.86
0.36
10.07
8.51
3.48 3.44 12.96 11.40
ns
–2
0.45
8.84
0.03 0.76
0.32
8.84
7.47
3.06 3.02 11.38 10.00
ns
Std.
0.60
7.59
0.04 1.02
0.43
7.59
6.18
4.62 4.95 10.98
9.57
ns
–1
0.51
6.45
0.04 0.86
0.36
6.45
5.25
3.93 4.21
9.34
8.14
ns
–2
0.45
5.67
0.03 0.76
0.32
5.67
4.61
3.45 3.70
8.20
7.15
ns
Std.
0.60
7.59
0.04 1.02
0.43
7.59
6.18
4.62 4.95 10.98
9.57
ns
–1
0.51
6.45
0.04 0.86
0.36
6.45
5.25
3.93 4.21
9.34
8.14
ns
–2
0.45
5.67
0.03 0.76
0.32
5.67
4.61
3.45 3.70
8.20
7.15
ns
Std.
0.60
5.46
0.04 1.02
0.43
5.46
4.29
4.97 5.54
8.86
7.68
ns
–1
0.51
4.65
0.04 0.86
0.36
4.65
3.65
4.22 4.71
7.53
6.54
ns
–2
0.45
4.08
0.03 0.76
0.32
4.08
3.20
3.71 4.14
6.61
5.74
ns
Std.
0.60
5.15
0.04 1.02
0.43
5.15
3.89
5.04 5.69
8.55
7.29
ns
–1
0.51
4.38
0.04 0.86
0.36
4.38
3.31
4.29 4.84
7.27
6.20
ns
–2
0.45
3.85
0.03 0.76
0.32
3.85
2.91
3.77 4.25
6.38
5.44
ns
Std.
0.60
4.75
0.04 1.02
0.43
4.75
3.22
5.14 6.28
8.15
6.61
ns
–1
0.51
4.04
0.04 0.86
0.36
4.04
2.74
4.37 5.34
6.93
5.62
ns
–2
0.45
3.55
0.03 0.76
0.32
3.55
2.40
3.84 4.69
6.09
4.94
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 40
ProASIC3 Flash Family FPGAs
Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Equiv.
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
2 mA
Std.
4 mA
6 mA
8 mA
16 mA
24 mA
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
0.60
15.86 0.04 1.54
0.43
15.86 13.51 4.09 3.80 19.25 16.90
ns
–1
0.51
13.49 0.04 1.31
0.36
13.49 11.49 3.48 3.23 16.38 14.38
ns
–2
0.45
11.84 0.03 1.15
0.32
11.84 10.09 3.05 2.84 14.38 12.62
ns
Std.
0.60
11.25 0.04 1.54
0.43
11.25
9.54
4.61 4.70 14.64 12.93
ns
–1
0.51
9.57
0.04 1.31
0.36
9.57
8.11
3.92 4.00 12.46 11.00
ns
–2
0.45
8.40
0.03 1.15
0.32
8.40
7.12
3.44 3.51 10.93
9.66
ns
Std.
0.60
11.25 0.04 1.54
0.43
11.25
9.54
4.61 4.70 14.64 12.93
ns
–1
0.51
9.57
0.04 1.31
0.36
9.57
8.11
3.92 4.00 12.46 11.00
ns
–2
0.45
8.40
0.03 1.15
0.32
8.40
7.12
3.44 3.51 10.93
9.66
ns
Std.
0.60
8.63
0.04 1.54
0.43
8.63
7.39
4.96 5.28 12.02 10.79
ns
–1
0.51
7.34
0.04 1.31
0.36
7.34
6.29
4.22 4.49 10.23
9.18
ns
–2
0.45
6.44
0.03 1.15
0.32
6.44
5.52
3.70 3.94
8.06
ns
Std.
0.60
8.05
0.04 1.54
0.43
8.05
6.93
5.03 5.43 11.44 10.32
ns
–1
0.51
6.85
0.04 1.31
0.36
6.85
5.90
4.28 4.62
9.74
8.78
ns
–2
0.45
6.01
0.03 1.15
0.32
6.01
5.18
3.76 4.06
8.55
7.71
ns
Std.
0.60
7.50
0.04 1.54
0.43
7.50
6.90
5.13 6.00 10.89 10.29
ns
–1
0.51
6.38
0.04 1.31
0.36
6.38
5.87
4.36 5.11
9.27
8.76
ns
–2
0.45
5.60
0.03 1.15
0.32
5.60
5.15
3.83 4.48
8.13
7.69
ns
8.98
tZHS Units
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 41
ProASIC3 Flash Family FPGAs
Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
Equiv.
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
2 mA
Std.
4 mA
6 mA
8 mA
16 mA
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
0.60
11.14 0.04 1.52
0.43
11.14
9.54
3.51 3.61 14.53 12.94
ns
–1
0.51
9.48
0.04 1.29
0.36
9.48
8.12
2.99 3.07 12.36 11.00
ns
–2
0.45
8.32
0.03 1.14
0.32
8.32
7.13
2.62 2.70 10.85
9.66
ns
Std.
0.60
6.96
0.04 1.52
0.43
6.96
5.79
3.99 4.45 10.35
9.19
ns
–1
0.51
5.92
0.04 1.29
0.36
5.92
4.93
3.39 3.78
8.81
7.82
ns
–2
0.45
5.20
0.03 1.14
0.32
5.20
4.33
2.98 3.32
7.73
6.86
ns
Std.
0.60
6.96
0.04 1.52
0.43
6.96
5.79
3.99 4.45 10.35
9.19
ns
–1
0.51
5.92
0.04 1.29
0.36
5.92
4.93
3.39 3.78
8.81
7.82
ns
–2
0.45
5.20
0.03 1.14
0.32
5.20
4.33
2.98 3.32
7.73
6.86
ns
Std.
0.60
4.89
0.04 1.52
0.43
4.89
3.92
4.31 4.98
8.28
7.32
ns
–1
0.51
4.16
0.04 1.29
0.36
4.16
3.34
3.67 4.24
7.04
6.22
ns
–2
0.45
3.65
0.03 1.14
0.32
3.65
2.93
3.22 3.72
6.18
5.46
ns
Std.
0.60
4.89
0.04 1.52
0.43
4.89
3.92
4.31 4.98
8.28
7.32
ns
–1
0.51
4.16
0.04 1.29
0.36
4.16
3.34
3.67 4.24
7.04
6.22
ns
–2
0.45
3.65
0.03 1.14
0.32
3.65
2.93
3.22 3.72
6.18
5.46
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 42
ProASIC3 Flash Family FPGAs
Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
Equiv.
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
2 mA
Std.
4 mA
6 mA
8 mA
16 mA
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
0.60
14.97 0.04 1.52
0.43
14.97 12.79 3.52 3.41 18.36 16.18
ns
–1
0.51
12.73 0.04 1.29
0.36
12.73 10.88 2.99 2.90 15.62 13.77
ns
–2
0.45
11.18 0.03 1.14
0.32
11.18
9.55
2.63 2.55 13.71 12.08
ns
Std.
0.60
10.36 0.04 1.52
0.43
10.36
8.93
3.99 4.24 13.75 12.33
ns
–1
0.51
8.81
0.04 1.29
0.36
8.81
7.60
3.39 3.60 11.70 10.49
ns
–2
0.45
7.74
0.03 1.14
0.32
7.74
6.67
2.98 3.16 10.27
9.21
ns
Std.
0.60
10.36 0.04 1.52
0.43
10.36
8.93
3.99 4.24 13.75 12.33
ns
–1
0.51
8.81
0.04 1.29
0.36
8.81
7.60
3.39 3.60 11.70 10.49
ns
–2
0.45
7.74
0.03 1.14
0.32
7.74
6.67
2.98 3.16 10.27
9.21
ns
Std.
0.60
7.81
0.04 1.52
0.43
7.81
6.85
4.32 4.76 11.20 10.24
ns
–1
0.51
6.64
0.04 1.29
0.36
6.64
5.82
3.67 4.05
9.53
8.71
ns
–2
0.45
5.83
0.03 1.14
0.32
5.83
5.11
3.22 3.56
8.36
7.65
ns
Std.
0.60
7.81
0.04 1.52
0.43
7.81
6.85
4.32 4.76 11.20 10.24
ns
–1
0.51
6.64
0.04 1.29
0.36
6.64
5.82
3.67 4.05
9.53
8.71
ns
–2
0.45
5.83
0.03 1.14
0.32
5.83
5.11
3.22 3.56
8.36
7.65
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 43
ProASIC3 Flash Family FPGAs
Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Equiv.
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
10.93
0.04
1.52
0.43
10.93
9.46
3.20
3.32
ns
–1
0.51
9.29
0.04
1.29
0.36
9.29
8.04
2.72
2.82
ns
–2
0.45
8.16
0.03
1.13
0.32
8.16
7.06
2.39
2.48
ns
Std.
0.60
10.93
0.04
1.52
0.43
10.93
9.46
3.20
3.32
ns
–1
0.51
9.29
0.04
1.29
0.36
9.29
8.04
2.72
2.82
ns
–2
0.45
8.16
0.03
1.13
0.32
8.16
7.06
2.39
2.48
ns
Std.
0.60
6.82
0.04
1.52
0.43
6.82
5.70
3.70
4.16
ns
–1
0.51
5.80
0.04
1.29
0.36
5.80
4.85
3.15
3.54
ns
–2
0.45
5.09
0.03
1.13
0.32
5.09
4.25
2.77
3.11
ns
Std.
0.60
6.82
0.04
1.52
0.43
6.82
5.70
3.70
4.16
ns
–1
0.51
5.80
0.04
1.29
0.36
5.80
4.85
3.15
3.54
ns
–2
0.45
5.09
0.03
1.13
0.32
5.09
4.25
2.77
3.11
ns
4 mA
6 mA
8 mA
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 44
ProASIC3 Flash Family FPGAs
Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Equiv.
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
14.64
0.04
1.52
0.43
14.64
12.97
3.21
3.15
ns
–1
0.51
12.45
0.04
1.29
0.36
12.45
11.04
2.73
2.68
ns
–2
0.45
10.93
0.03
1.13
0.32
10.93
9.69
2.39
2.35
ns
Std.
0.60
14.64
0.04
1.52
0.43
14.64
12.97
3.21
3.15
ns
–1
0.51
12.45
0.04
1.29
0.36
12.45
11.04
2.73
2.68
ns
–2
0.45
10.93
0.03
1.13
0.32
10.93
9.69
2.39
2.35
ns
Std.
0.60
10.16
0.04
1.52
0.43
10.16
9.08
3.71
3.98
ns
–1
0.51
8.64
0.04
1.29
0.36
8.64
7.73
3.15
3.39
ns
–2
0.45
7.58
0.03
1.13
0.32
7.58
6.78
2.77
2.97
ns
Std.
0.60
10.16
0.04
1.52
0.43
10.16
9.08
3.71
3.98
ns
–1
0.51
8.64
0.04
1.29
0.36
8.64
7.73
3.15
3.39
ns
–2
0.45
7.58
0.03
1.13
0.32
7.58
6.78
2.77
2.97
ns
4 mA
6 mA
8 mA
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 45
ProASIC3 Flash Family FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications.
Table 2-56 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
2.5 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.7
1.7
2.7
0.7
1.7
2
2
18
16
10
10
4 mA
–0.3
0.7
1.7
2.7
0.7
1.7
4
4
18
16
10
10
6 mA
–0.3
0.7
1.7
2.7
0.7
1.7
6
6
37
32
10
10
8 mA
–0.3
0.7
1.7
2.7
0.7
1.7
8
8
37
32
10
10
12 mA
–0.3
0.7
1.7
2.7
0.7
1.7
12 12
74
65
10
10
16 mA
–0.3
0.7
1.7
2.7
0.7
1.7
16 16
87
83
10
10
24 mA
–0.3
0.7
1.7
2.7
0.7
1.7
24 24
124
169
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-57 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
2.5 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.7
1.7
2.7
0.7
1.7
2
2
18
16
10
10
4 mA
–0.3
0.7
1.7
2.7
0.7
1.7
4
4
18
16
10
10
6 mA
–0.3
0.7
1.7
2.7
0.7
1.7
6
6
37
32
10
10
8 mA
–0.3
0.7
1.7
2.7
0.7
1.7
8
8
37
32
10
10
12 mA
–0.3
0.7
1.7
2.7
0.7
1.7
12
12
74
65
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R ev i si o n 1 5
2- 46
ProASIC3 Flash Family FPGAs
Table 2-58 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
2.5 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
16
18
Drive Strength
Min.
V
Max.,
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.7
1.7
3.6
0.7
1.7
2
2
10
10
4 mA
–0.3
0.7
1.7
3.6
0.7
1.7
4
4
16
18
10
10
6 mA
–0.3
0.7
1.7
3.6
0.7
1.7
6
6
32
37
10
10
8 mA
–0.3
0.7
1.7
3.6
0.7
1.7
8
8
32
37
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R = 1 kΩ
Test Point
Enable Path
Test Point
Datapath
Figure 2-7 •
35 pF
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
AC Loading
Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
2.5
1.2
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
R ev i si o n 1 5
2- 47
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-60 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.60
8.66
0.04
1.31
0.43
7.83
8.66
2.68
2.30
10.07
10.90
ns
–1
0.51
7.37
0.04
1.11
0.36
6.66
7.37
2.28
1.96
8.56
9.27
ns
–2
0.45
6.47
0.03
0.98
0.32
5.85
6.47
2.00
1.72
7.52
8.14
ns
Std.
0.60
5.17
0.04
1.31
0.43
5.04
5.17
3.05
3.00
7.27
7.40
ns
–1
0.51
4.39
0.04
1.11
0.36
4.28
4.39
2.59
2.55
6.19
6.30
ns
–2
0.45
3.86
0.03
0.98
0.32
3.76
3.86
2.28
2.24
5.43
5.53
ns
Std.
0.60
5.17
0.04
1.31
0.43
5.04
5.17
3.05
3.00
7.27
7.40
ns
–1
0.51
4.39
0.04
1.11
0.36
4.28
4.39
2.59
2.55
6.19
6.30
ns
–2
0.45
3.86
0.03
0.98
0.32
3.76
3.86
2.28
2.24
5.43
5.53
ns
Std.
0.60
3.56
0.04
1.31
0.43
3.63
3.43
3.30
3.44
5.86
5.67
ns
–1
0.51
3.03
0.04
1.11
0.36
3.08
2.92
2.81
2.92
4.99
4.82
ns
–2
0.45
2.66
0.03
0.98
0.32
2.71
2.56
2.47
2.57
4.38
4.23
ns
Std.
0.60
3.35
0.04
1.31
0.43
3.41
3.06
3.36
3.55
5.65
5.30
ns
–1
0.51
2.85
0.04
1.11
0.36
2.90
2.60
2.86
3.02
4.81
4.51
ns
–2
0.45
2.50
0.03
0.98
0.32
2.55
2.29
2.51
2.65
4.22
3.96
ns
Std.
0.60
3.09
0.04
1.31
0.43
3.15
2.44
3.44
4.00
5.38
4.68
ns
–1
0.51
2.63
0.04
1.11
0.36
2.68
2.08
2.92
3.40
4.58
3.98
ns
–2
0.45
2.31
0.03
0.98
0.32
2.35
1.82
2.57
2.98
4.02
3.49
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 48
ProASIC3 Flash Family FPGAs
Table 2-61 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.60
11.40
0.04
1.31
0.43
11.22
11.40
2.68
2.20
13.45
13.63
ns
–1
0.51
9.69
0.04
1.11
0.36
9.54
9.69
2.28
1.88
11.44
11.60
ns
–2
0.45
8.51
0.03
0.98
0.32
8.38
8.51
2.00
1.65
10.05
10.18
ns
Std.
0.60
7.96
0.04
1.31
0.43
8.11
7.81
3.05
2.89
10.34
10.05
ns
–1
0.51
6.77
0.04
1.11
0.36
6.90
6.65
2.59
2.46
8.80
8.55
ns
–2
0.45
5.94
0.03
0.98
0.32
6.05
5.84
2.28
2.16
7.72
7.50
ns
Std.
0.60
7.96
0.04
1.31
0.43
8.11
7.81
3.05
2.89
10.34
10.05
ns
–1
0.51
6.77
0.04
1.11
0.36
6.90
6.65
2.59
2.46
8.80
8.55
ns
–2
0.45
5.94
0.03
0.98
0.32
6.05
5.84
2.28
2.16
7.72
7.50
ns
Std.
0.60
6.18
0.04
1.31
0.43
6.29
5.92
3.30
3.32
8.53
8.15
ns
–1
0.51
5.26
0.04
1.11
0.36
5.35
5.03
2.81
2.83
7.26
6.94
ns
–2
0.45
4.61
0.03
0.98
0.32
4.70
4.42
2.47
2.48
6.37
6.09
ns
Std.
0.60
5.76
0.04
1.31
0.43
5.87
5.53
3.36
3.44
8.11
7.76
ns
–1
0.51
4.90
0.04
1.11
0.36
4.99
4.70
2.86
2.92
6.90
6.60
ns
–2
0.45
4.30
0.03
0.98
0.32
4.38
4.13
2.51
2.57
6.05
5.80
ns
Std.
0.60
5.51
0.04
1.31
0.43
5.50
5.51
3.43
3.87
7.74
7.74
ns
–1
0.51
4.68
0.04
1.11
0.36
4.68
4.68
2.92
3.29
6.58
6.59
ns
–2
0.45
4.11
0.03
0.98
0.32
4.11
4.11
2.56
2.89
5.78
5.78
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 49
ProASIC3 Flash Family FPGAs
Table 2-62 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
8.28
0.04
1.30
0.43
7.41
8.28
2.25
2.07
9.64
10.51
ns
–1
0.56
7.04
0.04
1.10
0.36
6.30
7.04
1.92
1.76
8.20
8.94
ns
–2
0.49
6.18
0.03
0.97
0.32
5.53
6.18
1.68
1.55
7.20
7.85
ns
Std.
0.66
4.85
0.04
1.30
0.43
4.65
4.85
2.59
2.71
6.88
7.09
ns
–1
0.56
4.13
0.04
1.10
0.36
3.95
4.13
2.20
2.31
5.85
6.03
ns
–2
0.49
3.62
0.03
0.97
0.32
3.47
3.62
1.93
2.02
5.14
5.29
ns
Std.
0.66
4.85
0.04
1.30
0.43
4.65
4.85
2.59
2.71
6.88
7.09
ns
–1
0.56
4.13
0.04
1.10
0.36
3.95
4.13
2.20
2.31
5.85
6.03
ns
–2
0.49
3.62
0.03
0.97
0.32
3.47
3.62
1.93
2.02
5.14
5.29
ns
Std.
0.66
3.21
0.04
1.30
0.43
3.27
3.14
2.82
3.11
5.50
5.38
ns
–1
0.56
2.73
0.04
1.10
0.36
2.78
2.67
2.40
2.65
4.68
4.57
ns
–2
0.49
2.39
0.03
0.97
0.32
2.44
2.35
2.11
2.32
4.11
4.02
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-63 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Strength
4 mA
6 mA
8 mA
12 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
10.84
0.04
1.30
0.43
10.64
10.84
2.26
1.99
12.87
13.08
ns
–1
0.56
9.22
0.04
1.10
0.36
9.05
9.22
1.92
1.69
10.95
11.12
ns
–2
0.49
8.10
0.03
0.97
0.32
7.94
8.10
1.68
1.49
9.61
9.77
ns
Std.
0.66
7.37
0.04
1.30
0.43
7.50
7.36
2.59
2.61
9.74
9.60
ns
–1
0.56
6.27
0.04
1.10
0.36
6.38
6.26
2.20
2.22
8.29
8.16
ns
–2
0.49
5.50
0.03
0.97
0.32
5.60
5.50
1.93
1.95
7.27
7.17
ns
Std.
0.66
7.37
0.04
1.30
0.43
7.50
7.36
2.59
2.61
9.74
9.60
ns
–1
0.56
6.27
0.04
1.10
0.36
6.38
6.26
2.20
2.22
8.29
8.16
ns
–2
0.49
5.50
0.03
0.97
0.32
5.60
5.50
1.93
1.95
7.27
7.17
ns
Std.
0.66
5.63
0.04
1.30
0.43
5.73
5.51
2.83
3.01
7.97
7.74
ns
–1
0.56
4.79
0.04
1.10
0.36
4.88
4.68
2.41
2.56
6.78
6.59
ns
–2
0.49
4.20
0.03
0.97
0.32
4.28
4.11
2.11
2.25
5.95
5.78
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 50
ProASIC3 Flash Family FPGAs
Table 2-64 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.66
8.20
0.04
1.29
0.43
7.24
8.20
2.03
1.91
ns
–1
0.56
6.98
0.04
1.10
0.36
6.16
6.98
1.73
1.62
ns
–2
0.49
6.13
0.03
0.96
0.32
5.41
6.13
1.52
1.43
ns
Std.
0.66
8.20
0.04
1.29
0.43
7.24
8.20
2.03
1.91
ns
–1
0.56
6.98
0.04
1.10
0.36
6.16
6.98
1.73
1.62
ns
–2
0.49
6.13
0.03
0.96
0.32
5.41
6.13
1.52
1.43
ns
Std.
0.66
4.77
0.04
1.29
0.43
4.55
4.77
2.38
2.55
ns
–1
0.56
4.05
0.04
1.10
0.36
3.87
4.05
2.03
2.17
ns
–2
0.49
3.56
0.03
0.96
0.32
3.40
3.56
1.78
1.91
ns
Std.
0.66
4.77
0.04
1.29
0.43
4.55
4.77
2.38
2.55
ns
–1
0.56
4.05
0.04
1.10
0.36
3.87
4.05
2.03
2.17
ns
–2
0.49
3.56
0.03
0.96
0.32
3.40
3.56
1.78
1.91
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-65 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.66
11.00
0.04
1.29
0.43
10.37
11.00
2.03
1.83
ns
–1
0.56
9.35
0.04
1.10
0.36
8.83
9.35
1.73
1.56
ns
–2
0.49
8.21
0.03
0.96
0.32
7.75
8.21
1.52
1.37
ns
Std.
0.66
11.00
0.04
1.29
0.43
10.37
11.00
2.03
1.83
ns
–1
0.56
9.35
0.04
1.10
0.36
8.83
9.35
1.73
1.56
ns
–2
0.49
8.21
0.03
0.96
0.32
7.75
8.21
1.52
1.37
ns
Std.
0.66
7.50
0.04
1.29
0.43
7.36
7.50
2.39
2.46
ns
–1
0.56
6.38
0.04
1.10
0.36
6.26
6.38
2.03
2.10
ns
–2
0.49
5.60
0.03
0.96
0.32
5.49
5.60
1.78
1.84
ns
Std.
0.66
7.50
0.04
1.29
0.43
7.36
7.50
2.39
2.46
ns
–1
0.56
6.38
0.04
1.10
0.36
6.26
6.38
2.03
2.10
ns
–2
0.49
5.60
0.03
0.96
0.32
5.49
5.60
1.78
1.84
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 51
ProASIC3 Flash Family FPGAs
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-66 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL1 IIH2
mA mA
Max.
mA3
Max.
mA3 µA4 µA4
Drive
Strength
Min.
V
Max.,
V
Min.
V
Max.
V
Max.
V
Min.
V
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
2
2
11
9
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
4
4
22
17
10
10
6 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
6
6
44
35
10
10
8 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45
8
8
51
45
10
10
12 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45 12 12
74
91
10
10
16 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.9
0.45
VCCI – 0.45 16 16
74
91
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-67 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL
mA mA
Max.
mA3
IOSH IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
2
2
11
9
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
4
4
22
17
10
10
6 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
6
6
44
35
10
10
8 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
8
8
44
35
10
10
µA4 µA4
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R ev i si o n 1 5
2- 52
ProASIC3 Flash Family FPGAs
Table 2-68 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.8 V
LVCMOS
VIL
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
Max. Max.
V
V
Min.
V
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
VIH
Drive
Strength
Min.
V
Max.
V
Min.
V
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
2
2
9
11
10
10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
4
4
17
22
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R = 1 kΩ
Test Point
Enable Path
Test Point
Datapath
Figure 2-8 •
35 pF
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
AC Loading
Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
1.8
0.9
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
R ev i si o n 1 5
2- 53
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-70 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
11.86
0.04
1.22
0.43
9.14
11.86
2.77
1.66
11.37
14.10
ns
–1
0.56
10.09
0.04
1.04
0.36
7.77
10.09
2.36
1.41
9.67
11.99
ns
–2
0.49
8.86
0.03
0.91
0.32
6.82
8.86
2.07
1.24
8.49
10.53
ns
Std.
0.66
6.91
0.04
1.22
0.43
5.86
6.91
3.22
2.84
8.10
9.15
ns
–1
0.56
5.88
0.04
1.04
0.36
4.99
5.88
2.74
2.41
6.89
7.78
ns
–2
0.49
5.16
0.03
0.91
0.32
4.38
5.16
2.41
2.12
6.05
6.83
ns
Std.
0.66
4.45
0.04
1.22
0.43
4.18
4.45
3.53
3.38
6.42
6.68
ns
–1
0.56
3.78
0.04
1.04
0.36
3.56
3.78
3.00
2.88
5.46
5.69
ns
–2
0.49
3.32
0.03
0.91
0.32
3.12
3.32
2.64
2.53
4.79
4.99
ns
Std.
0.66
3.92
0.04
1.22
0.43
3.93
3.92
3.60
3.52
6.16
6.16
ns
–1
0.56
3.34
0.04
1.04
0.36
3.34
3.34
3.06
3.00
5.24
5.24
ns
–2
0.49
2.93
0.03
0.91
0.32
2.93
2.93
2.69
2.63
4.60
4.60
ns
Std.
0.66
3.53
0.04
1.22
0.43
3.60
3.04
3.70
4.08
5.84
5.28
ns
–1
0.56
3.01
0.04
1.04
0.36
3.06
2.59
3.15
3.47
4.96
4.49
ns
–2
0.49
2.64
0.03
0.91
0.32
2.69
2.27
2.76
3.05
4.36
3.94
ns
Std.
0.66
3.53
0.04
1.22
0.43
3.60
3.04
3.70
4.08
5.84
5.28
ns
–1
0.56
3.01
0.04
1.04
0.36
3.06
2.59
3.15
3.47
4.96
4.49
ns
–2
0.49
2.64
0.03
0.91
0.32
2.69
2.27
2.76
3.05
4.36
3.94
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 54
ProASIC3 Flash Family FPGAs
Table 2-71 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
15.53
0.04
1.22
0.43
14.11
15.53
2.78
1.60
16.35
17.77
ns
–1
0.56
13.21
0.04
1.04
0.36
12.01
13.21
2.36
1.36
13.91
15.11
ns
–2
0.49
11.60
0.03
0.91
0.32
10.54
11.60
2.07
1.19
12.21
13.27
ns
Std.
0.66
10.48
0.04
1.22
0.43
10.41
10.48
3.23
2.73
12.65
12.71
ns
–1
0.56
8.91
0.04
1.04
0.36
8.86
8.91
2.75
2.33
10.76
10.81
ns
–2
0.49
7.82
0.03
0.91
0.32
7.77
7.82
2.41
2.04
9.44
9.49
ns
Std.
0.66
8.05
0.04
1.22
0.43
8.20
7.84
3.54
3.27
10.43
10.08
ns
–1
0.56
6.85
0.04
1.04
0.36
6.97
6.67
3.01
2.78
8.88
8.57
ns
–2
0.49
6.01
0.03
0.91
0.32
6.12
5.86
2.64
2.44
7.79
7.53
ns
Std.
0.66
7.50
0.04
1.22
0.43
7.64
7.30
3.61
3.41
9.88
9.53
ns
–1
0.56
6.38
0.04
1.04
0.36
6.50
6.21
3.07
2.90
8.40
8.11
ns
–2
0.49
5.60
0.03
0.91
0.32
5.71
5.45
2.69
2.55
7.38
7.12
ns
Std.
0.66
7.29
0.04
1.22
0.43
7.23
7.29
3.71
3.95
9.47
9.53
ns
–1
0.56
6.20
0.04
1.04
0.36
6.15
6.20
3.15
3.36
8.06
8.11
ns
–2
0.49
5.45
0.03
0.91
0.32
5.40
5.45
2.77
2.95
7.07
7.12
ns
Std.
0.66
7.29
0.04
1.22
0.43
7.23
7.29
3.71
3.95
9.47
9.53
ns
–1
0.56
6.20
0.04
1.04
0.36
6.15
6.20
3.15
3.36
8.06
8.11
ns
–2
0.49
5.45
0.03
0.91
0.32
5.40
5.45
2.77
2.95
7.07
7.12
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 55
ProASIC3 Flash Family FPGAs
Table 2-72 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
11.33
0.04
1.20
0.43
8.72
11.33
2.24
1.52
10.96
13.57
ns
–1
0.56
9.64
0.04
1.02
0.36
7.42
9.64
1.91
1.29
9.32
11.54
ns
–2
0.49
8.46
0.03
0.90
0.32
6.51
8.46
1.68
1.14
8.18
10.13
ns
Std.
0.66
6.48
0.04
1.20
0.43
5.48
6.48
2.65
2.60
7.72
8.72
ns
–1
0.56
5.51
0.04
1.02
0.36
4.66
5.51
2.25
2.21
6.56
7.42
ns
–2
0.49
4.84
0.03
0.90
0.32
4.09
4.84
1.98
1.94
5.76
6.51
ns
Std.
0.66
4.06
0.04
1.20
0.43
3.84
4.06
2.93
3.10
6.07
6.30
ns
–1
0.56
3.45
0.04
1.02
0.36
3.27
3.45
2.49
2.64
5.17
5.36
ns
–2
0.49
3.03
0.03
0.90
0.32
2.87
3.03
2.19
2.32
4.54
4.70
ns
Std.
0.66
4.06
0.04
1.20
0.43
3.84
4.06
2.93
3.10
6.07
6.30
ns
–1
0.56
3.45
0.04
1.02
0.36
3.27
3.45
2.49
2.64
5.17
5.36
ns
–2
0.49
3.03
0.03
0.90
0.32
2.87
3.03
2.19
2.32
4.54
4.70
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 56
ProASIC3 Flash Family FPGAs
Table 2-73 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
Std.
0.66
14.80
0.04
1.20
0.43
–1
0.56
12.59
0.04
1.02
–2
0.49
11.05
0.03
Std.
0.66
9.90
–1
0.56
–2
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
13.49 14.80
2.25
1.46
15.73
17.04
ns
0.36
11.48
12.59
1.91
1.25
13.38
14.49
ns
0.90
0.32
10.08
11.05
1.68
1.09
11.75
12.72
ns
0.04
1.20
0.43
9.73
9.90
2.65
2.50
11.97
12.13
ns
8.42
0.04
1.02
0.36
8.28
8.42
2.26
2.12
10.18
10.32
ns
0.49
7.39
0.03
0.90
0.32
7.27
7.39
1.98
1.86
8.94
9.06
ns
Std.
0.66
7.44
0.04
1.20
0.43
7.58
7.32
2.94
2.99
9.81
9.56
ns
–1
0.56
6.33
0.04
1.02
0.36
6.44
6.23
2.50
2.54
8.35
8.13
ns
–2
0.49
5.55
0.03
0.90
0.32
5.66
5.47
2.19
2.23
7.33
7.14
ns
Std.
0.66
7.44
0.04
1.20
0.43
7.58
7.32
2.94
2.99
9.81
9.56
ns
–1
0.56
6.33
0.04
1.02
0.36
6.44
6.23
2.50
2.54
8.35
8.13
ns
–2
0.49
5.55
0.03
0.90
0.32
5.66
5.47
2.19
2.23
7.33
7.14
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-74 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
4 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.66
11.21
0.04
1.20
0.43
8.53
11.21
1.99
1.21
ns
–1
0.56
9.54
0.04
1.02
0.36
7.26
9.54
1.69
1.03
ns
–2
0.49
8.37
0.03
0.90
0.32
6.37
8.37
1.49
0.90
ns
Std.
0.66
6.34
0.04
1.20
0.43
5.38
6.34
2.41
2.48
ns
–1
0.56
5.40
0.04
1.02
0.36
4.58
5.40
2.05
2.11
ns
–2
0.49
4.74
0.03
0.90
0.32
4.02
4.74
1.80
1.85
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 57
ProASIC3 Flash Family FPGAs
Table 2-75 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
4 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.66
15.01
0.04
1.20
0.43
13.15
15.01
1.99
1.99
ns
–1
0.56
12.77
0.04
1.02
0.36
11.19
12.77
1.70
1.70
ns
–2
0.49
11.21
0.03
0.90
0.32
9.82
11.21
1.49
1.49
ns
Std.
0.66
10.10
0.04
1.20
0.43
9.55
10.10
2.41
2.37
ns
–1
0.56
8.59
0.04
1.02
0.36
8.13
8.59
2.05
2.02
ns
–2
0.49
7.54
0.03
0.90
0.32
7.13
7.54
1.80
1.77
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-76 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Max.
V
Min.
V
Max.
mA mA mA3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.,
V
Max.
mA3 µA4 µA4
2 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI 0.75 * VCCI
2
2
16
13
10 10
4 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI 0.75 * VCCI
4
4
33
25
10 10
6 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI 0.75 * VCCI
6
6
39
32
10 10
8 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI 0.75 * VCCI
8
8
55
66
10 10
12 mA
–0.3
0.35 * VCCI
0.65 * VCCI
1.575
0.25 * VCCI 0.75 * VCCI 12
12
55
66
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R ev i si o n 1 5
2- 58
ProASIC3 Flash Family FPGAs
Table 2-77 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.5 V
LVCMOS
VIL
Drive
Min.
Strength
V
VIH
Max.
V
Min.
V
Max.
V
VOL
VOH
IOL IOH IOSL
IOSH
IIL1 IIH2
Max.
V
Min.
V
mA mA
Max.
mA3
Max.
mA3
µA4 µA4
2 mA
–0.3 0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI
2
2
16
13
10 10
4 mA
–0.3 0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI
4
4
33
25
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-78 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.5 V
LVCMOS
VIL
Drive
Strength
Min.
V
2 mA
–0.3
Max.
V
VIH
Min.
V
Max.
V
0.35 * VCCI 0.65 * VCCI
3.6
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Max.
V
Min.
V
Max. Max.
mA mA mA3 mA3 µA4 µA4
0.25 * VCCI 0.75 * VCCI
2
2
13
16
10
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R = 1 kΩ
Test Point
Enable Path
Test Point
Datapath
Figure 2-9 •
35 pF
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
AC Loading
Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
1.5
0.75
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
R ev i si o n 1 5
2- 59
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-80 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
8.36
0.04
1.44
0.43
6.82
8.36
3.39
2.77
9.06
10.60
ns
–1
0.56
7.11
0.04
1.22
0.36
5.80
7.11
2.88
2.35
7.71
9.02
ns
–2
0.49
6.24
0.03
1.07
0.32
5.10
6.24
2.53
2.06
6.76
7.91
ns
Std.
0.66
5.31
0.04
1.44
0.43
4.85
5.31
3.74
3.40
7.09
7.55
ns
–1
0.56
4.52
0.04
1.22
0.36
4.13
4.52
3.18
2.89
6.03
6.42
ns
–2
0.49
3.97
0.03
1.07
0.32
3.62
3.97
2.79
2.54
5.29
5.64
ns
Std.
0.66
4.67
0.04
1.44
0.43
4.55
4.67
3.82
3.56
6.78
6.90
ns
–1
0.56
3.97
0.04
1.22
0.36
3.87
3.97
3.25
3.03
5.77
5.87
ns
–2
0.49
3.49
0.03
1.07
0.32
3.40
3.49
2.85
2.66
5.07
5.16
ns
Std.
0.66
4.08
0.04
1.44
0.43
4.15
3.58
3.94
4.20
6.39
5.81
ns
–1
0.56
3.47
0.04
1.22
0.36
3.53
3.04
3.36
3.58
5.44
4.95
ns
–2
0.49
3.05
0.03
1.07
0.32
3.10
2.67
2.95
3.14
4.77
4.34
ns
Std.
0.66
4.08
0.04
1.44
0.43
4.15
3.58
3.94
4.20
6.39
5.81
ns
–1
0.56
3.47
0.04
1.22
0.36
3.53
3.04
3.36
3.58
5.44
4.95
ns
–2
0.49
3.05
0.03
1.07
0.32
3.10
2.67
2.95
3.14
4.77
4.34
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 60
ProASIC3 Flash Family FPGAs
Table 2-81 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
Std.
0.66
12.78
0.04
1.44
0.43
–1
0.56
10.87
0.04
1.22
–2
0.49
9.55
0.03
Std.
0.66
10.01
–1
0.56
–2
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
12.81 12.78
3.40
2.64
15.05 15.02
ns
0.36
10.90 10.87
2.89
2.25
12.80 12.78
ns
1.07
0.32
9.57
9.55
2.54
1.97
11.24
11.22
ns
0.04
1.44
0.43
10.19
9.55
3.75
3.27
12.43 11.78
ns
8.51
0.04
1.22
0.36
8.67
8.12
3.19
2.78
10.57 10.02
ns
0.49
7.47
0.03
1.07
0.32
7.61
7.13
2.80
2.44
9.28
8.80
ns
Std.
0.66
9.33
0.04
1.44
0.43
9.51
8.89
3.83
3.43
11.74
11.13
ns
–1
0.56
7.94
0.04
1.22
0.36
8.09
7.56
3.26
2.92
9.99
9.47
ns
–2
0.49
6.97
0.03
1.07
0.32
7.10
6.64
2.86
2.56
8.77
8.31
ns
Std.
0.66
8.91
0.04
1.44
0.43
9.07
8.89
3.95
4.05
11.31
11.13
ns
–1
0.56
7.58
0.04
1.22
0.36
7.72
7.57
3.36
3.44
9.62
9.47
ns
–2
0.49
6.65
0.03
1.07
0.32
6.78
6.64
2.95
3.02
8.45
8.31
ns
Std.
0.66
8.91
0.04
1.44
0.43
9.07
8.89
3.95
4.05
11.31
11.13
ns
–1
0.56
7.58
0.04
1.22
0.36
7.72
7.57
3.36
3.44
9.62
9.47
ns
–2
0.49
6.65
0.03
1.07
0.32
6.78
6.64
2.95
3.02
8.45
8.31
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 61
ProASIC3 Flash Family FPGAs
Table 2-82 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Strength
2 mA
4 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
7.83
0.04
1.42
0.43
6.42
7.83
2.71
2.55
8.65
10.07
ns
–1
0.56
6.66
0.04
1.21
0.36
5.46
6.66
2.31
2.17
7.36
8.56
ns
–2
0.49
5.85
0.03
1.06
0.32
4.79
5.85
2.02
1.90
6.46
7.52
ns
Std.
0.66
4.84
0.04
1.42
0.43
4.49
4.84
3.03
3.13
6.72
7.08
ns
–1
0.56
4.12
0.04
1.21
0.36
3.82
4.12
2.58
2.66
5.72
6.02
ns
–2
0.49
3.61
0.03
1.06
0.32
3.35
3.61
2.26
2.34
5.02
5.28
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-83 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Strength
2 mA
4 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
Std.
0.66
12.08
0.04
1.42
0.43
12.01 12.08 2.72
2.43 14.24 14.31
ns
–1
0.56
10.27
0.04
1.21
0.36
10.21 10.27 2.31
2.06 12.12 12.18
ns
–2
0.49
9.02
0.03
1.06
0.32
8.97
9.02
2.03
1.81 10.64 10.69
ns
Std.
0.66
9.28
0.04
1.42
0.43
9.45
8.91
3.04
3.00 11.69 11.15
ns
–1
0.56
7.89
0.04
1.21
0.36
8.04
7.58
2.58
2.55
9.94
9.49
ns
–2
0.49
6.93
0.03
1.06
0.32
7.06
6.66
2.27
2.24
8.73
8.33
ns
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-84 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.66
7.65
0.04
1.42
0.43
6.31
7.65
2.45
2.45
ns
–1
0.56
6.50
0.04
1.21
0.36
5.37
6.50
2.08
2.08
ns
–2
0.49
5.71
0.03
1.06
0.32
4.71
5.71
1.83
1.83
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 62
ProASIC3 Flash Family FPGAs
Table 2-85 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
Std.
0.66
12.33
0.04
1.42
0.43
11.79
12.33
2.45
2.32
ns
–1
0.56
10.49
0.04
1.21
0.36
10.03
10.49
2.08
1.98
ns
–2
0.49
9.21
0.03
1.06
0.32
8.81
9.21
1.83
1.73
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
Table 2-86 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
VIL
Min.
V
Drive Strength
VIH
Max.
V
Min.
V
Max.
V
Per PCI specification
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Max,.
V
Min.
V
Max.
mA1
Max.
mA1
µA2 µA2
mA mA
Per PCI curves
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable
path characterization are described in Figure 2-10.
R = 25Ω
Test Point
Datapath
R to VCCI for tDP (F)
R to GND for tDP (R)
R = 1 kΩ
Test Point
Enable Path
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
10 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-10 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is
described in Table 2-87.
Table 2-87 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
Measuring Point* (V)
CLOAD (pF)
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
10
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
R ev i si o n 1 5
2- 63
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-88 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
2.68
0.04
0.86
0.43
2.73
1.95
3.21
3.58
4.97
4.19
ns
–1
0.56
2.28
0.04
0.73
0.36
2.32
1.66
2.73
3.05
4.22
3.56
ns
–2
0.49
2.00
0.03
0.65
0.32
2.04
1.46
2.40
2.68
3.71
3.13
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-89 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
2.31
0.04
0.85
0.43
2.35
1.70
2.79
3.22
4.59
3.94
ns
–1
0.56
1.96
0.04
0.72
0.36
2.00
1.45
2.37
2.74
3.90
3.35
ns
–2
0.49
1.72
0.03
0.64
0.32
1.76
1.27
2.08
2.41
3.42
2.94
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when
the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12
OUTBUF_LVDS
FPGA
P
165 
Z0 = 50 
140 
N
165 
P
Z0 = 50 
FPGA
+
–
100 
INBUF_LVDS
N
Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation
R ev i si o n 1 5
2- 64
ProASIC3 Flash Family FPGAs
Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
Typ.
Max.
Units
2.375
2.5
2.625
V
VCCI
Supply Voltage
VOL
Output Low Voltage
0.9
1.075
1.25
V
VOH
Output High Voltage
1.25
1.425
1.6
V
1
Output Lower Current
0.65
0.91
1.16
mA
IOH 1
Output High Current
0.65
0.91
1.16
mA
VI
Input Voltage
2.925
V
IOL
0
2,3
Input High Leakage Current
10
µA
IIL 2,4
Input Low Leakage Current
10
µA
VODIFF
Differential Output Voltage
VOCM
IIH
250
350
450
mV
Output Common Mode Voltage
1.125
1.25
1.375
V
VICM
Input Common Mode Voltage
0.05
1.25
2.35
V
VIDIFF
Input Differential Voltage
100
350
mV
Notes:
1. IOL/ IOH defined by VODIFF/(Resistor Network)
2. Currents are measured at 85°C junction temperature.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <VCCI. Input current is
larger when operating outside recommended ranges.
4. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN <VIL.
Table 2-91 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
1.075
Input High (V)
Measuring Point* (V)
1.325
Cross point
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Timing Characteristics
Table 2-92 • LVDS
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
0.66
1.83
0.04
1.60
ns
–1
0.56
1.56
0.04
1.36
ns
–2
0.49
1.37
0.03
1.20
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 65
ProASIC3 Flash Family FPGAs
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20
loads. A sample application is given in Figure 2-12. The input and output buffer delays are available in
the LVDS section in Table 2-92.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 Ω and
RT = 70 Ω, given Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5").
Receiver
Transceiver
EN
R
+
-
+
Zstub
Z0
RT Z
0
D
EN
T
RS RS
Zstub
Driver
-
+
RS RS
Zstub
Receiver
EN
EN
R
-
+
RS RS
Zstub
Zstub
Transceiver
Zstub
EN
T
-
+
RS RS
Zstub
Zstub
BIBUF_LVDS
-
R S RS
...
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
RT
Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Bourns Part Number: CAT16-PC4F12
OUTBUF_LVPECL
FPGA
P
100 
187 W
N
100 
P
Z0 = 50 
+
–
100 
Z0 = 50 
FPGA
INBUF_LVPECL
N
Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation
R ev i si o n 1 5
2- 66
ProASIC3 Flash Family FPGAs
Table 2-93 • Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
Max.
Min.
3.0
Max.
Min.
3.3
Max.
Units
VCCI
Supply Voltage
3.6
VOL
Output Low Voltage
0.96
1.27
1.06
1.43
1.30
1.57
V
VOH
Output High Voltage
1.8
2.11
1.92
2.28
2.13
2.41
V
VIL, VIH
Input Low, Input High Voltages
0
3.6
0
3.6
0
3.6
V
VODIFF
Differential Output Voltage
0.625
0.97
0.625
0.97
0.625
0.97
V
VOCM
Output Common-Mode Voltage
1.762
1.98
1.762
1.98
1.762
1.98
V
VICM
Input Common-Mode Voltage
1.01
2.57
1.01
2.57
1.01
2.57
V
VIDIFF
Input Differential Voltage
300
300
V
300
mV
Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
1.64
Input High (V)
Measuring Point* (V)
1.94
Cross point
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Timing Characteristics
Table 2-95 • LVPECL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
tDOUT
tDP
tDIN
tPY
Units
Std.
Speed Grade
0.66
1.80
0.04
1.40
ns
–1
0.56
1.53
0.04
1.19
ns
–2
0.49
1.34
0.03
1.05
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 67
ProASIC3 Flash Family FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
INBUF
Preset
L
DOUT
Data_out
E
Y
F
Core
Array
G
PRE
D
Q
DFN1E1P1
TRIBUF
CLKBUF
CLK
INBUF
Enable
PRE
D
Q
C DFN1E1P1
INBUF
Data
Pad Out
D
E
E
EOUT
B
H
I
A
J
K
INBUF
INBUF
D_Enable
CLK
CLKBUF
Enable
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
PRE
D
Q
DFN1E1P1
E
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
R ev i si o n 1 5
2- 68
ProASIC3 Flash Family FPGAs
Table 2-96 • Parameter Definition and Measuring Nodes
Parameter Name
Parameter Definition
Measuring Nodes
(from, to)*
tOCLKQ
Clock-to-Q of the Output Data Register
H, DOUT
tOSUD
Data Setup Time for the Output Data Register
F, H
tOHD
Data Hold Time for the Output Data Register
F, H
tOSUE
Enable Setup Time for the Output Data Register
G, H
tOHE
Enable Hold Time for the Output Data Register
G, H
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
L, H
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
L, H
tOECLKQ
Clock-to-Q of the Output Enable Register
tOESUD
Data Setup Time for the Output Enable Register
J, H
tOEHD
Data Hold Time for the Output Enable Register
J, H
tOESUE
Enable Setup Time for the Output Enable Register
K, H
tOEHE
Enable Hold Time for the Output Enable Register
K, H
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
I, H
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
I, H
tICLKQ
Clock-to-Q of the Input Data Register
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tISUE
Enable Setup Time for the Input Data Register
B, A
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
D, E
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
D, A
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
D, A
L, DOUT
H, EOUT
I, EOUT
Note: *See Figure 2-14 on page 2-68 for more information.
R ev i si o n 1 5
2- 69
ProASIC3 Flash Family FPGAs
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
D
CC
Q
DFN1E1C1
EE
Data_out FF
D
Q
DFN1E1C1
TRIBUF
INBUF
Data
Core
Array
Pad Out
DOUT
Y
GG
INBUF
Enable
BB
EOUT
E
E
CLR
CLR
LL
INBUF
CLR
CLKBUF
CLK
HH
AA
JJ
DD
KK
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
D
Q
DFN1E1C1
E
INBUF
CLKBUF
CLK
Enable
INBUF
D_Enable
CLR
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
R ev i si o n 1 5
2- 70
ProASIC3 Flash Family FPGAs
Table 2-97 • Parameter Definition and Measuring Nodes
Parameter Name
Parameter Definition
Measuring Nodes
(from, to)*
tOCLKQ
Clock-to-Q of the Output Data Register
HH, DOUT
tOSUD
Data Setup Time for the Output Data Register
FF, HH
tOHD
Data Hold Time for the Output Data Register
FF, HH
tOSUE
Enable Setup Time for the Output Data Register
GG, HH
tOHE
Enable Hold Time for the Output Data Register
GG, HH
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
LL, HH
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
LL, HH
tOECLKQ
Clock-to-Q of the Output Enable Register
tOESUD
Data Setup Time for the Output Enable Register
JJ, HH
tOEHD
Data Hold Time for the Output Enable Register
JJ, HH
tOESUE
Enable Setup Time for the Output Enable Register
KK, HH
tOEHE
Enable Hold Time for the Output Enable Register
KK, HH
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
II, EOUT
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
II, HH
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
II, HH
tICLKQ
Clock-to-Q of the Input Data Register
AA, EE
tISUD
Data Setup Time for the Input Data Register
CC, AA
tIHD
Data Hold Time for the Input Data Register
CC, AA
tISUE
Enable Setup Time for the Input Data Register
BB, AA
tIHE
Enable Hold Time for the Input Data Register
BB, AA
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
DD, EE
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
DD, AA
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
DD, AA
LL, DOUT
HH, EOUT
Note: *See Figure 2-15 on page 2-70 for more information.
R ev i si o n 1 5
2- 71
ProASIC3 Flash Family FPGAs
Input Register
tICKMPWH tICKMPWL
CLK
50%
50%
Enable
50%
1
50%
50%
50%
tIHD
tISUD
Data
50%
50%
50%
0
tIWPRE
50%
tIRECPRE
tIREMPRE
50%
50%
tIHE
Preset
tISUE
50%
tIWCLR
50%
Clear
tIRECCLR
tIREMCLR
50%
50%
tIPRE2Q
50%
Out_1
50%
tICLR2Q
50%
tICLKQ
Figure 2-16 • Input Register Timing Diagram
Timing Characteristics
Table 2-98 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1 Std. Units
tICLKQ
Clock-to-Q of the Input Data Register
0.24 0.27 0.32
ns
tISUD
Data Setup Time for the Input Data Register
0.26 0.30 0.35
ns
tIHD
Data Hold Time for the Input Data Register
0.00 0.00 0.00
ns
tISUE
Enable Setup Time for the Input Data Register
0.37 0.42 0.50
ns
tIHE
Enable Hold Time for the Input Data Register
0.00 0.00 0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.45 0.52 0.61
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.45 0.52 0.61
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00 0.00 0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.22 0.25 0.30
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00 0.00 0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.22 0.25 0.30
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.22 0.25 0.30
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.22 0.25 0.30
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.36 0.41 0.48
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.32 0.37 0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 72
ProASIC3 Flash Family FPGAs
Output Register
tOCKMPWH tOCKMPWL
CLK
50%
50%
50%
50%
50%
50%
50%
tOSUD tOHD
1
Data_out
Enable
50%
50%
0
50%
tOWPRE
tOHE
Preset
tOSUE
tOREMPRE
tORECPRE
50%
50%
50%
tOWCLR
50%
Clear
tOREMCLR
tORECCLR
50%
50%
tOPRE2Q
50%
DOUT
50%
tOCLR2Q
50%
tOCLKQ
Figure 2-17 • Output Register Timing Diagram
Timing Characteristics
Table 2-99 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
tOCLKQ
Clock-to-Q of the Output Data Register
–2
–1
Std. Units
0.59 0.67 0.79
ns
tOSUD
Data Setup Time for the Output Data Register
0.31 0.36 0.42
ns
tOHD
Data Hold Time for the Output Data Register
0.00 0.00 0.00
ns
tOSUE
Enable Setup Time for the Output Data Register
0.44 0.50 0.59
ns
tOHE
Enable Hold Time for the Output Data Register
0.00 0.00 0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
0.80 0.91 1.07
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
0.80 0.91 1.07
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00 0.00 0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.22 0.25 0.30
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00 0.00 0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.22 0.25 0.30
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.22 0.25 0.30
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.22 0.25 0.30
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output Data Register
0.36 0.41 0.48
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register
0.32 0.37 0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
Output Enable Register
tOECKMPWH tOECKMPWL
CLK
50%
50%
50%
50%
50%
50%
50%
tOESUD tOEHD
1
D_Enable
Enable
Preset
50%
0 50%
50%
tOESUEtOEHE
tOEWPRE
tOEREMPRE
tOERECPRE
50%
50%
50%
tOEWCLR
50%
Clear
tOEPRE2Q
EOUT
50%
50%
tOERECCLR
50%
tOEREMCLR
50%
tOECLR2Q
50%
tOECLKQ
Figure 2-18 • Output Enable Register Timing Diagram
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-100 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.59 0.67 0.79
ns
tOESUD
Data Setup Time for the Output Enable Register
0.31 0.36 0.42
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00 0.00 0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
0.44 0.50 0.58
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00 0.00 0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.22 0.25 0.30
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.22 0.25 0.30
ns
tOECKMPWH
Clock Minimum Pulse Width High for the Output Enable Register
0.36 0.41 0.48
ns
tOECKMPWL
Clock Minimum Pulse Width Low for the Output Enable Register
0.32 0.37 0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 75
ProASIC3 Flash Family FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
Data
A
D
Out_QF
(to core)
E
Out_QR
(to core)
FF1
B
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 2-19 • Input DDR Timing Model
Table 2-101 • Parameter Definitions
Parameter Name
Parameter Definition
Measuring Nodes (from, to)
tDDRICLKQ1
Clock-to-Out Out_QR
B, D
tDDRICLKQ2
Clock-to-Out Out_QF
B, E
tDDRISUD
Data Setup Time of DDR input
A, B
tDDRIHD
Data Hold Time of DDR input
A, B
tDDRICLR2Q1
Clear-to-Out Out_QR
C, D
tDDRICLR2Q2
Clear-to-Out Out_QF
C, E
tDDRIREMCLR
Clear Removal
C, B
tDDRIRECCLR
Clear Recovery
C, B
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
CLK
tDDRISUD
Data
1
2
3
4
5
6
tDDRIHD
7
8
9
tDDRIRECCLR
CLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
2
6
4
tDDRICLKQ2
tDDRICLR2Q2
Out_QR
3
7
5
Figure 2-20 • Input DDR Timing Diagram
Timing Characteristics
Table 2-102 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.27
0.31
0.37
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.39
0.44
0.52
ns
tDDRISUD
Data Setup for Input DDR (Fall)
0.25
0.28
0.33
ns
Data Setup for Input DDR (Rise)
0.25
0.28
0.33
ns
Data Hold for Input DDR (Fall)
0.00
0.00
0.00
ns
Data Hold for Input DDR (Rise)
0.00
0.00
0.00
ns
tDDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR
0.46
0.53
0.62
ns
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
0.57
0.65
0.76
ns
tDDRIREMCLR
Asynchronous Clear Removal time for Input DDR
0.00
0.00
0.00
ns
tDDRIRECCLR
Asynchronous Clear Recovery time for Input DDR
0.22
0.25
0.30
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.22
0.25
0.30
ns
tDDRICKMPWH
Clock Minimum Pulse Width High for Input DDR
0.36
0.41
0.48
ns
tDDRICKMPWL
Clock Minimum Pulse Width Low for Input DDR
0.32
0.37
0.43
ns
FDDRIMAX
Maximum Frequency for Input DDR
350
309
263
MHz
tDDRIHD
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 77
ProASIC3 Flash Family FPGAs
Output DDR Module
Output DDR
A
Data_F
(from core)
X
FF1
B
CLK
CLKBUF
E
X
C
X
D
Data_R
(from core)
Out
0
X
1
X
OUTBUF
FF2
B
X
CLR
INBUF
C
X
DDR_OUT
Figure 2-21 • Output DDR Timing Model
Table 2-103 • Parameter Definitions
Parameter Name
Parameter Definition
Measuring Nodes (from, to)
tDDROCLKQ
Clock-to-Out
B, E
tDDROCLR2Q
Asynchronous Clear-to-Out
C, E
tDDROREMCLR
Clear Removal
C, B
tDDRORECCLR
Clear Recovery
C, B
tDDROSUD1
Data Setup Data_F
A, B
tDDROSUD2
Data Setup Data_R
D, B
tDDROHD1
Data Hold Data_F
A, B
tDDROHD2
Data Hold Data_R
D, B
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
CLK
tDDROSUD2 tDDROHD2
1
Data_F
2
5
tDDROHD1
tDDROREMCLR
Data_R 6
4
3
7
8
9
10
11
tDDRORECCLR
tDDROREMCLR
CLR
tDDROCLR2Q
tDDROCLKQ
Out
2
7
8
3
9
4
10
Figure 2-22 • Output DDR Timing Diagram
Timing Characteristics
Table 2-104 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
0.70
0.80
0.94
ns
tDDROSUD1
Data_F Data Setup for Output DDR
0.38
0.43
0.51
ns
tDDROSUD2
Data_R Data Setup for Output DDR
0.38
0.43
0.51
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
0.00
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
0.00
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
0.80
0.91
1.07
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
0.00
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.22
0.25
0.30
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.22
0.25
0.30
ns
tDDROCKMPWH
Clock Minimum Pulse Width High for the Output DDR
0.36
0.41
0.48
ns
tDDROCKMPWL
Clock Minimum Pulse Width Low for the Output DDR
0.32
0.37
0.43
ns
FDDOMAX
Maximum Frequency for the Output DDR
350
309
263
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 79
ProASIC3 Flash Family FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e,
and ProASIC3/E Macro Library Guide.
A
A
B
A
OR2
Y
AND2
A
Y
B
B
B
XOR2
A
B
C
Y
A
A
B
C
NOR2
B
A
A
Y
INV
NAND3
A
MAJ3
B
Y
NAND2
XOR3
Y
Y
0
MUX2
B
Y
Y
1
C
S
Figure 2-23 • Sample of Combinatorial Cells
R ev i si o n 1 5
2- 80
ProASIC3 Flash Family FPGAs
tPD
A
NAND2 or
Any Combinatorial
Logic
B
Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR))
where edges are applicable for the particular
combinatorial cell
VCC
50%
50%
A, B, C
GND
VCC
50%
50%
OUT
GND
VCC
tPD
tPD
(FF)
(RR)
OUT
tPD
(FR)
50%
tPD
50%
GND
(RF)
Figure 2-24 • Timing Model and Waveforms
R ev i si o n 1 5
2- 81
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-105 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Parameter
–2
–1
Std.
Units
Y = !A
tPD
0.40
0.46
0.54
ns
Y=A·B
tPD
0.47
0.54
0.63
ns
Y = !(A · B)
tPD
0.47
0.54
0.63
ns
Y=A+B
tPD
0.49
0.55
0.65
ns
NOR2
Y = !(A + B)
tPD
0.49
0.55
0.65
ns
XOR2
Y=A⊕B
tPD
0.74
0.84
0.99
ns
MAJ3
Y = MAJ(A, B, C)
tPD
0.70
0.79
0.93
ns
XOR3
Y=A⊕B⊕C
tPD
0.87
1.00
1.17
ns
MUX2
Y = A !S + B S
tPD
0.51
0.58
0.68
ns
AND3
Y=A·B·C
tPD
0.56
0.64
0.75
ns
INV
AND2
NAND2
OR2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E
Macro Library Guide.
Data
D
Out
Q
Data
En
DFN1
D
Out
Q
DFN1E1
CLK
CLK
PRE
Data
D
Q
Out
Data
En
DFN1C1
D
Q
Out
DFI1E1P1
CLK
CLK
CLR
Figure 2-25 • Sample of Sequential Cells
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
tCKMPWH tCKMPWL
CLK
50%
50%
tSUD
50%
Data
EN
PRE
50%
tRECPRE
tREMPRE
50%
50%
50%
CLR
tPRE2Q
50%
tREMCLR
tRECCLR
tWCLR
Out
50%
50%
0
tWPRE
tHE
50%
50%
tHD
50%
tSUE
50%
50%
50%
50%
tCLR2Q
50%
50%
tCLKQ
Figure 2-26 • Timing Model and Waveforms
Timing Characteristics
Table 2-106 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tCLKQ
Clock-to-Q of the Core Register
0.55 0.63 0.74
ns
tSUD
Data Setup Time for the Core Register
0.43 0.49 0.57
ns
tHD
Data Hold Time for the Core Register
0.00 0.00 0.00
ns
tSUE
Enable Setup Time for the Core Register
0.45 0.52 0.61
ns
tHE
Enable Hold Time for the Core Register
0.00 0.00 0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.40 0.45 0.53
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.40 0.45 0.53
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00 0.00 0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.22 0.25 0.30
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00 0.00 0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.22 0.25 0.30
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.22 0.25 0.30
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.22 0.25 0.30
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.32 0.37 0.43
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.36 0.41 0.48
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 83
ProASIC3 Flash Family FPGAs
Global Resource Characteristics
A3P250 Clock Tree Topology
Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250 device. It
is used to drive all D-flip-flops in the device.
Central
Global Rib
VersaTile
Rows
CCC
Global Spine
Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-89. Table 2-108 to Table 2-114 on page 2-88
present minimum and maximum global clock delays within each device. Minimum and maximum delays
are measured with minimum and maximum loading.
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-107 • A3P015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
1
–1
2
1
Std.
2
1
Min.
Max.
Min.
Max.
tRCKL
Input Low Delay for Global Clock
0.66
0.81
0.75
0.92
0.88
1.08
ns
tRCKH
Input High Delay for Global Clock
0.67
0.84
0.76
0.96
0.89
1.13
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.18
Min.
Max.2 Units
Parameter Description
0.21
0.25
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-108 • A3P030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
Parameter
1
–1
Std.
Max.2
Min.1
Max.2
Min.1 Max.2 Units
Description
Min.
tRCKL
Input Low Delay for Global Clock
0.67
0.81
0.76
0.92
0.89
1.09
ns
tRCKH
Input High Delay for Global Clock
0.68
0.85
0.77
0.97
0.91
1.14
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.18
0.21
0.24
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
Table 2-109 • A3P060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
Parameter
1
–1
2
1
Std.
Max.
2
Min.1 Max.2 Units
Description
Min.
Max.
Min.
tRCKL
Input Low Delay for Global Clock
0.71
0.93
0.81
1.05
0.95
1.24
ns
tRCKH
Input High Delay for Global Clock
0.70
0.96
0.80
1.09
0.94
1.28
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-110 • A3P125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Description
Min.1
Max.2
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
0.77
0.99
0.87
1.12
1.03
1.32
ns
tRCKH
Input High Delay for Global Clock
0.76
1.02
0.87
1.16
1.02
1.37
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
Parameter
0.26
0.29
Min.1 Max.2 Units
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
Table 2-111 • A3P250 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
Parameter
1
–1
Max.
2
Min.
1
Std.
Min.1 Max.2 Units
Description
Min.
tRCKL
Input Low Delay for Global Clock
0.80
1.01
0.91
1.15
1.07
1.36
ns
tRCKH
Input High Delay for Global Clock
0.78
1.04
0.89
1.18
1.04
1.39
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
Max.
2
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-112 • A3P400 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Description
Min.1
Max.2
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
0.87
1.09
0.99
1.24
1.17
1.46
ns
tRCKH
Input High Delay for Global Clock
0.86
1.11
0.98
1.27
1.15
1.49
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
Parameter
0.26
0.29
Min.1 Max.2 Units
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
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ProASIC3 Flash Family FPGAs
Table 2-113 • A3P600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
Parameter
1
–1
2
Min.
1
Std.
2
Max.
Min.1 Max.2 Units
Description
Min.
Max.
tRCKL
Input Low Delay for Global Clock
0.87
1.09
0.99
1.24
1.17
1.46
ns
tRCKH
Input High Delay for Global Clock
0.86
1.11
0.98
1.27
1.15
1.49
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-114 • A3P1000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Description
Min.1
Max.2
Min.1
Max.2
Min.1
tRCKL
Input Low Delay for Global Clock
0.94
1.16
1.07
1.32
1.26
1.55
ns
tRCKH
Input High Delay for Global Clock
0.93
1.19
1.06
1.35
1.24
1.59
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
Parameter
0.26
0.29
Max.2 Units
0.35
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 88
ProASIC3 Flash Family FPGAs
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-115 • ProASIC3 CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
125
MHz
Serial Clock (SCLK) for Dynamic PLL1
2, 3
2004
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable
Delay Block
ps
32
Input Period Jitter
1.5
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
0.75 MHz to 24 MHz
ns
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.50%
0.70%
24 MHz to 100 MHz
1.00%
1.20%
100 MHz to 250 MHz
1.75%
2.00%
250 MHz to 350 MHz
2.50%
5.60%
Acquisition Time
(A3P250 and A3P1000 only)
LockControl = 0
300
µs
LockControl = 1
300
µs
(all other dies)
LockControl = 0
300
µs
LockControl = 1
6.0
ms
LockControl = 0
1.6
ns
Tracking Jitter 5
(A3P250 and A3P1000 only)
(all other dies)
LockControl = 1
1.6
ns
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
48.5
51.5
%
Delay Range in Block: Programmable Delay 1
2, 3
0.6
5.56
ns
Delay Range in Block: Programmable Delay 2
2, 3
0.225
5.56
ns
Output Duty Cycle
Delay Range in Block: Fixed Delay2, 3
2.2
ns
Notes:
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.
3. TJ = 25°C, VCC = 1.5 V
4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help for more information.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
6. The A3P030 device does not contain a PLL.
R ev i si o n 1 5
2- 89
ProASIC3 Flash Family FPGAs
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.
Figure 2-28 • Peak-to-Peak Jitter Definition
R ev i si o n 1 5
2- 90
ProASIC3 Flash Family FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM512X18
RAM4K9
ADDRA11
ADDRA10
DOUTA8
DOUTA7
RADDR8
RADDR7
RD17
RD16
ADDRA0
DINA8
DINA7
DOUTA0
RADDR0
RD0
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
WMODEA
BLKA
WENA
CLKA
PIPE
REN
RCLK
ADDRB11
ADDRB10
DOUTB8
DOUTB7
ADDRB0
DOUTB0
DINB8
DINB7
WADDR8
WADDR7
WADDR0
WD17
WD16
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
WEN
WCLK
RESET
RESET
Figure 2-29 • RAM Models
R ev i si o n 1 5
2- 91
ProASIC3 Flash Family FPGAs
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS
tAH
A0
[R|W]ADDR
A1
A2
tBKS
tBKH
BLK
tENS
tENH
WEN
tCKQ1
DOUT|RD
D0
Dn
D1
D2
tDOH1
Figure 2-30 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
t
tAH
AS
A0
[R|W]ADDR
A1
A2
tBKS
tBKH
BLK
tENH
tENS
WEN
tCKQ2
DOUT|RD
Dn
D0
D1
tDOH2
Figure 2-31 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
R ev i si o n 1 5
2- 92
ProASIC3 Flash Family FPGAs
tCYC
tCKH
tCKL
CLK
tAS
tAH
A0
[R|W]ADDR
A1
A2
tBKS
tBKH
BLK
tENS
tENH
WEN
tDS
DI0
DIN|RD
tDH
DI1
D2
Dn
DOUT|RD
Figure 2-32 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
tAS
tAH
A0
ADDR
A1
A2
tBKS
tBKH
BLK
tENS
WEN
tDS
DI0
DIN
DOUT
(pass-through)
DOUT
(pipelined)
tDH
DI1
Dn
DI2
DI0
Dn
DI1
DI0
DI1
Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.
R ev i si o n 1 5
2- 93
ProASIC3 Flash Family FPGAs
tCYC
tCKH
tCKL
CLK
RESET
tRSTBQ
DOUT|RD
Dm
Dn
Figure 2-34 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
Timing Characteristics
Table 2-116 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tAS
Address setup time
0.25 0.28 0.33
ns
tAH
Address hold time
0.00 0.00 0.00
ns
tENS
REN, WEN setup time
0.14 0.16 0.19
ns
tENH
REN, WEN hold time
0.10 0.11 0.13
ns
tBKS
BLK setup time
0.23 0.27 0.31
ns
tBKH
BLK hold time
0.02 0.02 0.02
ns
tDS
Input data (DIN) setup time
0.18 0.21 0.25
ns
tDH
Input data (DIN) hold time
0.00 0.00 0.00
ns
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
2.36 2.68 3.15
ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
1.79 2.03 2.39
ns
Clock High to new data valid on DOUT (pipelined)
tCKQ2
0.89 1.02 1.20
ns
1
Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25
address—Applicable to Closing Edge
ns
tC2CWWH1
Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23
address—Applicable to Rising Edge
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34
address—Applicable to Opening Edge
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37
address— Applicable to Opening Edge
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
0.92 1.05 1.23
ns
RESET Low to Data Out Low on DOUT (pipelined)
0.92 1.05 1.23
ns
tREMRSTB
RESET removal
0.29 0.33 0.38
ns
tRECRSTB
RESET recovery
1.50 1.71 2.01
ns
tMPWRSTB
RESET minimum pulse width
0.21 0.24 0.29
ns
tCYC
Clock cycle time
3.23 3.68 4.32
ns
tC2CWWL
R ev i si o n 1 5
2- 94
ProASIC3 Flash Family FPGAs
Table 2-116 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V (continued)
Parameter
FMAX
Description
Maximum frequency
–2
–1
Std. Units
310
272
231
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 95
ProASIC3 Flash Family FPGAs
Table 2-117 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tAS
Address setup time
0.25 0.28 0.33
ns
tAH
Address hold time
0.00 0.00 0.00
ns
tENS
REN, WEN setup time
0.13 0.15 0.17
ns
tENH
REN, WEN hold time
0.10 0.11 0.13
ns
tDS
Input data (WD) setup time
0.18 0.21 0.25
ns
tDH
Input data (WD) hold time
0.00 0.00 0.00
ns
tCKQ1
Clock High to new data valid on RD (output retained)
2.16 2.46 2.89
ns
Clock High to new data valid on RD (pipelined)
0.90 1.02 1.20
ns
1
Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38
address—Applicable to Opening Edge
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44
address—Applicable to Opening Edge
ns
tRSTBQ
RESET Low to data out Low on RD (flow-through)
0.92 1.05 1.23
ns
RESET Low to data out Low on RD (pipelined)
0.92 1.05 1.23
ns
tREMRSTB
RESET removal
0.29 0.33 0.38
ns
tRECRSTB
RESET recovery
1.50 1.71 2.01
ns
tMPWRSTB
RESET minimum pulse width
0.21 0.24 0.29
ns
tCYC
Clock cycle time
3.23 3.68 4.32
ns
FMAX
Maximum frequency
310
tCKQ2
tC2CRWH
272
231
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 96
ProASIC3 Flash Family FPGAs
FIFO
FIFO4K18
RW2
RW1
RW0
WW2
WW1
WW0
ESTOP
FSTOP
RD17
RD16
RD0
FULL
AFULL
EMPTY
AEMPTY
AEVAL11
AEVAL10
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-35 • FIFO Model
R ev i si o n 1 5
2- 97
ProASIC3 Flash Family FPGAs
Timing Waveforms
tCYC
RCLK
tENH
tENS
REN
tBKH
tBKS
RBLK
tCKQ1
RD
(flow-through)
Dn
D0
D1
D2
D0
D1
tCKQ2
RD
(pipelined)
Dn
Figure 2-36 • FIFO Read
tCYC
WCLK
tENS
tENH
WEN
WBLK
tBKS
tBKH
tDS
WD
DI0
tDH
DI1
Figure 2-37 • FIFO Write
R ev i si o n 1 5
2- 98
ProASIC3 Flash Family FPGAs
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET
tRSTFG
EMPTY
tRSTAF
AEMPTY
tRSTFG
FULL
tRSTAF
AFULL
WA/RA
(Address Counter)
MATCH (A0)
Figure 2-38 • FIFO Reset
tCYC
RCLK
tRCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
(Address Counter) NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion
R ev i si o n 1 5
2- 99
ProASIC3 Flash Family FPGAs
tCYC
WCLK
tWCKFF
FULL
tCKAF
AFULL
WA/RA NO MATCH
(Address Counter)
NO MATCH
Dist = AFF_TH
MATCH (FULL)
Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
WA/RA MATCH
(Address Counter) (EMPTY)
RCLK
NO MATCH
1st Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
NO MATCH
Dist = AEF_TH + 1
2nd Rising
Edge
After 1st
Write
tRCKEF
EMPTY
tCKAF
AEMPTY
Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
WCLK
MATCH (FULL)
NO MATCH
1st Rising
Edge
After 1st
Read
NO MATCH
NO MATCH
NO MATCH
Dist = AFF_TH – 1
1st Rising
Edge
After 2nd
Read
tWCKF
FULL
tCKAF
AFULL
Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion
R ev i si o n 1 5
2- 100
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-118 • FIFO (for all dies except A3P250)
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tENS
REN, WEN Setup Time
1.34
1.52
1.79
ns
tENH
REN, WEN Hold Time
0.00
0.00
0.00
ns
tBKS
BLK Setup Time
0.19
0.22
0.26
ns
tBKH
BLK Hold Time
0.00
0.00
0.00
ns
tDS
Input Data (WD) Setup Time
0.18
0.21
0.25
ns
tDH
Input Data (WD) Hold Time
0.00
0.00
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.17
2.47
2.90
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.94
1.07
1.26
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on RD (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency for FIFO
310
272
231
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
R ev i si o n 1 5
2- 101
ProASIC3 Flash Family FPGAs
Table 2-119 • FIFO (for A3P250 only, aspect-ratio-dependent)
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tENS
REN, WEN Setup Time
3.26
3.71
4.36
ns
tENH
REN, WEN Hold Time
0.00
0.00
0.00
ns
tBKS
BLK Setup Time
0.19
0.22
0.26
ns
tBKH
BLK Hold Time
0.00
0.00
0.00
ns
tDS
Input Data (WD) Setup Time
0.18
0.21
0.25
ns
tDH
Input Data (WD) Hold Time
0.00
0.00
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.17
2.47
2.90
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.94
1.07
1.26
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on RD (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency for FIFO
310
272
231
MHz
R ev i si o n 1 5
2- 102
ProASIC3 Flash Family FPGAs
Table 2-120 • A3P250 FIFO 512×8
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tENS
REN, WEN Setup Time
3.75
4.27
5.02
ns
tENH
REN, WEN Hold Time
0.00
0.00
0.00
ns
tBKS
BLK Setup Time
0.19
0.22
0.26
ns
tBKH
BLK Hold Time
0.00
0.00
0.00
ns
tDS
Input Data (WD) Setup Time
0.18
0.21
0.25
ns
tDH
Input Data (WD) Hold Time
0.00
0.00
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.17
2.47
2.90
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.94
1.07
1.26
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on RD (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency for FIFO
310
272
231
MHz
R ev i si o n 1 5
2- 103
ProASIC3 Flash Family FPGAs
Table 2-121 • A3P250 FIFO 1k×4
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tENS
REN, WEN Setup Time
4.05
4.61
5.42
ns
tENH
REN, WEN Hold Time
0.00
0.00
0.00
ns
tBKS
BLK Setup Time
0.19
0.22
0.26
ns
tBKH
BLK Hold Time
0.00
0.00
0.00
ns
tDS
Input Data (WD) Setup Time
0.18
0.21
0.25
ns
tDH
Input Data (WD) Hold Time
0.00
0.00
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.36
2.68
3.15
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.89
1.02
1.20
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on RD (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency for FIFO
310
272
231
MHz
R ev i si o n 1 5
2- 104
ProASIC3 Flash Family FPGAs
Table 2-122 • A3P250 FIFO 2k×2
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tENS
REN, WEN Setup Time
4.39
5.00
5.88
ns
tENH
REN, WEN Hold Time
0.00
0.00
0.00
ns
tBKS
BLK Setup Time
0.19
0.22
0.26
ns
tBKH
BLK Hold Time
0.00
0.00
0.00
ns
tDS
Input Data (WD) Setup Time
0.18
0.21
0.25
ns
tDH
Input Data (WD) Hold Time
0.00
0.00
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.36
2.68
3.15
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.89
1.02
1.20
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on RD (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency for FIFO
310
272
231
MHz
Table 2-123 • A3P250 FIFO 4k×1
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tENS
REN, WEN Setup Time
4.86
5.53
6.50
ns
tENH
REN, WEN Hold Time
0.00
0.00
0.00
ns
tBKS
BLK Setup Time
0.19
0.22
0.26
ns
tBKH
BLK Hold Time
0.00
0.00
0.00
ns
tDS
Input Data (WD) Setup Time
0.18
0.21
0.25
ns
tDH
Input Data (WD) Hold Time
0.00
0.00
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.36
2.68
3.15
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.89
1.02
1.20
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
R ev i si o n 1 5
2- 105
ProASIC3 Flash Family FPGAs
Table 2-123 • A3P250 FIFO 4k×1 (continued)
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data Out Low on DO (pass-through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on DO (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency
310
272
231
MHz
Embedded FlashROM Characteristics
tSU
CLK
tSU
tHOLD
Address
tSU
tHOLD
A0
tHOLD
A1
tCKQ2
tCKQ2
D0
Data
tCKQ2
D0
D1
Figure 2-43 • Timing Diagram
Timing Characteristics
Table 2-124 • Embedded FlashROM Access Time
Parameter
Description
–2
–1
Std.
Units
tSU
Address Setup Time
0.53
0.61
0.71
ns
tHOLD
Address Hold Time
0.00
0.00
0.00
ns
tCK2Q
Clock to Out
21.42
24.40
28.68
ns
FMAX
Maximum Clock Frequency
15
15
15
MHz
R ev i si o n 1 5
2- 106
ProASIC3 Flash Family FPGAs
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-14 for more details.
Timing Characteristics
Table 2-125 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tDISU
Test Data Input Setup Time
0.50
0.57
0.67
ns
tDIHD
Test Data Input Hold Time
1.00
1.13
1.33
ns
tTMSSU
Test Mode Select Setup Time
0.50
0.57
0.67
ns
tTMDHD
Test Mode Select Hold Time
1.00
1.13
1.33
ns
tTCK2Q
Clock to Q (data out)
6.00
6.80
8.00
ns
tRSTB2Q
Reset to Q (data out)
20.00
22.67
26.67
ns
FTCKMAX
TCK Maximum Frequency
25.00
22.00
19.00
MHz
tTRSTREM
ResetB Removal Time
0.00
0.00
0.00
ns
tTRSTREC
ResetB Recovery Time
0.20
0.23
0.27
ns
tTRSTMPW
ResetB Minimum Pulse
TBD
TBD
TBD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for
derating values.
R ev i si o n 1 5
2- 107
3 – Pin Descriptions
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine
in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,
both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,
1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied
to GND. An output pad powered by VCCIX and terminated to ground through any resistor, will yield the
leakage current to ground as ~ 0uA, if VCCIX is floating and ~ 3 uA, if VCCIX is grounded.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within
the package and improves input signal integrity. Each bank must have at least one VMV connection, and
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or
3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV
and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V.
When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs
to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground.
Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise
from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in
IGLOO and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for a complete
board solution for the PLL analog power supply and ground.
There is one VCCPLF pin on ProASIC3 devices.
VCOMPLA/B/C/D/E/F PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool
automatically disables the unused PLLs to lower power consumption. The user should tie unused
VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on ProASIC3 devices.
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design.
R ev i si o n 1 5
3-1
Pin Descriptions
If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin
could be tied to GND.
It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If
a device is in a JTAG chain of interconnected boards, the board containing the device can be powered
down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be
able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
GL
•
Output buffer is disabled (with tristate value of high impedance)
•
Input buffer is disabled (with tristate value of high impedance)
•
Weak pull-up is programmed
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO
and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide. All inputs labeled GC/GF
are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2
are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into
the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global
network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure section of the handbook for the device you are using for an explanation of the
naming of global pins.
FF
Flash*Freeze Mode Activation Pin
Flash*Freeze is available on IGLOO, ProASIC3L, and RT ProASIC3 devices. It is not supported on
ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The
FF pin is active-low, has the same characteristics as a single-ended I/O, and must meet the maximum
rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a
regular I/O. For IGLOOe, ProASIC3EL, and RT ProASIC3 only, the FF pin can be configured as a
Schmitt trigger input.
3- 2
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
JTAG Pins
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pullup/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Refer to Table 1
for more information.
Table 1 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance
3.3 V
200 Ω –1 kΩ
2.5 V
200 Ω –1 kΩ
1.8 V
500 Ω –1 kΩ
1.5 V
500 Ω –1 kΩ
Notes:
1. Equivalent parallel resistance if more than one device is on the JTAG chain
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled down.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pulldown resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from Table 1 and must satisfy the parallel resistance value requirement. The
values in Table 1 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
R ev i si o n 1 5
3-3
Pin Descriptions
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements.
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Related Documents
User’s Guides
ProASIC FPGA Fabric User’s Guide
http://www.microsemi.com/soc/documents/PA3_UG.pdf
Packaging
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials are at http://www.microsemi.com/products/solutions/package/docs.aspx.
3- 4
R ev isio n 1 5
4 – Package Pin Assignments
QN48 – Bottom View
Pin 1
48
1
Note: The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
R ev i si o n 1 5
4-1
Package Pin Assignments
QN48
QN48
Pin Number
A3P030 Function
Pin Number
A3P030 Function
1
IO82RSB1
37
IO24RSB0
2
GEC0/IO73RSB1
38
IO22RSB0
3
GEA0/IO72RSB1
39
IO20RSB0
4
GEB0/IO71RSB1
40
IO18RSB0
5
GND
41
IO16RSB0
6
VCCIB1
42
IO14RSB0
7
IO68RSB1
43
IO10RSB0
8
IO67RSB1
44
IO08RSB0
9
IO66RSB1
45
IO06RSB0
10
IO65RSB1
46
IO04RSB0
11
IO64RSB1
47
IO02RSB0
12
IO62RSB1
48
IO00RSB0
13
IO61RSB1
14
IO60RSB1
15
IO57RSB1
16
IO55RSB1
17
IO53RSB1
18
VCC
19
VCCIB1
20
IO46RSB1
21
IO42RSB1
22
TCK
23
TDI
24
TMS
25
VPUMP
26
TDO
27
TRST
28
VJTAG
29
IO38RSB0
30
GDB0/IO34RSB0
31
GDA0/IO33RSB0
32
GDC0/IO32RSB0
33
VCCIB0
34
GND
35
VCC
36
IO25RSB0
4- 2
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
QN68 – Bottom View
Pin A1 Mark
68
1
Note: The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
R ev i si o n 1 5
4-3
Package Pin Assignments
QN68
QN68
Pin Number
A3P015 Function
Pin Number
A3P015 Function
1
IO82RSB1
37
TRST
2
IO80RSB1
38
VJTAG
3
IO78RSB1
39
IO40RSB0
4
IO76RSB1
40
IO37RSB0
5
GEC0/IO73RSB1
41
GDB0/IO34RSB0
6
GEA0/IO72RSB1
42
GDA0/IO33RSB0
7
GEB0/IO71RSB1
43
GDC0/IO32RSB0
8
VCC
44
VCCIB0
9
GND
45
GND
10
VCCIB1
46
VCC
11
IO68RSB1
47
IO31RSB0
12
IO67RSB1
48
IO29RSB0
13
IO66RSB1
49
IO28RSB0
14
IO65RSB1
50
IO27RSB0
15
IO64RSB1
51
IO25RSB0
16
IO63RSB1
52
IO24RSB0
17
IO62RSB1
53
IO22RSB0
18
IO60RSB1
54
IO21RSB0
19
IO58RSB1
55
IO19RSB0
20
IO56RSB1
56
IO17RSB0
21
IO54RSB1
57
IO15RSB0
22
IO52RSB1
58
IO14RSB0
23
IO51RSB1
59
VCCIB0
24
VCC
60
GND
25
GND
61
VCC
26
VCCIB1
62
IO12RSB0
27
IO50RSB1
63
IO10RSB0
28
IO48RSB1
64
IO08RSB0
29
IO46RSB1
65
IO06RSB0
30
IO44RSB1
66
IO04RSB0
31
IO42RSB1
67
IO02RSB0
32
TCK
68
IO00RSB0
33
TDI
34
TMS
35
VPUMP
36
TDO
4- 4
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
QN68
QN68
Pin Number
A3P030 Function
Pin Number
A3P030 Function
1
IO82RSB1
37
TRST
2
IO80RSB1
38
VJTAG
3
IO78RSB1
39
IO40RSB0
4
IO76RSB1
40
IO37RSB0
5
GEC0/IO73RSB1
41
GDB0/IO34RSB0
6
GEA0/IO72RSB1
42
GDA0/IO33RSB0
7
GEB0/IO71RSB1
43
GDC0/IO32RSB0
8
VCC
44
VCCIB0
9
GND
45
GND
10
VCCIB1
46
VCC
11
IO68RSB1
47
IO31RSB0
12
IO67RSB1
48
IO29RSB0
13
IO66RSB1
49
IO28RSB0
14
IO65RSB1
50
IO27RSB0
15
IO64RSB1
51
IO25RSB0
16
IO63RSB1
52
IO24RSB0
17
IO62RSB1
53
IO22RSB0
18
IO60RSB1
54
IO21RSB0
19
IO58RSB1
55
IO19RSB0
20
IO56RSB1
56
IO17RSB0
21
IO54RSB1
57
IO15RSB0
22
IO52RSB1
58
IO14RSB0
23
IO51RSB1
59
VCCIB0
24
VCC
60
GND
25
GND
61
VCC
26
VCCIB1
62
IO12RSB0
27
IO50RSB1
63
IO10RSB0
28
IO48RSB1
64
IO08RSB0
29
IO46RSB1
65
IO06RSB0
30
IO44RSB1
66
IO04RSB0
31
IO42RSB1
67
IO02RSB0
32
TCK
68
IO00RSB0
33
TDI
34
TMS
35
VPUMP
36
TDO
R ev i si o n 1 5
4-5
Package Pin Assignments
QN132 – Bottom View
A37
B34
C31
A48
B44
C40
Pin A1Mark
D4
D1
A36
B33
C30
C1
C21
B23
A25
C10
B11
A12
D3
B1
A1
D2
Optional
Corner Pad (4x)
C20
B22
A24
C11
B12
A13
Notes:
1. The die attach paddle center of the package is tied to ground (GND).
2. Option corner pads come with this device and package combination. It is optional to tie them to ground or leave them
floating.
3. The QN132 package is discontinued and is not available for ProASIC3 devices. For Package Manufacturing and
Environmental information, visit the Resource Center at:
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4- 6
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number
A3P030 Function
Pin Number
A3P030 Function
Pin Number
A3P030 Function
A1
IO01RSB1
A37
IO26RSB0
B25
GND
A2
IO81RSB1
A38
IO23RSB0
B26
NC
A3
NC
A39
NC
B27
IO41RSB0
A4
IO80RSB1
A40
IO22RSB0
B28
GND
A5
GEC0/IO77RSB1
A41
IO20RSB0
B29
GDA0/IO37RSB0
A6
NC
A42
IO18RSB0
B30
NC
A7
GEB0/IO75RSB1
A43
VCC
B31
GND
A8
IO73RSB1
A44
IO15RSB0
B32
IO33RSB0
A9
NC
A45
IO12RSB0
B33
IO30RSB0
A10
VCC
A46
IO10RSB0
B34
IO27RSB0
A11
IO71RSB1
A47
IO09RSB0
B35
IO24RSB0
A12
IO68RSB1
A48
IO06RSB0
B36
GND
A13
IO63RSB1
B1
IO02RSB1
B37
IO21RSB0
A14
IO60RSB1
B2
IO82RSB1
B38
IO19RSB0
A15
NC
B3
GND
B39
GND
A16
IO59RSB1
B4
IO79RSB1
B40
IO16RSB0
A17
IO57RSB1
B5
NC
B41
IO13RSB0
A18
VCC
B6
GND
B42
GND
A19
IO54RSB1
B7
IO74RSB1
B43
IO08RSB0
A20
IO52RSB1
B8
NC
B44
IO05RSB0
A21
IO49RSB1
B9
GND
C1
IO03RSB1
A22
IO48RSB1
B10
IO70RSB1
C2
IO00RSB1
A23
IO47RSB1
B11
IO67RSB1
C3
NC
A24
TDI
B12
IO64RSB1
C4
IO78RSB1
A25
TRST
B13
IO61RSB1
C5
GEA0/IO76RSB1
A26
IO44RSB0
B14
GND
C6
NC
A27
NC
B15
IO58RSB1
C7
NC
A28
IO43RSB0
B16
IO56RSB1
C8
VCCIB1
A29
IO42RSB0
B17
GND
C9
IO69RSB1
A30
IO40RSB0
B18
IO53RSB1
C10
IO66RSB1
A31
IO39RSB0
B19
IO50RSB1
C11
IO65RSB1
A32
GDC0/IO36RSB0
B20
GND
C12
IO62RSB1
A33
NC
B21
IO46RSB1
C13
NC
A34
VCC
B22
TMS
C14
NC
A35
IO34RSB0
B23
TDO
C15
IO55RSB1
A36
IO31RSB0
B24
IO45RSB0
C16
VCCIB1
R ev i si o n 1 5
4-7
Package Pin Assignments
QN132
Pin Number
A3P030 Function
C17
IO51RSB1
C18
NC
C19
TCK
C20
NC
C21
VPUMP
C22
VJTAG
C23
NC
C24
NC
C25
NC
C26
GDB0/IO38RSB0
C27
NC
C28
VCCIB0
C29
IO32RSB0
C30
IO29RSB0
C31
IO28RSB0
C32
IO25RSB0
C33
NC
C34
NC
C35
VCCIB0
C36
IO17RSB0
C37
IO14RSB0
C38
IO11RSB0
C39
IO07RSB0
C40
IO04RSB0
D1
GND
D2
GND
D3
GND
D4
GND
4- 8
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number
A3P060 Function
Pin Number
A3P060 Function
Pin Number
A3P060 Function
A1
GAB2/IO00RSB1
A37
GBB1/IO25RSB0
B25
GND
A2
IO93RSB1
A38
GBC0/IO22RSB0
B26
NC
A3
VCCIB1
A39
VCCIB0
B27
GCB2/IO45RSB0
A4
GFC1/IO89RSB1
A40
IO21RSB0
B28
GND
A5
GFB0/IO86RSB1
A41
IO18RSB0
B29
GCB0/IO41RSB0
A6
VCCPLF
A42
IO15RSB0
B30
GCC1/IO38RSB0
A7
GFA1/IO84RSB1
A43
IO14RSB0
B31
GND
A8
GFC2/IO81RSB1
A44
IO11RSB0
B32
GBB2/IO30RSB0
A9
IO78RSB1
A45
GAB1/IO08RSB0
B33
VMV0
A10
VCC
A46
NC
B34
GBA0/IO26RSB0
A11
GEB1/IO75RSB1
A47
GAB0/IO07RSB0
B35
GBC1/IO23RSB0
A12
GEA0/IO72RSB1
A48
IO04RSB0
B36
GND
A13
GEC2/IO69RSB1
B1
IO01RSB1
B37
IO20RSB0
A14
IO65RSB1
B2
GAC2/IO94RSB1
B38
IO17RSB0
A15
VCC
B3
GND
B39
GND
A16
IO64RSB1
B4
GFC0/IO88RSB1
B40
IO12RSB0
A17
IO63RSB1
B5
VCOMPLF
B41
GAC0/IO09RSB0
A18
IO62RSB1
B6
GND
B42
GND
A19
IO61RSB1
B7
GFB2/IO82RSB1
B43
GAA1/IO06RSB0
A20
IO58RSB1
B8
IO79RSB1
B44
GNDQ
A21
GDB2/IO55RSB1
B9
GND
C1
GAA2/IO02RSB1
A22
NC
B10
GEB0/IO74RSB1
C2
IO95RSB1
A23
GDA2/IO54RSB1
B11
VMV1
C3
VCC
A24
TDI
B12
GEB2/IO70RSB1
C4
GFB1/IO87RSB1
A25
TRST
B13
IO67RSB1
C5
GFA0/IO85RSB1
A26
GDC1/IO48RSB0
B14
GND
C6
GFA2/IO83RSB1
A27
VCC
B15
NC
C7
IO80RSB1
A28
IO47RSB0
B16
NC
C8
VCCIB1
A29
GCC2/IO46RSB0
B17
GND
C9
GEA1/IO73RSB1
A30
GCA2/IO44RSB0
B18
IO59RSB1
C10
GNDQ
A31
GCA0/IO43RSB0
B19
GDC2/IO56RSB1
C11
GEA2/IO71RSB1
A32
GCB1/IO40RSB0
B20
GND
C12
IO68RSB1
A33
IO36RSB0
B21
GNDQ
C13
VCCIB1
A34
VCC
B22
TMS
C14
NC
A35
IO31RSB0
B23
TDO
C15
NC
A36
GBA2/IO28RSB0
B24
GDC0/IO49RSB0
C16
IO60RSB1
R ev i si o n 1 5
4-9
Package Pin Assignments
QN132
Pin Number
A3P060 Function
C17
IO57RSB1
C18
NC
C19
TCK
C20
VMV1
C21
VPUMP
C22
VJTAG
C23
VCCIB0
C24
NC
C25
NC
C26
GCA1/IO42RSB0
C27
GCC0/IO39RSB0
C28
VCCIB0
C29
IO29RSB0
C30
GNDQ
C31
GBA1/IO27RSB0
C32
GBB0/IO24RSB0
C33
VCC
C34
IO19RSB0
C35
IO16RSB0
C36
IO13RSB0
C37
GAC1/IO10RSB0
C38
NC
C39
GAA0/IO05RSB0
C40
VMV0
D1
GND
D2
GND
D3
GND
D4
GND
4- 10
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number
A3P125 Function
Pin Number
A3P125 Function
Pin Number
A3P125 Function
A1
GAB2/IO69RSB1
A37
GBB1/IO38RSB0
B25
GND
A2
IO130RSB1
A38
GBC0/IO35RSB0
B26
NC
A3
VCCIB1
A39
VCCIB0
B27
GCB2/IO58RSB0
A4
GFC1/IO126RSB1
A40
IO28RSB0
B28
GND
A5
GFB0/IO123RSB1
A41
IO22RSB0
B29
GCB0/IO54RSB0
A6
VCCPLF
A42
IO18RSB0
B30
GCC1/IO51RSB0
A7
GFA1/IO121RSB1
A43
IO14RSB0
B31
GND
A8
GFC2/IO118RSB1
A44
IO11RSB0
B32
GBB2/IO43RSB0
A9
IO115RSB1
A45
IO07RSB0
B33
VMV0
A10
VCC
A46
VCC
B34
GBA0/IO39RSB0
A11
GEB1/IO110RSB1
A47
GAC1/IO05RSB0
B35
GBC1/IO36RSB0
A12
GEA0/IO107RSB1
A48
GAB0/IO02RSB0
B36
GND
A13
GEC2/IO104RSB1
B1
IO68RSB1
B37
IO26RSB0
A14
IO100RSB1
B2
GAC2/IO131RSB1
B38
IO21RSB0
A15
VCC
B3
GND
B39
GND
A16
IO99RSB1
B4
GFC0/IO125RSB1
B40
IO13RSB0
A17
IO96RSB1
B5
VCOMPLF
B41
IO08RSB0
A18
IO94RSB1
B6
GND
B42
GND
A19
IO91RSB1
B7
GFB2/IO119RSB1
B43
GAC0/IO04RSB0
A20
IO85RSB1
B8
IO116RSB1
B44
GNDQ
A21
IO79RSB1
B9
GND
C1
GAA2/IO67RSB1
A22
VCC
B10
GEB0/IO109RSB1
C2
IO132RSB1
A23
GDB2/IO71RSB1
B11
VMV1
C3
VCC
A24
TDI
B12
GEB2/IO105RSB1
C4
GFB1/IO124RSB1
A25
TRST
B13
IO101RSB1
C5
GFA0/IO122RSB1
A26
GDC1/IO61RSB0
B14
GND
C6
GFA2/IO120RSB1
A27
VCC
B15
IO98RSB1
C7
IO117RSB1
A28
IO60RSB0
B16
IO95RSB1
C8
VCCIB1
A29
GCC2/IO59RSB0
B17
GND
C9
GEA1/IO108RSB1
A30
GCA2/IO57RSB0
B18
IO87RSB1
C10
GNDQ
A31
GCA0/IO56RSB0
B19
IO81RSB1
C11
GEA2/IO106RSB1
A32
GCB1/IO53RSB0
B20
GND
C12
IO103RSB1
A33
IO49RSB0
B21
GNDQ
C13
VCCIB1
A34
VCC
B22
TMS
C14
IO97RSB1
A35
IO44RSB0
B23
TDO
C15
IO93RSB1
A36
GBA2/IO41RSB0
B24
GDC0/IO62RSB0
C16
IO89RSB1
R ev i si o n 1 5
4- 11
Package Pin Assignments
QN132
Pin Number
A3P125 Function
C17
IO83RSB1
C18
VCCIB1
C19
TCK
C20
VMV1
C21
VPUMP
C22
VJTAG
C23
VCCIB0
C24
NC
C25
NC
C26
GCA1/IO55RSB0
C27
GCC0/IO52RSB0
C28
VCCIB0
C29
IO42RSB0
C30
GNDQ
C31
GBA1/IO40RSB0
C32
GBB0/IO37RSB0
C33
VCC
C34
IO24RSB0
C35
IO19RSB0
C36
IO16RSB0
C37
IO10RSB0
C38
VCCIB0
C39
GAB1/IO03RSB0
C40
VMV0
D1
GND
D2
GND
D3
GND
D4
GND
4- 12
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number
A3P250 Function
Pin Number
A3P250 Function
Pin Number
A3P250 Function
A1
GAB2/IO117UPB3
A37
GBB1/IO38RSB0
B25
GND
A2
IO117VPB3
A38
GBC0/IO35RSB0
B26
IO54PDB1
A3
VCCIB3
A39
VCCIB0
B27
GCB2/IO52PDB1
A4
GFC1/IO110PDB3
A40
IO28RSB0
B28
GND
A5
GFB0/IO109NPB3
A41
IO22RSB0
B29
GCB0/IO49NDB1
A6
VCCPLF
A42
IO18RSB0
B30
GCC1/IO48PDB1
A7
GFA1/IO108PPB3
A43
IO14RSB0
B31
GND
A8
GFC2/IO105PPB3
A44
IO11RSB0
B32
GBB2/IO42PDB1
A9
IO103NDB3
A45
IO07RSB0
B33
VMV1
A10
VCC
A46
VCC
B34
GBA0/IO39RSB0
A11
GEA1/IO98PPB3
A47
GAC1/IO05RSB0
B35
GBC1/IO36RSB0
A12
GEA0/IO98NPB3
A48
GAB0/IO02RSB0
B36
GND
A13
GEC2/IO95RSB2
B1
IO118VDB3
B37
IO26RSB0
A14
IO91RSB2
B2
GAC2/IO116UDB3
B38
IO21RSB0
A15
VCC
B3
GND
B39
GND
A16
IO90RSB2
B4
GFC0/IO110NDB3
B40
IO13RSB0
A17
IO87RSB2
B5
VCOMPLF
B41
IO08RSB0
A18
IO85RSB2
B6
GND
B42
GND
A19
IO82RSB2
B7
GFB2/IO106PSB3
B43
GAC0/IO04RSB0
A20
IO76RSB2
B8
IO103PDB3
B44
GNDQ
A21
IO70RSB2
B9
GND
C1
GAA2/IO118UDB3
A22
VCC
B10
GEB0/IO99NDB3
C2
IO116VDB3
A23
GDB2/IO62RSB2
B11
VMV3
C3
VCC
A24
TDI
B12
GEB2/IO96RSB2
C4
GFB1/IO109PPB3
A25
TRST
B13
IO92RSB2
C5
GFA0/IO108NPB3
A26
GDC1/IO58UDB1
B14
GND
C6
GFA2/IO107PSB3
A27
VCC
B15
IO89RSB2
C7
IO105NPB3
A28
IO54NDB1
B16
IO86RSB2
C8
VCCIB3
A29
IO52NDB1
B17
GND
C9
GEB1/IO99PDB3
A30
GCA2/IO51PPB1
B18
IO78RSB2
C10
GNDQ
A31
GCA0/IO50NPB1
B19
IO72RSB2
C11
GEA2/IO97RSB2
A32
GCB1/IO49PDB1
B20
GND
C12
IO94RSB2
A33
IO47NSB1
B21
GNDQ
C13
VCCIB2
A34
VCC
B22
TMS
C14
IO88RSB2
A35
IO41NPB1
B23
TDO
C15
IO84RSB2
A36
GBA2/IO41PPB1
B24
GDC0/IO58VDB1
C16
IO80RSB2
R ev i si o n 1 5
4- 13
Package Pin Assignments
QN132
Pin Number
A3P250 Function
C17
IO74RSB2
C18
VCCIB2
C19
TCK
C20
VMV2
C21
VPUMP
C22
VJTAG
C23
VCCIB1
C24
IO53NSB1
C25
IO51NPB1
C26
GCA1/IO50PPB1
C27
GCC0/IO48NDB1
C28
VCCIB1
C29
IO42NDB1
C30
GNDQ
C31
GBA1/IO40RSB0
C32
GBB0/IO37RSB0
C33
VCC
C34
IO24RSB0
C35
IO19RSB0
C36
IO16RSB0
C37
IO10RSB0
C38
VCCIB0
C39
GAB1/IO03RSB0
C40
VMV0
D1
GND
D2
GND
D3
GND
D4
GND
4- 14
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
CS121 – Bottom View
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
Note: The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
R ev i si o n 1 5
4- 15
Package Pin Assignments
CS121
CS121
CS121
Pin Number
A3P060 Function
Pin Number
A3P060 Function
Pin Number
A3P060 Function
A1
GNDQ
D4
IO10RSB0
G7
VCC
A2
IO01RSB0
D5
IO11RSB0
G8
GDC0/IO46RSB0
A3
GAA1/IO03RSB0
D6
IO18RSB0
G9
GDA1/IO49RSB0
A4
GAC1/IO07RSB0
D7
IO32RSB0
G10
GDB0/IO48RSB0
A5
IO15RSB0
D8
IO31RSB0
G11
GCA0/IO40RSB0
A6
IO13RSB0
D9
GCA2/IO41RSB0
H1
IO75RSB1
A7
IO17RSB0
D10
IO30RSB0
H2
IO76RSB1
A8
GBB1/IO22RSB0
D11
IO33RSB0
H3
GFC2/IO78RSB1
A9
GBA1/IO24RSB0
E1
IO87RSB1
H4
GFA2/IO80RSB1
A10
GNDQ
E2
GFC0/IO85RSB1
H5
IO77RSB1
A11
VMV0
E3
IO92RSB1
H6
GEC2/IO66RSB1
B1
GAA2/IO95RSB1
E4
IO94RSB1
H7
IO54RSB1
B2
IO00RSB0
E5
VCC
H8
GDC2/IO53RSB1
B3
GAA0/IO02RSB0
E6
VCCIB0
H9
VJTAG
B4
GAC0/IO06RSB0
E7
GND
H10
TRST
B5
IO08RSB0
E8
GCC0/IO36RSB0
H11
IO44RSB0
B6
IO12RSB0
E9
IO34RSB0
J1
GEC1/IO74RSB1
B7
IO16RSB0
E10
GCB1/IO37RSB0
J2
GEC0/IO73RSB1
B8
GBC1/IO20RSB0
E11
GCC1/IO35RSB0
J3
GEB1/IO72RSB1
B9
GBB0/IO21RSB0
F1
VCOMPLF
J4
GEA0/IO69RSB1
B10
GBB2/IO27RSB0
F2
GFB0/IO83RSB1
J5
GEB2/IO67RSB1
B11
GBA2/IO25RSB0
F3
GFA0/IO82RSB1
J6
IO62RSB1
C1
IO89RSB1
F4
GFC1/IO86RSB1
J7
GDA2/IO51RSB1
C2
GAC2/IO91RSB1
F5
VCCIB1
J8
GDB2/IO52RSB1
C3
GAB1/IO05RSB0
F6
VCC
J9
TDI
C4
GAB0/IO04RSB0
F7
VCCIB0
J10
TDO
C5
IO09RSB0
F8
GCB2/IO42RSB0
J11
GDC1/IO45RSB0
C6
IO14RSB0
F9
GCC2/IO43RSB0
K1
GEB0/IO71RSB1
C7
GBA0/IO23RSB0
F10
GCB0/IO38RSB0
K2
GEA1/IO70RSB1
C8
GBC0/IO19RSB0
F11
GCA1/IO39RSB0
K3
GEA2/IO68RSB1
C9
IO26RSB0
G1
VCCPLF
K4
IO64RSB1
C10
IO28RSB0
G2
GFB2/IO79RSB1
K5
IO60RSB1
C11
GBC2/IO29RSB0
G3
GFA1/IO81RSB1
K6
IO59RSB1
D1
IO88RSB1
G4
GFB1/IO84RSB1
K7
IO56RSB1
D2
IO90RSB1
G5
GND
K8
TCK
D3
GAB2/IO93RSB1
G6
VCCIB1
K9
TMS
4- 16
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
CS121
Pin Number
A3P060 Function
K10
VPUMP
K11
GDB1/IO47RSB0
L1
VMV1
L2
GNDQ
L3
IO65RSB1
L4
IO63RSB1
L5
IO61RSB1
L6
IO58RSB1
L7
IO57RSB1
L8
IO55RSB1
L9
GNDQ
L10
GDA0/IO50RSB0
L11
VMV1
R ev i si o n 1 5
4- 17
Package Pin Assignments
VQ100 – Top View
100
1
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4- 18
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
VQ100
VQ100
VQ100
Pin Number
A3P030 Function
Pin Number
A3P030 Function
Pin Number
A3P030 Function
1
GND
37
VCC
73
IO27RSB0
2
IO82RSB1
38
GND
74
IO26RSB0
3
IO81RSB1
39
VCCIB1
75
IO25RSB0
4
IO80RSB1
40
IO49RSB1
76
IO24RSB0
5
IO79RSB1
41
IO47RSB1
77
IO23RSB0
6
IO78RSB1
42
IO46RSB1
78
IO22RSB0
7
IO77RSB1
43
IO45RSB1
79
IO21RSB0
8
IO76RSB1
44
IO44RSB1
80
IO20RSB0
9
GND
45
IO43RSB1
81
IO19RSB0
10
IO75RSB1
46
IO42RSB1
82
IO18RSB0
11
IO74RSB1
47
TCK
83
IO17RSB0
12
GEC0/IO73RSB1
48
TDI
84
IO16RSB0
13
GEA0/IO72RSB1
49
TMS
85
IO15RSB0
14
GEB0/IO71RSB1
50
NC
86
IO14RSB0
15
IO70RSB1
51
GND
87
VCCIB0
16
IO69RSB1
52
VPUMP
88
GND
17
VCC
53
NC
89
VCC
18
VCCIB1
54
TDO
90
IO12RSB0
19
IO68RSB1
55
TRST
91
IO10RSB0
20
IO67RSB1
56
VJTAG
92
IO08RSB0
21
IO66RSB1
57
IO41RSB0
93
IO07RSB0
22
IO65RSB1
58
IO40RSB0
94
IO06RSB0
23
IO64RSB1
59
IO39RSB0
95
IO05RSB0
24
IO63RSB1
60
IO38RSB0
96
IO04RSB0
25
IO62RSB1
61
IO37RSB0
97
IO03RSB0
26
IO61RSB1
62
IO36RSB0
98
IO02RSB0
27
IO60RSB1
63
GDB0/IO34RSB0
99
IO01RSB0
28
IO59RSB1
64
GDA0/IO33RSB0
100
IO00RSB0
29
IO58RSB1
65
GDC0/IO32RSB0
30
IO57RSB1
66
VCCIB0
31
IO56RSB1
67
GND
32
IO55RSB1
68
VCC
33
IO54RSB1
69
IO31RSB0
34
IO53RSB1
70
IO30RSB0
35
IO52RSB1
71
IO29RSB0
36
IO51RSB1
72
IO28RSB0
R ev i si o n 1 5
4- 19
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number
A3P060 Function
Pin Number
A3P060 Function
Pin Number
A3P060 Function
1
GND
37
VCC
73
GBA2/IO25RSB0
2
GAA2/IO51RSB1
38
GND
74
VMV0
3
IO52RSB1
39
VCCIB1
75
GNDQ
4
GAB2/IO53RSB1
40
IO60RSB1
76
GBA1/IO24RSB0
5
IO95RSB1
41
IO59RSB1
77
GBA0/IO23RSB0
6
GAC2/IO94RSB1
42
IO58RSB1
78
GBB1/IO22RSB0
7
IO93RSB1
43
IO57RSB1
79
GBB0/IO21RSB0
8
IO92RSB1
44
GDC2/IO56RSB1
80
GBC1/IO20RSB0
9
GND
45
GDB2/IO55RSB1
81
GBC0/IO19RSB0
10
GFB1/IO87RSB1
46
GDA2/IO54RSB1
82
IO18RSB0
11
GFB0/IO86RSB1
47
TCK
83
IO17RSB0
12
VCOMPLF
48
TDI
84
IO15RSB0
13
GFA0/IO85RSB1
49
TMS
85
IO13RSB0
14
VCCPLF
50
VMV1
86
IO11RSB0
15
GFA1/IO84RSB1
51
GND
87
VCCIB0
16
GFA2/IO83RSB1
52
VPUMP
88
GND
17
VCC
53
NC
89
VCC
18
VCCIB1
54
TDO
90
IO10RSB0
19
GEC1/IO77RSB1
55
TRST
91
IO09RSB0
20
GEB1/IO75RSB1
56
VJTAG
92
IO08RSB0
21
GEB0/IO74RSB1
57
GDA1/IO49RSB0
93
GAC1/IO07RSB0
22
GEA1/IO73RSB1
58
GDC0/IO46RSB0
94
GAC0/IO06RSB0
23
GEA0/IO72RSB1
59
GDC1/IO45RSB0
95
GAB1/IO05RSB0
24
VMV1
60
GCC2/IO43RSB0
96
GAB0/IO04RSB0
25
GNDQ
61
GCB2/IO42RSB0
97
GAA1/IO03RSB0
26
GEA2/IO71RSB1
62
GCA0/IO40RSB0
98
GAA0/IO02RSB0
27
GEB2/IO70RSB1
63
GCA1/IO39RSB0
99
IO01RSB0
28
GEC2/IO69RSB1
64
GCC0/IO36RSB0
100
IO00RSB0
29
IO68RSB1
65
GCC1/IO35RSB0
30
IO67RSB1
66
VCCIB0
31
IO66RSB1
67
GND
32
IO65RSB1
68
VCC
33
IO64RSB1
69
IO31RSB0
34
IO63RSB1
70
GBC2/IO29RSB0
35
IO62RSB1
71
GBB2/IO27RSB0
36
IO61RSB1
72
IO26RSB0
4- 20
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
VQ100
VQ100
VQ100
Pin Number
A3P125 Function
Pin Number
A3P125 Function
Pin Number
A3P125 Function
1
GND
37
VCC
73
GBA2/IO41RSB0
2
GAA2/IO67RSB1
38
GND
74
VMV0
3
IO68RSB1
39
VCCIB1
75
GNDQ
4
GAB2/IO69RSB1
40
IO87RSB1
76
GBA1/IO40RSB0
5
IO132RSB1
41
IO84RSB1
77
GBA0/IO39RSB0
6
GAC2/IO131RSB1
42
IO81RSB1
78
GBB1/IO38RSB0
7
IO130RSB1
43
IO75RSB1
79
GBB0/IO37RSB0
8
IO129RSB1
44
GDC2/IO72RSB1
80
GBC1/IO36RSB0
9
GND
45
GDB2/IO71RSB1
81
GBC0/IO35RSB0
10
GFB1/IO124RSB1
46
GDA2/IO70RSB1
82
IO32RSB0
11
GFB0/IO123RSB1
47
TCK
83
IO28RSB0
12
VCOMPLF
48
TDI
84
IO25RSB0
13
GFA0/IO122RSB1
49
TMS
85
IO22RSB0
14
VCCPLF
50
VMV1
86
IO19RSB0
15
GFA1/IO121RSB1
51
GND
87
VCCIB0
16
GFA2/IO120RSB1
52
VPUMP
88
GND
17
VCC
53
NC
89
VCC
18
VCCIB1
54
TDO
90
IO15RSB0
19
GEC0/IO111RSB1
55
TRST
91
IO13RSB0
20
GEB1/IO110RSB1
56
VJTAG
92
IO11RSB0
21
GEB0/IO109RSB1
57
GDA1/IO65RSB0
93
IO09RSB0
22
GEA1/IO108RSB1
58
GDC0/IO62RSB0
94
IO07RSB0
23
GEA0/IO107RSB1
59
GDC1/IO61RSB0
95
GAC1/IO05RSB0
24
VMV1
60
GCC2/IO59RSB0
96
GAC0/IO04RSB0
25
GNDQ
61
GCB2/IO58RSB0
97
GAB1/IO03RSB0
26
GEA2/IO106RSB1
62
GCA0/IO56RSB0
98
GAB0/IO02RSB0
27
GEB2/IO105RSB1
63
GCA1/IO55RSB0
99
GAA1/IO01RSB0
28
GEC2/IO104RSB1
64
GCC0/IO52RSB0
100
GAA0/IO00RSB0
29
IO102RSB1
65
GCC1/IO51RSB0
30
IO100RSB1
66
VCCIB0
31
IO99RSB1
67
GND
32
IO97RSB1
68
VCC
33
IO96RSB1
69
IO47RSB0
34
IO95RSB1
70
GBC2/IO45RSB0
35
IO94RSB1
71
GBB2/IO43RSB0
36
IO93RSB1
72
IO42RSB0
R ev i si o n 1 5
4- 21
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number
A3P250 Function
Pin Number
A3P250 Function
Pin Number
A3P250 Function
1
GND
37
VCC
73
GBA2/IO41PDB1
2
GAA2/IO118UDB3
38
GND
74
VMV1
3
IO118VDB3
39
VCCIB2
75
GNDQ
4
GAB2/IO117UDB3
40
IO77RSB2
76
GBA1/IO40RSB0
5
IO117VDB3
41
IO74RSB2
77
GBA0/IO39RSB0
6
GAC2/IO116UDB3
42
IO71RSB2
78
GBB1/IO38RSB0
7
IO116VDB3
43
GDC2/IO63RSB2
79
GBB0/IO37RSB0
8
IO112PSB3
44
GDB2/IO62RSB2
80
GBC1/IO36RSB0
9
GND
45
GDA2/IO61RSB2
81
GBC0/IO35RSB0
10
GFB1/IO109PDB3
46
GNDQ
82
IO29RSB0
11
GFB0/IO109NDB3
47
TCK
83
IO27RSB0
12
VCOMPLF
48
TDI
84
IO25RSB0
13
GFA0/IO108NPB3
49
TMS
85
IO23RSB0
14
VCCPLF
50
VMV2
86
IO21RSB0
15
GFA1/IO108PPB3
51
GND
87
VCCIB0
16
GFA2/IO107PSB3
52
VPUMP
88
GND
17
VCC
53
NC
89
VCC
18
VCCIB3
54
TDO
90
IO15RSB0
19
GFC2/IO105PSB3
55
TRST
91
IO13RSB0
20
GEC1/IO100PDB3
56
VJTAG
92
IO11RSB0
21
GEC0/IO100NDB3
57
GDA1/IO60USB1
93
GAC1/IO05RSB0
22
GEA1/IO98PDB3
58
GDC0/IO58VDB1
94
GAC0/IO04RSB0
23
GEA0/IO98NDB3
59
GDC1/IO58UDB1
95
GAB1/IO03RSB0
24
VMV3
60
IO52NDB1
96
GAB0/IO02RSB0
25
GNDQ
61
GCB2/IO52PDB1
97
GAA1/IO01RSB0
26
GEA2/IO97RSB2
62
GCA1/IO50PDB1
98
GAA0/IO00RSB0
27
GEB2/IO96RSB2
63
GCA0/IO50NDB1
99
GNDQ
28
GEC2/IO95RSB2
64
GCC0/IO48NDB1
100
VMV0
29
IO93RSB2
65
GCC1/IO48PDB1
30
IO92RSB2
66
VCCIB1
31
IO91RSB2
67
GND
32
IO90RSB2
68
VCC
33
IO88RSB2
69
IO43NDB1
34
IO86RSB2
70
GBC2/IO43PDB1
35
IO85RSB2
71
GBB2/IO42PSB1
36
IO84RSB2
72
IO41NDB1
4- 22
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
TQ144 – Top View
144
1
144-Pin
TQFP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
R ev i si o n 1 5
4- 23
Package Pin Assignments
TQ144
TQ144
TQ144
Pin Number
A3P060 Function
Pin Number
A3P060 Function
Pin Number
A3P060 Function
1
GAA2/IO51RSB1
37
NC
73
VPUMP
2
IO52RSB1
38
GEA2/IO71RSB1
74
NC
3
GAB2/IO53RSB1
39
GEB2/IO70RSB1
75
TDO
4
IO95RSB1
40
GEC2/IO69RSB1
76
TRST
5
GAC2/IO94RSB1
41
IO68RSB1
77
VJTAG
6
IO93RSB1
42
IO67RSB1
78
GDA0/IO50RSB0
7
IO92RSB1
43
IO66RSB1
79
GDB0/IO48RSB0
8
IO91RSB1
44
IO65RSB1
80
GDB1/IO47RSB0
9
VCC
45
VCC
81
VCCIB0
10
GND
46
GND
82
GND
11
VCCIB1
47
VCCIB1
83
IO44RSB0
12
IO90RSB1
48
NC
84
GCC2/IO43RSB0
13
GFC1/IO89RSB1
49
IO64RSB1
85
GCB2/IO42RSB0
14
GFC0/IO88RSB1
50
NC
86
GCA2/IO41RSB0
15
GFB1/IO87RSB1
51
IO63RSB1
87
GCA0/IO40RSB0
16
GFB0/IO86RSB1
52
NC
88
GCA1/IO39RSB0
17
VCOMPLF
53
IO62RSB1
89
GCB0/IO38RSB0
18
GFA0/IO85RSB1
54
NC
90
GCB1/IO37RSB0
19
VCCPLF
55
IO61RSB1
91
GCC0/IO36RSB0
20
GFA1/IO84RSB1
56
NC
92
GCC1/IO35RSB0
21
GFA2/IO83RSB1
57
NC
93
IO34RSB0
22
GFB2/IO82RSB1
58
IO60RSB1
94
IO33RSB0
23
GFC2/IO81RSB1
59
IO59RSB1
95
NC
24
IO80RSB1
60
IO58RSB1
96
NC
25
IO79RSB1
61
IO57RSB1
97
NC
26
IO78RSB1
62
NC
98
VCCIB0
27
GND
63
GND
99
GND
28
VCCIB1
64
NC
100
VCC
29
GEC1/IO77RSB1
65
GDC2/IO56RSB1
101
IO30RSB0
30
GEC0/IO76RSB1
66
GDB2/IO55RSB1
102
GBC2/IO29RSB0
31
GEB1/IO75RSB1
67
GDA2/IO54RSB1
103
IO28RSB0
32
GEB0/IO74RSB1
68
GNDQ
104
GBB2/IO27RSB0
33
GEA1/IO73RSB1
69
TCK
105
IO26RSB0
34
GEA0/IO72RSB1
70
TDI
106
GBA2/IO25RSB0
35
VMV1
71
TMS
107
VMV0
36
GNDQ
72
VMV1
108
GNDQ
4- 24
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
TQ144
Pin Number
A3P060 Function
109
NC
110
NC
111
GBA1/IO24RSB0
112
GBA0/IO23RSB0
113
GBB1/IO22RSB0
114
GBB0/IO21RSB0
115
GBC1/IO20RSB0
116
GBC0/IO19RSB0
117
VCCIB0
118
GND
119
VCC
120
IO18RSB0
121
IO17RSB0
122
IO16RSB0
123
IO15RSB0
124
IO14RSB0
125
IO13RSB0
126
IO12RSB0
127
IO11RSB0
128
NC
129
IO10RSB0
130
IO09RSB0
131
IO08RSB0
132
GAC1/IO07RSB0
133
GAC0/IO06RSB0
134
NC
135
GND
136
NC
137
GAB1/IO05RSB0
138
GAB0/IO04RSB0
139
GAA1/IO03RSB0
140
GAA0/IO02RSB0
141
IO01RSB0
142
IO00RSB0
143
GNDQ
144
VMV0
R ev i si o n 1 5
4- 25
Package Pin Assignments
TQ144
TQ144
TQ144
Pin Number
A3P125 Function
Pin Number
A3P125 Function
Pin Number
A3P125 Function
1
GAA2/IO67RSB1
37
NC
73
VPUMP
2
IO68RSB1
38
GEA2/IO106RSB1
74
NC
3
GAB2/IO69RSB1
39
GEB2/IO105RSB1
75
TDO
4
IO132RSB1
40
GEC2/IO104RSB1
76
TRST
5
GAC2/IO131RSB1
41
IO103RSB1
77
VJTAG
6
IO130RSB1
42
IO102RSB1
78
GDA0/IO66RSB0
7
IO129RSB1
43
IO101RSB1
79
GDB0/IO64RSB0
8
IO128RSB1
44
IO100RSB1
80
GDB1/IO63RSB0
9
VCC
45
VCC
81
VCCIB0
10
GND
46
GND
82
GND
11
VCCIB1
47
VCCIB1
83
IO60RSB0
12
IO127RSB1
48
IO99RSB1
84
GCC2/IO59RSB0
13
GFC1/IO126RSB1
49
IO97RSB1
85
GCB2/IO58RSB0
14
GFC0/IO125RSB1
50
IO95RSB1
86
GCA2/IO57RSB0
15
GFB1/IO124RSB1
51
IO93RSB1
87
GCA0/IO56RSB0
16
GFB0/IO123RSB1
52
IO92RSB1
88
GCA1/IO55RSB0
17
VCOMPLF
53
IO90RSB1
89
GCB0/IO54RSB0
18
GFA0/IO122RSB1
54
IO88RSB1
90
GCB1/IO53RSB0
19
VCCPLF
55
IO86RSB1
91
GCC0/IO52RSB0
20
GFA1/IO121RSB1
56
IO84RSB1
92
GCC1/IO51RSB0
21
GFA2/IO120RSB1
57
IO83RSB1
93
IO50RSB0
22
GFB2/IO119RSB1
58
IO82RSB1
94
IO49RSB0
23
GFC2/IO118RSB1
59
IO81RSB1
95
NC
24
IO117RSB1
60
IO80RSB1
96
NC
25
IO116RSB1
61
IO79RSB1
97
NC
26
IO115RSB1
62
VCC
98
VCCIB0
27
GND
63
GND
99
GND
28
VCCIB1
64
VCCIB1
100
VCC
29
GEC1/IO112RSB1
65
GDC2/IO72RSB1
101
IO47RSB0
30
GEC0/IO111RSB1
66
GDB2/IO71RSB1
102
GBC2/IO45RSB0
31
GEB1/IO110RSB1
67
GDA2/IO70RSB1
103
IO44RSB0
32
GEB0/IO109RSB1
68
GNDQ
104
GBB2/IO43RSB0
33
GEA1/IO108RSB1
69
TCK
105
IO42RSB0
34
GEA0/IO107RSB1
70
TDI
106
GBA2/IO41RSB0
35
VMV1
71
TMS
107
VMV0
36
GNDQ
72
VMV1
108
GNDQ
4- 26
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
TQ144
Pin Number
A3P125 Function
109
GBA1/IO40RSB0
110
GBA0/IO39RSB0
111
GBB1/IO38RSB0
112
GBB0/IO37RSB0
113
GBC1/IO36RSB0
114
GBC0/IO35RSB0
115
IO34RSB0
116
IO33RSB0
117
VCCIB0
118
GND
119
VCC
120
IO29RSB0
121
IO28RSB0
122
IO27RSB0
123
IO25RSB0
124
IO23RSB0
125
IO21RSB0
126
IO19RSB0
127
IO17RSB0
128
IO16RSB0
129
IO14RSB0
130
IO12RSB0
131
IO10RSB0
132
IO08RSB0
133
IO06RSB0
134
VCCIB0
135
GND
136
VCC
137
GAC1/IO05RSB0
138
GAC0/IO04RSB0
139
GAB1/IO03RSB0
140
GAB0/IO02RSB0
141
GAA1/IO01RSB0
142
GAA0/IO00RSB0
143
GNDQ
144
VMV0
R ev i si o n 1 5
4- 27
Package Pin Assignments
PQ208 – Top View
1
208
208-Pin PQFP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4- 28
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number
A3P125 Function
Pin Number
A3P125 Function
Pin Number
A3P125 Function
1
GND
37
IO116RSB1
73
IO92RSB1
2
GAA2/IO67RSB1
38
IO115RSB1
74
IO91RSB1
3
IO68RSB1
39
NC
75
IO90RSB1
4
GAB2/IO69RSB1
40
VCCIB1
76
IO89RSB1
5
IO132RSB1
41
GND
77
IO88RSB1
6
GAC2/IO131RSB1
42
IO114RSB1
78
IO87RSB1
7
NC
43
IO113RSB1
79
IO86RSB1
8
NC
44
GEC1/IO112RSB1
80
IO85RSB1
9
IO130RSB1
45
GEC0/IO111RSB1
81
GND
10
IO129RSB1
46
GEB1/IO110RSB1
82
IO84RSB1
11
NC
47
GEB0/IO109RSB1
83
IO83RSB1
12
IO128RSB1
48
GEA1/IO108RSB1
84
IO82RSB1
13
NC
49
GEA0/IO107RSB1
85
IO81RSB1
14
NC
50
VMV1
86
IO80RSB1
15
NC
51
GNDQ
87
IO79RSB1
16
VCC
52
GND
88
VCC
17
GND
53
NC
89
VCCIB1
18
VCCIB1
54
NC
90
IO78RSB1
19
IO127RSB1
55
GEA2/IO106RSB1
91
IO77RSB1
20
NC
56
GEB2/IO105RSB1
92
IO76RSB1
21
GFC1/IO126RSB1
57
GEC2/IO104RSB1
93
IO75RSB1
22
GFC0/IO125RSB1
58
IO103RSB1
94
IO74RSB1
23
GFB1/IO124RSB1
59
IO102RSB1
95
IO73RSB1
24
GFB0/IO123RSB1
60
IO101RSB1
96
GDC2/IO72RSB1
25
VCOMPLF
61
IO100RSB1
97
GND
26
GFA0/IO122RSB1
62
VCCIB1
98
GDB2/IO71RSB1
27
VCCPLF
63
IO99RSB1
99
GDA2/IO70RSB1
28
GFA1/IO121RSB1
64
IO98RSB1
100
GNDQ
29
GND
65
GND
101
TCK
30
GFA2/IO120RSB1
66
IO97RSB1
102
TDI
31
NC
67
IO96RSB1
103
TMS
32
GFB2/IO119RSB1
68
IO95RSB1
104
VMV1
33
NC
69
IO94RSB1
105
GND
34
GFC2/IO118RSB1
70
IO93RSB1
106
VPUMP
35
IO117RSB1
71
VCC
107
NC
36
NC
72
VCCIB1
108
TDO
R ev i si o n 1 5
4- 29
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number
A3P125 Function
Pin Number
A3P125 Function
Pin Number
A3P125 Function
109
TRST
145
IO46RSB0
181
IO21RSB0
110
VJTAG
146
NC
182
IO20RSB0
111
GDA0/IO66RSB0
147
NC
183
IO19RSB0
112
GDA1/IO65RSB0
148
NC
184
IO18RSB0
113
GDB0/IO64RSB0
149
GBC2/IO45RSB0
185
IO17RSB0
114
GDB1/IO63RSB0
150
IO44RSB0
186
VCCIB0
115
GDC0/IO62RSB0
151
GBB2/IO43RSB0
187
VCC
116
GDC1/IO61RSB0
152
IO42RSB0
188
IO16RSB0
117
NC
153
GBA2/IO41RSB0
189
IO15RSB0
118
NC
154
VMV0
190
IO14RSB0
119
NC
155
GNDQ
191
IO13RSB0
120
NC
156
GND
192
IO12RSB0
121
NC
157
NC
193
IO11RSB0
122
GND
158
GBA1/IO40RSB0
194
IO10RSB0
123
VCCIB0
159
GBA0/IO39RSB0
195
GND
124
NC
160
GBB1/IO38RSB0
196
IO09RSB0
125
NC
161
GBB0/IO37RSB0
197
IO08RSB0
126
VCC
162
GND
198
IO07RSB0
127
IO60RSB0
163
GBC1/IO36RSB0
199
IO06RSB0
128
GCC2/IO59RSB0
164
GBC0/IO35RSB0
200
VCCIB0
129
GCB2/IO58RSB0
165
IO34RSB0
201
GAC1/IO05RSB0
130
GND
166
IO33RSB0
202
GAC0/IO04RSB0
131
GCA2/IO57RSB0
167
IO32RSB0
203
GAB1/IO03RSB0
132
GCA0/IO56RSB0
168
IO31RSB0
204
GAB0/IO02RSB0
133
GCA1/IO55RSB0
169
IO30RSB0
205
GAA1/IO01RSB0
134
GCB0/IO54RSB0
170
VCCIB0
206
GAA0/IO00RSB0
135
GCB1/IO53RSB0
171
VCC
207
GNDQ
136
GCC0/IO52RSB0
172
IO29RSB0
208
VMV0
137
GCC1/IO51RSB0
173
IO28RSB0
138
IO50RSB0
174
IO27RSB0
139
IO49RSB0
175
IO26RSB0
140
VCCIB0
176
IO25RSB0
141
GND
177
IO24RSB0
142
VCC
178
GND
143
IO48RSB0
179
IO23RSB0
144
IO47RSB0
180
IO22RSB0
4- 30
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number
A3P250 Function
Pin Number
A3P250 Function
Pin Number
A3P250 Function
1
GND
37
IO104PDB3
73
IO83RSB2
2
GAA2/IO118UDB3
38
IO104NDB3
74
IO82RSB2
3
IO118VDB3
39
IO103PSB3
75
IO81RSB2
4
GAB2/IO117UDB3
40
VCCIB3
76
IO80RSB2
5
IO117VDB3
41
GND
77
IO79RSB2
6
GAC2/IO116UDB3
42
IO101PDB3
78
IO78RSB2
7
IO116VDB3
43
IO101NDB3
79
IO77RSB2
8
IO115UDB3
44
GEC1/IO100PDB3
80
IO76RSB2
9
IO115VDB3
45
GEC0/IO100NDB3
81
GND
10
IO114UDB3
46
GEB1/IO99PDB3
82
IO75RSB2
11
IO114VDB3
47
GEB0/IO99NDB3
83
IO74RSB2
12
IO113PDB3
48
GEA1/IO98PDB3
84
IO73RSB2
13
IO113NDB3
49
GEA0/IO98NDB3
85
IO72RSB2
14
IO112PDB3
50
VMV3
86
IO71RSB2
15
IO112NDB3
51
GNDQ
87
IO70RSB2
16
VCC
52
GND
88
VCC
17
GND
53
NC
89
VCCIB2
18
VCCIB3
54
NC
90
IO69RSB2
19
IO111PDB3
55
GEA2/IO97RSB2
91
IO68RSB2
20
IO111NDB3
56
GEB2/IO96RSB2
92
IO67RSB2
21
GFC1/IO110PDB3
57
GEC2/IO95RSB2
93
IO66RSB2
22
GFC0/IO110NDB3
58
IO94RSB2
94
IO65RSB2
23
GFB1/IO109PDB3
59
IO93RSB2
95
IO64RSB2
24
GFB0/IO109NDB3
60
IO92RSB2
96
GDC2/IO63RSB2
25
VCOMPLF
61
IO91RSB2
97
GND
26
GFA0/IO108NPB3
62
VCCIB2
98
GDB2/IO62RSB2
27
VCCPLF
63
IO90RSB2
99
GDA2/IO61RSB2
28
GFA1/IO108PPB3
64
IO89RSB2
100
GNDQ
29
GND
65
GND
101
TCK
30
GFA2/IO107PDB3
66
IO88RSB2
102
TDI
31
IO107NDB3
67
IO87RSB2
103
TMS
32
GFB2/IO106PDB3
68
IO86RSB2
104
VMV2
33
IO106NDB3
69
IO85RSB2
105
GND
34
GFC2/IO105PDB3
70
IO84RSB2
106
VPUMP
35
IO105NDB3
71
VCC
107
NC
36
NC
72
VCCIB2
108
TDO
R ev i si o n 1 5
4- 31
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number
A3P250 Function
Pin Number
A3P250 Function
Pin Number
A3P250 Function
109
TRST
145
IO45PDB1
181
IO21RSB0
110
VJTAG
146
IO44NDB1
182
IO20RSB0
111
GDA0/IO60VDB1
147
IO44PDB1
183
IO19RSB0
112
GDA1/IO60UDB1
148
IO43NDB1
184
IO18RSB0
113
GDB0/IO59VDB1
149
GBC2/IO43PDB1
185
IO17RSB0
114
GDB1/IO59UDB1
150
IO42NDB1
186
VCCIB0
115
GDC0/IO58VDB1
151
GBB2/IO42PDB1
187
VCC
116
GDC1/IO58UDB1
152
IO41NDB1
188
IO16RSB0
117
IO57VDB1
153
GBA2/IO41PDB1
189
IO15RSB0
118
IO57UDB1
154
VMV1
190
IO14RSB0
119
IO56NDB1
155
GNDQ
191
IO13RSB0
120
IO56PDB1
156
GND
192
IO12RSB0
121
IO55RSB1
157
NC
193
IO11RSB0
122
GND
158
GBA1/IO40RSB0
194
IO10RSB0
123
VCCIB1
159
GBA0/IO39RSB0
195
GND
124
NC
160
GBB1/IO38RSB0
196
IO09RSB0
125
NC
161
GBB0/IO37RSB0
197
IO08RSB0
126
VCC
162
GND
198
IO07RSB0
127
IO53NDB1
163
GBC1/IO36RSB0
199
IO06RSB0
128
GCC2/IO53PDB1
164
GBC0/IO35RSB0
200
VCCIB0
129
GCB2/IO52PSB1
165
IO34RSB0
201
GAC1/IO05RSB0
130
GND
166
IO33RSB0
202
GAC0/IO04RSB0
131
GCA2/IO51PSB1
167
IO32RSB0
203
GAB1/IO03RSB0
132
GCA1/IO50PDB1
168
IO31RSB0
204
GAB0/IO02RSB0
133
GCA0/IO50NDB1
169
IO30RSB0
205
GAA1/IO01RSB0
134
GCB0/IO49NDB1
170
VCCIB0
206
GAA0/IO00RSB0
135
GCB1/IO49PDB1
171
VCC
207
GNDQ
136
GCC0/IO48NDB1
172
IO29RSB0
208
VMV0
137
GCC1/IO48PDB1
173
IO28RSB0
138
IO47NDB1
174
IO27RSB0
139
IO47PDB1
175
IO26RSB0
140
VCCIB1
176
IO25RSB0
141
GND
177
IO24RSB0
142
VCC
178
GND
143
IO46RSB1
179
IO23RSB0
144
IO45NDB1
180
IO22RSB0
4- 32
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
1
GND
37
IO141PSB3
73
IO112RSB2
2
GAA2/IO155UDB3
38
IO140PDB3
74
IO111RSB2
3
IO155VDB3
39
IO140NDB3
75
IO110RSB2
4
GAB2/IO154UDB3
40
VCCIB3
76
IO109RSB2
5
IO154VDB3
41
GND
77
IO108RSB2
6
GAC2/IO153UDB3
42
IO138PDB3
78
IO107RSB2
7
IO153VDB3
43
IO138NDB3
79
IO106RSB2
8
IO152UDB3
44
GEC1/IO137PDB3
80
IO104RSB2
9
IO152VDB3
45
GEC0/IO137NDB3
81
GND
10
IO151UDB3
46
GEB1/IO136PDB3
82
IO102RSB2
11
IO151VDB3
47
GEB0/IO136NDB3
83
IO101RSB2
12
IO150PDB3
48
GEA1/IO135PDB3
84
IO100RSB2
13
IO150NDB3
49
GEA0/IO135NDB3
85
IO99RSB2
14
IO149PDB3
50
VMV3
86
IO98RSB2
15
IO149NDB3
51
GNDQ
87
IO97RSB2
16
VCC
52
GND
88
VCC
17
GND
53
VMV2
89
VCCIB2
18
VCCIB3
54
NC
90
IO94RSB2
19
IO148PDB3
55
GEA2/IO134RSB2
91
IO92RSB2
20
IO148NDB3
56
GEB2/IO133RSB2
92
IO90RSB2
21
GFC1/IO147PDB3
57
GEC2/IO132RSB2
93
IO88RSB2
22
GFC0/IO147NDB3
58
IO131RSB2
94
IO86RSB2
23
GFB1/IO146PDB3
59
IO130RSB2
95
IO84RSB2
24
GFB0/IO146NDB3
60
IO129RSB2
96
GDC2/IO82RSB2
25
VCOMPLF
61
IO128RSB2
97
GND
26
GFA0/IO145NPB3
62
VCCIB2
98
GDB2/IO81RSB2
27
VCCPLF
63
IO125RSB2
99
GDA2/IO80RSB2
28
GFA1/IO145PPB3
64
IO123RSB2
100
GNDQ
29
GND
65
GND
101
TCK
30
GFA2/IO144PDB3
66
IO121RSB2
102
TDI
31
IO144NDB3
67
IO119RSB2
103
TMS
32
GFB2/IO143PDB3
68
IO117RSB2
104
VMV2
33
IO143NDB3
69
IO115RSB2
105
GND
34
GFC2/IO142PDB3
70
IO113RSB2
106
VPUMP
35
IO142NDB3
71
VCC
107
NC
36
NC
72
VCCIB2
108
TDO
R ev i si o n 1 5
4- 33
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
109
TRST
145
IO64PDB1
181
IO27RSB0
110
VJTAG
146
IO63NDB1
182
IO26RSB0
111
GDA0/IO79VDB1
147
IO63PDB1
183
IO25RSB0
112
GDA1/IO79UDB1
148
IO62NDB1
184
IO24RSB0
113
GDB0/IO78VDB1
149
GBC2/IO62PDB1
185
IO23RSB0
114
GDB1/IO78UDB1
150
IO61NDB1
186
VCCIB0
115
GDC0/IO77VDB1
151
GBB2/IO61PDB1
187
VCC
116
GDC1/IO77UDB1
152
IO60NDB1
188
IO21RSB0
117
IO76VDB1
153
GBA2/IO60PDB1
189
IO20RSB0
118
IO76UDB1
154
VMV1
190
IO19RSB0
119
IO75NDB1
155
GNDQ
191
IO18RSB0
120
IO75PDB1
156
GND
192
IO17RSB0
121
IO74RSB1
157
VMV0
193
IO16RSB0
122
GND
158
GBA1/IO59RSB0
194
IO15RSB0
123
VCCIB1
159
GBA0/IO58RSB0
195
GND
124
NC
160
GBB1/IO57RSB0
196
IO13RSB0
125
NC
161
GBB0/IO56RSB0
197
IO11RSB0
126
VCC
162
GND
198
IO09RSB0
127
IO72NDB1
163
GBC1/IO55RSB0
199
IO07RSB0
128
GCC2/IO72PDB1
164
GBC0/IO54RSB0
200
VCCIB0
129
GCB2/IO71PSB1
165
IO52RSB0
201
GAC1/IO05RSB0
130
GND
166
IO49RSB0
202
GAC0/IO04RSB0
131
GCA2/IO70PSB1
167
IO46RSB0
203
GAB1/IO03RSB0
132
GCA1/IO69PDB1
168
IO43RSB0
204
GAB0/IO02RSB0
133
GCA0/IO69NDB1
169
IO40RSB0
205
GAA1/IO01RSB0
134
GCB0/IO68NDB1
170
VCCIB0
206
GAA0/IO00RSB0
135
GCB1/IO68PDB1
171
VCC
207
GNDQ
136
GCC0/IO67NDB1
172
IO36RSB0
208
VMV0
137
GCC1/IO67PDB1
173
IO35RSB0
138
IO66NDB1
174
IO34RSB0
139
IO66PDB1
175
IO33RSB0
140
VCCIB1
176
IO32RSB0
141
GND
177
IO31RSB0
142
VCC
178
GND
143
IO65RSB1
179
IO29RSB0
144
IO64NDB1
180
IO28RSB0
4- 34
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
1
GND
37
IO152PDB3
73
IO120RSB2
2
GAA2/IO174PDB3
38
IO152NDB3
74
IO119RSB2
3
IO174NDB3
39
IO150PSB3
75
IO118RSB2
4
GAB2/IO173PDB3
40
VCCIB3
76
IO117RSB2
5
IO173NDB3
41
GND
77
IO116RSB2
6
GAC2/IO172PDB3
42
IO147PDB3
78
IO115RSB2
7
IO172NDB3
43
IO147NDB3
79
IO114RSB2
8
IO171PDB3
44
GEC1/IO146PDB3
80
IO112RSB2
9
IO171NDB3
45
GEC0/IO146NDB3
81
GND
10
IO170PDB3
46
GEB1/IO145PDB3
82
IO111RSB2
11
IO170NDB3
47
GEB0/IO145NDB3
83
IO110RSB2
12
IO169PDB3
48
GEA1/IO144PDB3
84
IO109RSB2
13
IO169NDB3
49
GEA0/IO144NDB3
85
IO108RSB2
14
IO168PDB3
50
VMV3
86
IO107RSB2
15
IO168NDB3
51
GNDQ
87
IO106RSB2
16
VCC
52
GND
88
VCC
17
GND
53
VMV2
89
VCCIB2
18
VCCIB3
54
GEA2/IO143RSB2
90
IO104RSB2
19
IO166PDB3
55
GEB2/IO142RSB2
91
IO102RSB2
20
IO166NDB3
56
GEC2/IO141RSB2
92
IO100RSB2
21
GFC1/IO164PDB3
57
IO140RSB2
93
IO98RSB2
22
GFC0/IO164NDB3
58
IO139RSB2
94
IO96RSB2
23
GFB1/IO163PDB3
59
IO138RSB2
95
IO92RSB2
24
GFB0/IO163NDB3
60
IO137RSB2
96
GDC2/IO91RSB2
25
VCOMPLF
61
IO136RSB2
97
GND
26
GFA0/IO162NPB3
62
VCCIB2
98
GDB2/IO90RSB2
27
VCCPLF
63
IO135RSB2
99
GDA2/IO89RSB2
28
GFA1/IO162PPB3
64
IO133RSB2
100
GNDQ
29
GND
65
GND
101
TCK
30
GFA2/IO161PDB3
66
IO131RSB2
102
TDI
31
IO161NDB3
67
IO129RSB2
103
TMS
32
GFB2/IO160PDB3
68
IO127RSB2
104
VMV2
33
IO160NDB3
69
IO125RSB2
105
GND
34
GFC2/IO159PDB3
70
IO123RSB2
106
VPUMP
35
IO159NDB3
71
VCC
107
GNDQ
36
VCC
72
VCCIB2
108
TDO
R ev i si o n 1 5
4- 35
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
109
TRST
145
IO64PDB1
181
IO27RSB0
110
VJTAG
146
IO63NDB1
182
IO26RSB0
111
GDA0/IO88NDB1
147
IO63PDB1
183
IO25RSB0
112
GDA1/IO88PDB1
148
IO62NDB1
184
IO24RSB0
113
GDB0/IO87NDB1
149
GBC2/IO62PDB1
185
IO23RSB0
114
GDB1/IO87PDB1
150
IO61NDB1
186
VCCIB0
115
GDC0/IO86NDB1
151
GBB2/IO61PDB1
187
VCC
116
GDC1/IO86PDB1
152
IO60NDB1
188
IO20RSB0
117
IO84NDB1
153
GBA2/IO60PDB1
189
IO19RSB0
118
IO84PDB1
154
VMV1
190
IO18RSB0
119
IO82NDB1
155
GNDQ
191
IO17RSB0
120
IO82PDB1
156
GND
192
IO16RSB0
121
IO81PSB1
157
VMV0
193
IO14RSB0
122
GND
158
GBA1/IO59RSB0
194
IO12RSB0
123
VCCIB1
159
GBA0/IO58RSB0
195
GND
124
IO77NDB1
160
GBB1/IO57RSB0
196
IO10RSB0
125
IO77PDB1
161
GBB0/IO56RSB0
197
IO09RSB0
126
NC
162
GND
198
IO08RSB0
127
IO74NDB1
163
GBC1/IO55RSB0
199
IO07RSB0
128
GCC2/IO74PDB1
164
GBC0/IO54RSB0
200
VCCIB0
129
GCB2/IO73PSB1
165
IO52RSB0
201
GAC1/IO05RSB0
130
GND
166
IO50RSB0
202
GAC0/IO04RSB0
131
GCA2/IO72PSB1
167
IO48RSB0
203
GAB1/IO03RSB0
132
GCA1/IO71PDB1
168
IO46RSB0
204
GAB0/IO02RSB0
133
GCA0/IO71NDB1
169
IO44RSB0
205
GAA1/IO01RSB0
134
GCB0/IO70NDB1
170
VCCIB0
206
GAA0/IO00RSB0
135
GCB1/IO70PDB1
171
VCC
207
GNDQ
136
GCC0/IO69NDB1
172
IO36RSB0
208
VMV0
137
GCC1/IO69PDB1
173
IO35RSB0
138
IO67NDB1
174
IO34RSB0
139
IO67PDB1
175
IO33RSB0
140
VCCIB1
176
IO32RSB0
141
GND
177
IO31RSB0
142
VCC
178
GND
143
IO65PSB1
179
IO29RSB0
144
IO64NDB1
180
IO28RSB0
4- 36
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
1
GND
37
IO199PDB3
73
IO162RSB2
2
GAA2/IO225PDB3
38
IO199NDB3
74
IO160RSB2
3
IO225NDB3
39
IO197PSB3
75
IO158RSB2
4
GAB2/IO224PDB3
40
VCCIB3
76
IO156RSB2
5
IO224NDB3
41
GND
77
IO154RSB2
6
GAC2/IO223PDB3
42
IO191PDB3
78
IO152RSB2
7
IO223NDB3
43
IO191NDB3
79
IO150RSB2
8
IO222PDB3
44
GEC1/IO190PDB3
80
IO148RSB2
9
IO222NDB3
45
GEC0/IO190NDB3
81
GND
10
IO220PDB3
46
GEB1/IO189PDB3
82
IO143RSB2
11
IO220NDB3
47
GEB0/IO189NDB3
83
IO141RSB2
12
IO218PDB3
48
GEA1/IO188PDB3
84
IO139RSB2
13
IO218NDB3
49
GEA0/IO188NDB3
85
IO137RSB2
14
IO216PDB3
50
VMV3
86
IO135RSB2
15
IO216NDB3
51
GNDQ
87
IO133RSB2
16
VCC
52
GND
88
VCC
17
GND
53
VMV2
89
VCCIB2
18
VCCIB3
54
GEA2/IO187RSB2
90
IO128RSB2
19
IO212PDB3
55
GEB2/IO186RSB2
91
IO126RSB2
20
IO212NDB3
56
GEC2/IO185RSB2
92
IO124RSB2
21
GFC1/IO209PDB3
57
IO184RSB2
93
IO122RSB2
22
GFC0/IO209NDB3
58
IO183RSB2
94
IO120RSB2
23
GFB1/IO208PDB3
59
IO182RSB2
95
IO118RSB2
24
GFB0/IO208NDB3
60
IO181RSB2
96
GDC2/IO116RSB2
25
VCOMPLF
61
IO180RSB2
97
GND
26
GFA0/IO207NPB3
62
VCCIB2
98
GDB2/IO115RSB2
27
VCCPLF
63
IO178RSB2
99
GDA2/IO114RSB2
28
GFA1/IO207PPB3
64
IO176RSB2
100
GNDQ
29
GND
65
GND
101
TCK
30
GFA2/IO206PDB3
66
IO174RSB2
102
TDI
31
IO206NDB3
67
IO172RSB2
103
TMS
32
GFB2/IO205PDB3
68
IO170RSB2
104
VMV2
33
IO205NDB3
69
IO168RSB2
105
GND
34
GFC2/IO204PDB3
70
IO166RSB2
106
VPUMP
35
IO204NDB3
71
VCC
107
GNDQ
36
VCC
72
VCCIB2
108
TDO
R ev i si o n 1 5
4- 37
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
109
TRST
145
IO84PDB1
181
IO33RSB0
110
VJTAG
146
IO82NDB1
182
IO31RSB0
111
GDA0/IO113NDB1
147
IO82PDB1
183
IO29RSB0
112
GDA1/IO113PDB1
148
IO80NDB1
184
IO27RSB0
113
GDB0/IO112NDB1
149
GBC2/IO80PDB1
185
IO25RSB0
114
GDB1/IO112PDB1
150
IO79NDB1
186
VCCIB0
115
GDC0/IO111NDB1
151
GBB2/IO79PDB1
187
VCC
116
GDC1/IO111PDB1
152
IO78NDB1
188
IO22RSB0
117
IO109NDB1
153
GBA2/IO78PDB1
189
IO20RSB0
118
IO109PDB1
154
VMV1
190
IO18RSB0
119
IO106NDB1
155
GNDQ
191
IO16RSB0
120
IO106PDB1
156
GND
192
IO15RSB0
121
IO104PSB1
157
VMV0
193
IO14RSB0
122
GND
158
GBA1/IO77RSB0
194
IO13RSB0
123
VCCIB1
159
GBA0/IO76RSB0
195
GND
124
IO99NDB1
160
GBB1/IO75RSB0
196
IO12RSB0
125
IO99PDB1
161
GBB0/IO74RSB0
197
IO11RSB0
126
NC
162
GND
198
IO10RSB0
127
IO96NDB1
163
GBC1/IO73RSB0
199
IO09RSB0
128
GCC2/IO96PDB1
164
GBC0/IO72RSB0
200
VCCIB0
129
GCB2/IO95PSB1
165
IO70RSB0
201
GAC1/IO05RSB0
130
GND
166
IO67RSB0
202
GAC0/IO04RSB0
131
GCA2/IO94PSB1
167
IO63RSB0
203
GAB1/IO03RSB0
132
GCA1/IO93PDB1
168
IO60RSB0
204
GAB0/IO02RSB0
133
GCA0/IO93NDB1
169
IO57RSB0
205
GAA1/IO01RSB0
134
GCB0/IO92NDB1
170
VCCIB0
206
GAA0/IO00RSB0
135
GCB1/IO92PDB1
171
VCC
207
GNDQ
136
GCC0/IO91NDB1
172
IO54RSB0
208
VMV0
137
GCC1/IO91PDB1
173
IO51RSB0
138
IO88NDB1
174
IO48RSB0
139
IO88PDB1
175
IO45RSB0
140
VCCIB1
176
IO42RSB0
141
GND
177
IO40RSB0
142
VCC
178
GND
143
IO86PSB1
179
IO38RSB0
144
IO84NDB1
180
IO35RSB0
4- 38
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG144 – Bottom View
A1 Ball Pad Corner
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
R ev i si o n 1 5
4- 39
Package Pin Assignments
FG144
FG144
FG144
Pin Number
A3P060 Function
Pin Number
A3P060 Function
Pin Number
A3P060 Function
A1
GNDQ
D1
IO91RSB1
G1
GFA1/IO84RSB1
A2
VMV0
D2
IO92RSB1
G2
GND
A3
GAB0/IO04RSB0
D3
IO93RSB1
G3
VCCPLF
A4
GAB1/IO05RSB0
D4
GAA2/IO51RSB1
G4
GFA0/IO85RSB1
A5
IO08RSB0
D5
GAC0/IO06RSB0
G5
GND
A6
GND
D6
GAC1/IO07RSB0
G6
GND
A7
IO11RSB0
D7
GBC0/IO19RSB0
G7
GND
A8
VCC
D8
GBC1/IO20RSB0
G8
GDC1/IO45RSB0
A9
IO16RSB0
D9
GBB2/IO27RSB0
G9
IO32RSB0
A10
GBA0/IO23RSB0
D10
IO18RSB0
G10
GCC2/IO43RSB0
A11
GBA1/IO24RSB0
D11
IO28RSB0
G11
IO31RSB0
A12
GNDQ
D12
GCB1/IO37RSB0
G12
GCB2/IO42RSB0
B1
GAB2/IO53RSB1
E1
VCC
H1
VCC
B2
GND
E2
GFC0/IO88RSB1
H2
GFB2/IO82RSB1
B3
GAA0/IO02RSB0
E3
GFC1/IO89RSB1
H3
GFC2/IO81RSB1
B4
GAA1/IO03RSB0
E4
VCCIB1
H4
GEC1/IO77RSB1
B5
IO00RSB0
E5
IO52RSB1
H5
VCC
B6
IO10RSB0
E6
VCCIB0
H6
IO34RSB0
B7
IO12RSB0
E7
VCCIB0
H7
IO44RSB0
B8
IO14RSB0
E8
GCC1/IO35RSB0
H8
GDB2/IO55RSB1
B9
GBB0/IO21RSB0
E9
VCCIB0
H9
GDC0/IO46RSB0
B10
GBB1/IO22RSB0
E10
VCC
H10
VCCIB0
B11
GND
E11
GCA0/IO40RSB0
H11
IO33RSB0
B12
VMV0
E12
IO30RSB0
H12
VCC
C1
IO95RSB1
F1
GFB0/IO86RSB1
J1
GEB1/IO75RSB1
C2
GFA2/IO83RSB1
F2
VCOMPLF
J2
IO78RSB1
C3
GAC2/IO94RSB1
F3
GFB1/IO87RSB1
J3
VCCIB1
C4
VCC
F4
IO90RSB1
J4
GEC0/IO76RSB1
C5
IO01RSB0
F5
GND
J5
IO79RSB1
C6
IO09RSB0
F6
GND
J6
IO80RSB1
C7
IO13RSB0
F7
GND
J7
VCC
C8
IO15RSB0
F8
GCC0/IO36RSB0
J8
TCK
C9
IO17RSB0
F9
GCB0/IO38RSB0
J9
GDA2/IO54RSB1
C10
GBA2/IO25RSB0
F10
GND
J10
TDO
C11
IO26RSB0
F11
GCA1/IO39RSB0
J11
GDA1/IO49RSB0
C12
GBC2/IO29RSB0
F12
GCA2/IO41RSB0
J12
GDB1/IO47RSB0
4- 40
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG144
Pin Number
A3P060 Function
K1
GEB0/IO74RSB1
K2
GEA1/IO73RSB1
K3
GEA0/IO72RSB1
K4
GEA2/IO71RSB1
K5
IO65RSB1
K6
IO64RSB1
K7
GND
K8
IO57RSB1
K9
GDC2/IO56RSB1
K10
GND
K11
GDA0/IO50RSB0
K12
GDB0/IO48RSB0
L1
GND
L2
VMV1
L3
GEB2/IO70RSB1
L4
IO67RSB1
L5
VCCIB1
L6
IO62RSB1
L7
IO59RSB1
L8
IO58RSB1
L9
TMS
L10
VJTAG
L11
VMV1
L12
TRST
M1
GNDQ
M2
GEC2/IO69RSB1
M3
IO68RSB1
M4
IO66RSB1
M5
IO63RSB1
M6
IO61RSB1
M7
IO60RSB1
M8
NC
M9
TDI
M10
VCCIB1
M11
VPUMP
M12
GNDQ
R ev i si o n 1 5
4- 41
Package Pin Assignments
FG144
FG144
FG144
Pin Number
A3P125 Function
Pin Number
A3P125 Function
Pin Number
A3P125 Function
A1
GNDQ
D1
IO128RSB1
G1
GFA1/IO121RSB1
A2
VMV0
D2
IO129RSB1
G2
GND
A3
GAB0/IO02RSB0
D3
IO130RSB1
G3
VCCPLF
A4
GAB1/IO03RSB0
D4
GAA2/IO67RSB1
G4
GFA0/IO122RSB1
A5
IO11RSB0
D5
GAC0/IO04RSB0
G5
GND
A6
GND
D6
GAC1/IO05RSB0
G6
GND
A7
IO18RSB0
D7
GBC0/IO35RSB0
G7
GND
A8
VCC
D8
GBC1/IO36RSB0
G8
GDC1/IO61RSB0
A9
IO25RSB0
D9
GBB2/IO43RSB0
G9
IO48RSB0
A10
GBA0/IO39RSB0
D10
IO28RSB0
G10
GCC2/IO59RSB0
A11
GBA1/IO40RSB0
D11
IO44RSB0
G11
IO47RSB0
A12
GNDQ
D12
GCB1/IO53RSB0
G12
GCB2/IO58RSB0
B1
GAB2/IO69RSB1
E1
VCC
H1
VCC
B2
GND
E2
GFC0/IO125RSB1
H2
GFB2/IO119RSB1
B3
GAA0/IO00RSB0
E3
GFC1/IO126RSB1
H3
GFC2/IO118RSB1
B4
GAA1/IO01RSB0
E4
VCCIB1
H4
GEC1/IO112RSB1
B5
IO08RSB0
E5
IO68RSB1
H5
VCC
B6
IO14RSB0
E6
VCCIB0
H6
IO50RSB0
B7
IO19RSB0
E7
VCCIB0
H7
IO60RSB0
B8
IO22RSB0
E8
GCC1/IO51RSB0
H8
GDB2/IO71RSB1
B9
GBB0/IO37RSB0
E9
VCCIB0
H9
GDC0/IO62RSB0
B10
GBB1/IO38RSB0
E10
VCC
H10
VCCIB0
B11
GND
E11
GCA0/IO56RSB0
H11
IO49RSB0
B12
VMV0
E12
IO46RSB0
H12
VCC
C1
IO132RSB1
F1
GFB0/IO123RSB1
J1
GEB1/IO110RSB1
C2
GFA2/IO120RSB1
F2
VCOMPLF
J2
IO115RSB1
C3
GAC2/IO131RSB1
F3
GFB1/IO124RSB1
J3
VCCIB1
C4
VCC
F4
IO127RSB1
J4
GEC0/IO111RSB1
C5
IO10RSB0
F5
GND
J5
IO116RSB1
C6
IO12RSB0
F6
GND
J6
IO117RSB1
C7
IO21RSB0
F7
GND
J7
VCC
C8
IO24RSB0
F8
GCC0/IO52RSB0
J8
TCK
C9
IO27RSB0
F9
GCB0/IO54RSB0
J9
GDA2/IO70RSB1
C10
GBA2/IO41RSB0
F10
GND
J10
TDO
C11
IO42RSB0
F11
GCA1/IO55RSB0
J11
GDA1/IO65RSB0
C12
GBC2/IO45RSB0
F12
GCA2/IO57RSB0
J12
GDB1/IO63RSB0
4- 42
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG144
Pin Number
A3P125 Function
K1
GEB0/IO109RSB1
K2
GEA1/IO108RSB1
K3
GEA0/IO107RSB1
K4
GEA2/IO106RSB1
K5
IO100RSB1
K6
IO98RSB1
K7
GND
K8
IO73RSB1
K9
GDC2/IO72RSB1
K10
GND
K11
GDA0/IO66RSB0
K12
GDB0/IO64RSB0
L1
GND
L2
VMV1
L3
GEB2/IO105RSB1
L4
IO102RSB1
L5
VCCIB1
L6
IO95RSB1
L7
IO85RSB1
L8
IO74RSB1
L9
TMS
L10
VJTAG
L11
VMV1
L12
TRST
M1
GNDQ
M2
GEC2/IO104RSB1
M3
IO103RSB1
M4
IO101RSB1
M5
IO97RSB1
M6
IO94RSB1
M7
IO86RSB1
M8
IO75RSB1
M9
TDI
M10
VCCIB1
M11
VPUMP
M12
GNDQ
R ev i si o n 1 5
4- 43
Package Pin Assignments
FG144
FG144
FG144
Pin Number
A3P250 Function
Pin Number
A3P250 Function
Pin Number
A3P250 Function
A1
GNDQ
D1
IO112NDB3
G1
GFA1/IO108PPB3
A2
VMV0
D2
IO112PDB3
G2
GND
A3
GAB0/IO02RSB0
D3
IO116VDB3
G3
VCCPLF
A4
GAB1/IO03RSB0
D4
GAA2/IO118UPB3
G4
GFA0/IO108NPB3
A5
IO16RSB0
D5
GAC0/IO04RSB0
G5
GND
A6
GND
D6
GAC1/IO05RSB0
G6
GND
A7
IO29RSB0
D7
GBC0/IO35RSB0
G7
GND
A8
VCC
D8
GBC1/IO36RSB0
G8
GDC1/IO58UPB1
A9
IO33RSB0
D9
GBB2/IO42PDB1
G9
IO53NDB1
A10
GBA0/IO39RSB0
D10
IO42NDB1
G10
GCC2/IO53PDB1
A11
GBA1/IO40RSB0
D11
IO43NPB1
G11
IO52NDB1
A12
GNDQ
D12
GCB1/IO49PPB1
G12
GCB2/IO52PDB1
B1
GAB2/IO117UDB3
E1
VCC
H1
VCC
B2
GND
E2
GFC0/IO110NDB3
H2
GFB2/IO106PDB3
B3
GAA0/IO00RSB0
E3
GFC1/IO110PDB3
H3
GFC2/IO105PSB3
B4
GAA1/IO01RSB0
E4
VCCIB3
H4
GEC1/IO100PDB3
B5
IO14RSB0
E5
IO118VPB3
H5
VCC
B6
IO19RSB0
E6
VCCIB0
H6
IO79RSB2
B7
IO22RSB0
E7
VCCIB0
H7
IO65RSB2
B8
IO30RSB0
E8
GCC1/IO48PDB1
H8
GDB2/IO62RSB2
B9
GBB0/IO37RSB0
E9
VCCIB1
H9
GDC0/IO58VPB1
B10
GBB1/IO38RSB0
E10
VCC
H10
VCCIB1
B11
GND
E11
GCA0/IO50NDB1
H11
IO54PSB1
B12
VMV1
E12
IO51NDB1
H12
VCC
C1
IO117VDB3
F1
GFB0/IO109NPB3
J1
GEB1/IO99PDB3
C2
GFA2/IO107PPB3
F2
VCOMPLF
J2
IO106NDB3
C3
GAC2/IO116UDB3
F3
GFB1/IO109PPB3
J3
VCCIB3
C4
VCC
F4
IO107NPB3
J4
GEC0/IO100NDB3
C5
IO12RSB0
F5
GND
J5
IO88RSB2
C6
IO17RSB0
F6
GND
J6
IO81RSB2
C7
IO24RSB0
F7
GND
J7
VCC
C8
IO31RSB0
F8
GCC0/IO48NDB1
J8
TCK
C9
IO34RSB0
F9
GCB0/IO49NPB1
J9
GDA2/IO61RSB2
C10
GBA2/IO41PDB1
F10
GND
J10
TDO
C11
IO41NDB1
F11
GCA1/IO50PDB1
J11
GDA1/IO60UDB1
C12
GBC2/IO43PPB1
F12
GCA2/IO51PDB1
J12
GDB1/IO59UDB1
4- 44
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG144
Pin Number
A3P250 Function
K1
GEB0/IO99NDB3
K2
GEA1/IO98PDB3
K3
GEA0/IO98NDB3
K4
GEA2/IO97RSB2
K5
IO90RSB2
K6
IO84RSB2
K7
GND
K8
IO66RSB2
K9
GDC2/IO63RSB2
K10
GND
K11
GDA0/IO60VDB1
K12
GDB0/IO59VDB1
L1
GND
L2
VMV3
L3
GEB2/IO96RSB2
L4
IO91RSB2
L5
VCCIB2
L6
IO82RSB2
L7
IO80RSB2
L8
IO72RSB2
L9
TMS
L10
VJTAG
L11
VMV2
L12
TRST
M1
GNDQ
M2
GEC2/IO95RSB2
M3
IO92RSB2
M4
IO89RSB2
M5
IO87RSB2
M6
IO85RSB2
M7
IO78RSB2
M8
IO76RSB2
M9
TDI
M10
VCCIB2
M11
VPUMP
M12
GNDQ
R ev i si o n 1 5
4- 45
Package Pin Assignments
FG144
FG144
FG144
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
A1
GNDQ
D1
IO149NDB3
G1
GFA1/IO145PPB3
A2
VMV0
D2
IO149PDB3
G2
GND
A3
GAB0/IO02RSB0
D3
IO153VDB3
G3
VCCPLF
A4
GAB1/IO03RSB0
D4
GAA2/IO155UPB3
G4
GFA0/IO145NPB3
A5
IO16RSB0
D5
GAC0/IO04RSB0
G5
GND
A6
GND
D6
GAC1/IO05RSB0
G6
GND
A7
IO30RSB0
D7
GBC0/IO54RSB0
G7
GND
A8
VCC
D8
GBC1/IO55RSB0
G8
GDC1/IO77UPB1
A9
IO34RSB0
D9
GBB2/IO61PDB1
G9
IO72NDB1
A10
GBA0/IO58RSB0
D10
IO61NDB1
G10
GCC2/IO72PDB1
A11
GBA1/IO59RSB0
D11
IO62NPB1
G11
IO71NDB1
A12
GNDQ
D12
GCB1/IO68PPB1
G12
GCB2/IO71PDB1
B1
GAB2/IO154UDB3
E1
VCC
H1
VCC
B2
GND
E2
GFC0/IO147NDB3
H2
GFB2/IO143PDB3
B3
GAA0/IO00RSB0
E3
GFC1/IO147PDB3
H3
GFC2/IO142PSB3
B4
GAA1/IO01RSB0
E4
VCCIB3
H4
GEC1/IO137PDB3
B5
IO14RSB0
E5
IO155VPB3
H5
VCC
B6
IO19RSB0
E6
VCCIB0
H6
IO75PDB1
B7
IO23RSB0
E7
VCCIB0
H7
IO75NDB1
B8
IO31RSB0
E8
GCC1/IO67PDB1
H8
GDB2/IO81RSB2
B9
GBB0/IO56RSB0
E9
VCCIB1
H9
GDC0/IO77VPB1
B10
GBB1/IO57RSB0
E10
VCC
H10
VCCIB1
B11
GND
E11
GCA0/IO69NDB1
H11
IO73PSB1
B12
VMV1
E12
IO70NDB1
H12
VCC
C1
IO154VDB3
F1
GFB0/IO146NPB3
J1
GEB1/IO136PDB3
C2
GFA2/IO144PPB3
F2
VCOMPLF
J2
IO143NDB3
C3
GAC2/IO153UDB3
F3
GFB1/IO146PPB3
J3
VCCIB3
C4
VCC
F4
IO144NPB3
J4
GEC0/IO137NDB3
C5
IO12RSB0
F5
GND
J5
IO125RSB2
C6
IO17RSB0
F6
GND
J6
IO116RSB2
C7
IO25RSB0
F7
GND
J7
VCC
C8
IO32RSB0
F8
GCC0/IO67NDB1
J8
TCK
C9
IO53RSB0
F9
GCB0/IO68NPB1
J9
GDA2/IO80RSB2
C10
GBA2/IO60PDB1
F10
GND
J10
TDO
C11
IO60NDB1
F11
GCA1/IO69PDB1
J11
GDA1/IO79UDB1
C12
GBC2/IO62PPB1
F12
GCA2/IO70PDB1
J12
GDB1/IO78UDB1
4- 46
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG144
Pin Number
A3P400 Function
K1
GEB0/IO136NDB3
K2
GEA1/IO135PDB3
K3
GEA0/IO135NDB3
K4
GEA2/IO134RSB2
K5
IO127RSB2
K6
IO121RSB2
K7
GND
K8
IO104RSB2
K9
GDC2/IO82RSB2
K10
GND
K11
GDA0/IO79VDB1
K12
GDB0/IO78VDB1
L1
GND
L2
VMV3
L3
GEB2/IO133RSB2
L4
IO128RSB2
L5
VCCIB2
L6
IO119RSB2
L7
IO114RSB2
L8
IO110RSB2
L9
TMS
L10
VJTAG
L11
VMV2
L12
TRST
M1
GNDQ
M2
GEC2/IO132RSB2
M3
IO129RSB2
M4
IO126RSB2
M5
IO124RSB2
M6
IO122RSB2
M7
IO117RSB2
M8
IO115RSB2
M9
TDI
M10
VCCIB2
M11
VPUMP
M12
GNDQ
R ev i si o n 1 5
4- 47
Package Pin Assignments
FG144
FG144
FG144
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
A1
GNDQ
D1
IO169PDB3
G1
GFA1/IO162PPB3
A2
VMV0
D2
IO169NDB3
G2
GND
A3
GAB0/IO02RSB0
D3
IO172NDB3
G3
VCCPLF
A4
GAB1/IO03RSB0
D4
GAA2/IO174PPB3
G4
GFA0/IO162NPB3
A5
IO10RSB0
D5
GAC0/IO04RSB0
G5
GND
A6
GND
D6
GAC1/IO05RSB0
G6
GND
A7
IO34RSB0
D7
GBC0/IO54RSB0
G7
GND
A8
VCC
D8
GBC1/IO55RSB0
G8
GDC1/IO86PPB1
A9
IO50RSB0
D9
GBB2/IO61PDB1
G9
IO74NDB1
A10
GBA0/IO58RSB0
D10
IO61NDB1
G10
GCC2/IO74PDB1
A11
GBA1/IO59RSB0
D11
IO62NPB1
G11
IO73NDB1
A12
GNDQ
D12
GCB1/IO70PPB1
G12
GCB2/IO73PDB1
B1
GAB2/IO173PDB3
E1
VCC
H1
VCC
B2
GND
E2
GFC0/IO164NDB3
H2
GFB2/IO160PDB3
B3
GAA0/IO00RSB0
E3
GFC1/IO164PDB3
H3
GFC2/IO159PSB3
B4
GAA1/IO01RSB0
E4
VCCIB3
H4
GEC1/IO146PDB3
B5
IO13RSB0
E5
IO174NPB3
H5
VCC
B6
IO19RSB0
E6
VCCIB0
H6
IO80PDB1
B7
IO31RSB0
E7
VCCIB0
H7
IO80NDB1
B8
IO39RSB0
E8
GCC1/IO69PDB1
H8
GDB2/IO90RSB2
B9
GBB0/IO56RSB0
E9
VCCIB1
H9
GDC0/IO86NPB1
B10
GBB1/IO57RSB0
E10
VCC
H10
VCCIB1
B11
GND
E11
GCA0/IO71NDB1
H11
IO84PSB1
B12
VMV1
E12
IO72NDB1
H12
VCC
C1
IO173NDB3
F1
GFB0/IO163NPB3
J1
GEB1/IO145PDB3
C2
GFA2/IO161PPB3
F2
VCOMPLF
J2
IO160NDB3
C3
GAC2/IO172PDB3
F3
GFB1/IO163PPB3
J3
VCCIB3
C4
VCC
F4
IO161NPB3
J4
GEC0/IO146NDB3
C5
IO16RSB0
F5
GND
J5
IO129RSB2
C6
IO25RSB0
F6
GND
J6
IO131RSB2
C7
IO28RSB0
F7
GND
J7
VCC
C8
IO42RSB0
F8
GCC0/IO69NDB1
J8
TCK
C9
IO45RSB0
F9
GCB0/IO70NPB1
J9
GDA2/IO89RSB2
C10
GBA2/IO60PDB1
F10
GND
J10
TDO
C11
IO60NDB1
F11
GCA1/IO71PDB1
J11
GDA1/IO88PDB1
C12
GBC2/IO62PPB1
F12
GCA2/IO72PDB1
J12
GDB1/IO87PDB1
4- 48
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG144
Pin Number
A3P600 Function
K1
GEB0/IO145NDB3
K2
GEA1/IO144PDB3
K3
GEA0/IO144NDB3
K4
GEA2/IO143RSB2
K5
IO119RSB2
K6
IO111RSB2
K7
GND
K8
IO94RSB2
K9
GDC2/IO91RSB2
K10
GND
K11
GDA0/IO88NDB1
K12
GDB0/IO87NDB1
L1
GND
L2
VMV3
L3
GEB2/IO142RSB2
L4
IO136RSB2
L5
VCCIB2
L6
IO115RSB2
L7
IO103RSB2
L8
IO97RSB2
L9
TMS
L10
VJTAG
L11
VMV2
L12
TRST
M1
GNDQ
M2
GEC2/IO141RSB2
M3
IO138RSB2
M4
IO123RSB2
M5
IO126RSB2
M6
IO134RSB2
M7
IO108RSB2
M8
IO99RSB2
M9
TDI
M10
VCCIB2
M11
VPUMP
M12
GNDQ
R ev i si o n 1 5
4- 49
Package Pin Assignments
FG144
FG144
FG144
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
A1
GNDQ
D1
IO213PDB3
G1
GFA1/IO207PPB3
A2
VMV0
D2
IO213NDB3
G2
GND
A3
GAB0/IO02RSB0
D3
IO223NDB3
G3
VCCPLF
A4
GAB1/IO03RSB0
D4
GAA2/IO225PPB3
G4
GFA0/IO207NPB3
A5
IO10RSB0
D5
GAC0/IO04RSB0
G5
GND
A6
GND
D6
GAC1/IO05RSB0
G6
GND
A7
IO44RSB0
D7
GBC0/IO72RSB0
G7
GND
A8
VCC
D8
GBC1/IO73RSB0
G8
GDC1/IO111PPB1
A9
IO69RSB0
D9
GBB2/IO79PDB1
G9
IO96NDB1
A10
GBA0/IO76RSB0
D10
IO79NDB1
G10
GCC2/IO96PDB1
A11
GBA1/IO77RSB0
D11
IO80NPB1
G11
IO95NDB1
A12
GNDQ
D12
GCB1/IO92PPB1
G12
GCB2/IO95PDB1
B1
GAB2/IO224PDB3
E1
VCC
H1
VCC
B2
GND
E2
GFC0/IO209NDB3
H2
GFB2/IO205PDB3
B3
GAA0/IO00RSB0
E3
GFC1/IO209PDB3
H3
GFC2/IO204PSB3
B4
GAA1/IO01RSB0
E4
VCCIB3
H4
GEC1/IO190PDB3
B5
IO13RSB0
E5
IO225NPB3
H5
VCC
B6
IO26RSB0
E6
VCCIB0
H6
IO105PDB1
B7
IO35RSB0
E7
VCCIB0
H7
IO105NDB1
B8
IO60RSB0
E8
GCC1/IO91PDB1
H8
GDB2/IO115RSB2
B9
GBB0/IO74RSB0
E9
VCCIB1
H9
GDC0/IO111NPB1
B10
GBB1/IO75RSB0
E10
VCC
H10
VCCIB1
B11
GND
E11
GCA0/IO93NDB1
H11
IO101PSB1
B12
VMV1
E12
IO94NDB1
H12
VCC
C1
IO224NDB3
F1
GFB0/IO208NPB3
J1
GEB1/IO189PDB3
C2
GFA2/IO206PPB3
F2
VCOMPLF
J2
IO205NDB3
C3
GAC2/IO223PDB3
F3
GFB1/IO208PPB3
J3
VCCIB3
C4
VCC
F4
IO206NPB3
J4
GEC0/IO190NDB3
C5
IO16RSB0
F5
GND
J5
IO160RSB2
C6
IO29RSB0
F6
GND
J6
IO157RSB2
C7
IO32RSB0
F7
GND
J7
VCC
C8
IO63RSB0
F8
GCC0/IO91NDB1
J8
TCK
C9
IO66RSB0
F9
GCB0/IO92NPB1
J9
GDA2/IO114RSB2
C10
GBA2/IO78PDB1
F10
GND
J10
TDO
C11
IO78NDB1
F11
GCA1/IO93PDB1
J11
GDA1/IO113PDB1
C12
GBC2/IO80PPB1
F12
GCA2/IO94PDB1
J12
GDB1/IO112PDB1
4- 50
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG144
Pin Number
A3P1000 Function
K1
GEB0/IO189NDB3
K2
GEA1/IO188PDB3
K3
GEA0/IO188NDB3
K4
GEA2/IO187RSB2
K5
IO169RSB2
K6
IO152RSB2
K7
GND
K8
IO117RSB2
K9
GDC2/IO116RSB2
K10
GND
K11
GDA0/IO113NDB1
K12
GDB0/IO112NDB1
L1
GND
L2
VMV3
L3
GEB2/IO186RSB2
L4
IO172RSB2
L5
VCCIB2
L6
IO153RSB2
L7
IO144RSB2
L8
IO140RSB2
L9
TMS
L10
VJTAG
L11
VMV2
L12
TRST
M1
GNDQ
M2
GEC2/IO185RSB2
M3
IO173RSB2
M4
IO168RSB2
M5
IO161RSB2
M6
IO156RSB2
M7
IO145RSB2
M8
IO141RSB2
M9
TDI
M10
VCCIB2
M11
VPUMP
M12
GNDQ
R ev i si o n 1 5
4- 51
Package Pin Assignments
FG256 – Bottom View
A1 Ball Pad Corner
16 15 14 13 12 11 10 9
8
7
6 5 4
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4- 52
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number
A3P250 Function
Pin Number
A3P250 Function
Pin Number
A3P250 Function
A1
GND
C5
GAC0/IO04RSB0
E9
IO24RSB0
A2
GAA0/IO00RSB0
C6
GAC1/IO05RSB0
E10
VCCIB0
A3
GAA1/IO01RSB0
C7
IO13RSB0
E11
VCCIB0
A4
GAB0/IO02RSB0
C8
IO17RSB0
E12
VMV1
A5
IO07RSB0
C9
IO22RSB0
E13
GBC2/IO43PDB1
A6
IO10RSB0
C10
IO27RSB0
E14
IO46RSB1
A7
IO11RSB0
C11
IO31RSB0
E15
NC
A8
IO15RSB0
C12
GBC0/IO35RSB0
E16
IO45PDB1
A9
IO20RSB0
C13
IO34RSB0
F1
IO113NDB3
A10
IO25RSB0
C14
NC
F2
IO112PPB3
A11
IO29RSB0
C15
IO42NPB1
F3
NC
A12
IO33RSB0
C16
IO44PDB1
F4
IO115VDB3
A13
GBB1/IO38RSB0
D1
IO114VDB3
F5
VCCIB3
A14
GBA0/IO39RSB0
D2
IO114UDB3
F6
GND
A15
GBA1/IO40RSB0
D3
GAC2/IO116UDB3
F7
VCC
A16
GND
D4
NC
F8
VCC
B1
GAB2/IO117UDB3
D5
GNDQ
F9
VCC
B2
GAA2/IO118UDB3
D6
IO08RSB0
F10
VCC
B3
NC
D7
IO14RSB0
F11
GND
B4
GAB1/IO03RSB0
D8
IO18RSB0
F12
VCCIB1
B5
IO06RSB0
D9
IO23RSB0
F13
IO43NDB1
B6
IO09RSB0
D10
IO28RSB0
F14
NC
B7
IO12RSB0
D11
IO32RSB0
F15
IO47PPB1
B8
IO16RSB0
D12
GNDQ
F16
IO45NDB1
B9
IO21RSB0
D13
NC
G1
IO111NDB3
B10
IO26RSB0
D14
GBB2/IO42PPB1
G2
IO111PDB3
B11
IO30RSB0
D15
NC
G3
IO112NPB3
B12
GBC1/IO36RSB0
D16
IO44NDB1
G4
GFC1/IO110PPB3
B13
GBB0/IO37RSB0
E1
IO113PDB3
G5
VCCIB3
B14
NC
E2
NC
G6
VCC
B15
GBA2/IO41PDB1
E3
IO116VDB3
G7
GND
B16
IO41NDB1
E4
IO115UDB3
G8
GND
C1
IO117VDB3
E5
VMV0
G9
GND
C2
IO118VDB3
E6
VCCIB0
G10
GND
C3
NC
E7
VCCIB0
G11
VCC
C4
NC
E8
IO19RSB0
G12
VCCIB1
R ev i si o n 1 5
4- 53
Package Pin Assignments
FG256
FG256
FG256
Pin Number
A3P250 Function
Pin Number
A3P250 Function
Pin Number
A3P250 Function
G13
GCC1/IO48PPB1
K1
GFC2/IO105PDB3
M5
VMV3
G14
IO47NPB1
K2
IO107NPB3
M6
VCCIB2
G15
IO54PDB1
K3
IO104PPB3
M7
VCCIB2
G16
IO54NDB1
K4
NC
M8
NC
H1
GFB0/IO109NPB3
K5
VCCIB3
M9
IO74RSB2
H2
GFA0/IO108NDB3
K6
VCC
M10
VCCIB2
H3
GFB1/IO109PPB3
K7
GND
M11
VCCIB2
H4
VCOMPLF
K8
GND
M12
VMV2
H5
GFC0/IO110NPB3
K9
GND
M13
NC
H6
VCC
K10
GND
M14
GDB1/IO59UPB1
H7
GND
K11
VCC
M15
GDC1/IO58UDB1
H8
GND
K12
VCCIB1
M16
IO56NDB1
H9
GND
K13
IO52NPB1
N1
IO103NDB3
H10
GND
K14
IO55RSB1
N2
IO101PPB3
H11
VCC
K15
IO53NPB1
N3
GEC1/IO100PPB3
H12
GCC0/IO48NPB1
K16
IO51NDB1
N4
NC
H13
GCB1/IO49PPB1
L1
IO105NDB3
N5
GNDQ
H14
GCA0/IO50NPB1
L2
IO104NPB3
N6
GEA2/IO97RSB2
H15
NC
L3
NC
N7
IO86RSB2
H16
GCB0/IO49NPB1
L4
IO102RSB3
N8
IO82RSB2
J1
GFA2/IO107PPB3
L5
VCCIB3
N9
IO75RSB2
J2
GFA1/IO108PDB3
L6
GND
N10
IO69RSB2
J3
VCCPLF
L7
VCC
N11
IO64RSB2
J4
IO106NDB3
L8
VCC
N12
GNDQ
J5
GFB2/IO106PDB3
L9
VCC
N13
NC
J6
VCC
L10
VCC
N14
VJTAG
J7
GND
L11
GND
N15
GDC0/IO58VDB1
J8
GND
L12
VCCIB1
N16
GDA1/IO60UDB1
J9
GND
L13
GDB0/IO59VPB1
P1
GEB1/IO99PDB3
J10
GND
L14
IO57VDB1
P2
GEB0/IO99NDB3
J11
VCC
L15
IO57UDB1
P3
NC
J12
GCB2/IO52PPB1
L16
IO56PDB1
P4
NC
J13
GCA1/IO50PPB1
M1
IO103PDB3
P5
IO92RSB2
J14
GCC2/IO53PPB1
M2
NC
P6
IO89RSB2
J15
NC
M3
IO101NPB3
P7
IO85RSB2
J16
GCA2/IO51PDB1
M4
GEC0/IO100NPB3
P8
IO81RSB2
4- 54
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG256
FG256
Pin Number
A3P250 Function
Pin Number
A3P250 Function
P9
IO76RSB2
T13
IO67RSB2
P10
IO71RSB2
T14
GDA2/IO61RSB2
P11
IO66RSB2
T15
TMS
P12
NC
T16
GND
P13
TCK
P14
VPUMP
P15
TRST
P16
GDA0/IO60VDB1
R1
GEA1/IO98PDB3
R2
GEA0/IO98NDB3
R3
NC
R4
GEC2/IO95RSB2
R5
IO91RSB2
R6
IO88RSB2
R7
IO84RSB2
R8
IO80RSB2
R9
IO77RSB2
R10
IO72RSB2
R11
IO68RSB2
R12
IO65RSB2
R13
GDB2/IO62RSB2
R14
TDI
R15
NC
R16
TDO
T1
GND
T2
IO94RSB2
T3
GEB2/IO96RSB2
T4
IO93RSB2
T5
IO90RSB2
T6
IO87RSB2
T7
IO83RSB2
T8
IO79RSB2
T9
IO78RSB2
T10
IO73RSB2
T11
IO70RSB2
T12
GDC2/IO63RSB2
R ev i si o n 1 5
4- 55
Package Pin Assignments
FG256
FG256
FG256
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
A1
GND
C5
GAC0/IO04RSB0
E9
IO31RSB0
A2
GAA0/IO00RSB0
C6
GAC1/IO05RSB0
E10
VCCIB0
A3
GAA1/IO01RSB0
C7
IO20RSB0
E11
VCCIB0
A4
GAB0/IO02RSB0
C8
IO24RSB0
E12
VMV1
A5
IO16RSB0
C9
IO33RSB0
E13
GBC2/IO62PDB1
A6
IO17RSB0
C10
IO39RSB0
E14
IO65RSB1
A7
IO22RSB0
C11
IO45RSB0
E15
IO52RSB0
A8
IO28RSB0
C12
GBC0/IO54RSB0
E16
IO66PDB1
A9
IO34RSB0
C13
IO48RSB0
F1
IO150NDB3
A10
IO37RSB0
C14
VMV0
F2
IO149NPB3
A11
IO41RSB0
C15
IO61NPB1
F3
IO09RSB0
A12
IO43RSB0
C16
IO63PDB1
F4
IO152UDB3
A13
GBB1/IO57RSB0
D1
IO151VDB3
F5
VCCIB3
A14
GBA0/IO58RSB0
D2
IO151UDB3
F6
GND
A15
GBA1/IO59RSB0
D3
GAC2/IO153UDB3
F7
VCC
A16
GND
D4
IO06RSB0
F8
VCC
B1
GAB2/IO154UDB3
D5
GNDQ
F9
VCC
B2
GAA2/IO155UDB3
D6
IO10RSB0
F10
VCC
B3
IO12RSB0
D7
IO19RSB0
F11
GND
B4
GAB1/IO03RSB0
D8
IO26RSB0
F12
VCCIB1
B5
IO13RSB0
D9
IO30RSB0
F13
IO62NDB1
B6
IO14RSB0
D10
IO40RSB0
F14
IO49RSB0
B7
IO21RSB0
D11
IO46RSB0
F15
IO64PPB1
B8
IO27RSB0
D12
GNDQ
F16
IO66NDB1
B9
IO32RSB0
D13
IO47RSB0
G1
IO148NDB3
B10
IO38RSB0
D14
GBB2/IO61PPB1
G2
IO148PDB3
B11
IO42RSB0
D15
IO53RSB0
G3
IO149PPB3
B12
GBC1/IO55RSB0
D16
IO63NDB1
G4
GFC1/IO147PPB3
B13
GBB0/IO56RSB0
E1
IO150PDB3
G5
VCCIB3
B14
IO44RSB0
E2
IO08RSB0
G6
VCC
B15
GBA2/IO60PDB1
E3
IO153VDB3
G7
GND
B16
IO60NDB1
E4
IO152VDB3
G8
GND
C1
IO154VDB3
E5
VMV0
G9
GND
C2
IO155VDB3
E6
VCCIB0
G10
GND
C3
IO11RSB0
E7
VCCIB0
G11
VCC
C4
IO07RSB0
E8
IO25RSB0
G12
VCCIB1
4- 56
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
G13
GCC1/IO67PPB1
K1
GFC2/IO142PDB3
M5
VMV3
G14
IO64NPB1
K2
IO144NPB3
M6
VCCIB2
G15
IO73PDB1
K3
IO141PPB3
M7
VCCIB2
G16
IO73NDB1
K4
IO120RSB2
M8
IO108RSB2
H1
GFB0/IO146NPB3
K5
VCCIB3
M9
IO101RSB2
H2
GFA0/IO145NDB3
K6
VCC
M10
VCCIB2
H3
GFB1/IO146PPB3
K7
GND
M11
VCCIB2
H4
VCOMPLF
K8
GND
M12
VMV2
H5
GFC0/IO147NPB3
K9
GND
M13
IO83RSB2
H6
VCC
K10
GND
M14
GDB1/IO78UPB1
H7
GND
K11
VCC
M15
GDC1/IO77UDB1
H8
GND
K12
VCCIB1
M16
IO75NDB1
H9
GND
K13
IO71NPB1
N1
IO140NDB3
H10
GND
K14
IO74RSB1
N2
IO138PPB3
H11
VCC
K15
IO72NPB1
N3
GEC1/IO137PPB3
H12
GCC0/IO67NPB1
K16
IO70NDB1
N4
IO131RSB2
H13
GCB1/IO68PPB1
L1
IO142NDB3
N5
GNDQ
H14
GCA0/IO69NPB1
L2
IO141NPB3
N6
GEA2/IO134RSB2
H15
NC
L3
IO125RSB2
N7
IO117RSB2
H16
GCB0/IO68NPB1
L4
IO139RSB3
N8
IO111RSB2
J1
GFA2/IO144PPB3
L5
VCCIB3
N9
IO99RSB2
J2
GFA1/IO145PDB3
L6
GND
N10
IO94RSB2
J3
VCCPLF
L7
VCC
N11
IO87RSB2
J4
IO143NDB3
L8
VCC
N12
GNDQ
J5
GFB2/IO143PDB3
L9
VCC
N13
IO93RSB2
J6
VCC
L10
VCC
N14
VJTAG
J7
GND
L11
GND
N15
GDC0/IO77VDB1
J8
GND
L12
VCCIB1
N16
GDA1/IO79UDB1
J9
GND
L13
GDB0/IO78VPB1
P1
GEB1/IO136PDB3
J10
GND
L14
IO76VDB1
P2
GEB0/IO136NDB3
J11
VCC
L15
IO76UDB1
P3
VMV2
J12
GCB2/IO71PPB1
L16
IO75PDB1
P4
IO129RSB2
J13
GCA1/IO69PPB1
M1
IO140PDB3
P5
IO128RSB2
J14
GCC2/IO72PPB1
M2
IO130RSB2
P6
IO122RSB2
J15
NC
M3
IO138NPB3
P7
IO115RSB2
J16
GCA2/IO70PDB1
M4
GEC0/IO137NPB3
P8
IO110RSB2
R ev i si o n 1 5
4- 57
Package Pin Assignments
FG256
FG256
Pin Number
A3P400 Function
Pin Number
A3P400 Function
P9
IO98RSB2
T13
IO86RSB2
P10
IO95RSB2
T14
GDA2/IO80RSB2
P11
IO88RSB2
T15
TMS
P12
IO84RSB2
T16
GND
P13
TCK
P14
VPUMP
P15
TRST
P16
GDA0/IO79VDB1
R1
GEA1/IO135PDB3
R2
GEA0/IO135NDB3
R3
IO127RSB2
R4
GEC2/IO132RSB2
R5
IO123RSB2
R6
IO118RSB2
R7
IO112RSB2
R8
IO106RSB2
R9
IO100RSB2
R10
IO96RSB2
R11
IO89RSB2
R12
IO85RSB2
R13
GDB2/IO81RSB2
R14
TDI
R15
NC
R16
TDO
T1
GND
T2
IO126RSB2
T3
GEB2/IO133RSB2
T4
IO124RSB2
T5
IO116RSB2
T6
IO113RSB2
T7
IO107RSB2
T8
IO105RSB2
T9
IO102RSB2
T10
IO97RSB2
T11
IO92RSB2
T12
GDC2/IO82RSB2
4- 58
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
A1
GND
C5
GAC0/IO04RSB0
E9
IO31RSB0
A2
GAA0/IO00RSB0
C6
GAC1/IO05RSB0
E10
VCCIB0
A3
GAA1/IO01RSB0
C7
IO20RSB0
E11
VCCIB0
A4
GAB0/IO02RSB0
C8
IO24RSB0
E12
VMV1
A5
IO11RSB0
C9
IO33RSB0
E13
GBC2/IO62PDB1
A6
IO16RSB0
C10
IO39RSB0
E14
IO67PPB1
A7
IO18RSB0
C11
IO44RSB0
E15
IO64PPB1
A8
IO28RSB0
C12
GBC0/IO54RSB0
E16
IO66PDB1
A9
IO34RSB0
C13
IO51RSB0
F1
IO166NDB3
A10
IO37RSB0
C14
VMV0
F2
IO168NPB3
A11
IO41RSB0
C15
IO61NPB1
F3
IO167PPB3
A12
IO43RSB0
C16
IO63PDB1
F4
IO169PDB3
A13
GBB1/IO57RSB0
D1
IO171NDB3
F5
VCCIB3
A14
GBA0/IO58RSB0
D2
IO171PDB3
F6
GND
A15
GBA1/IO59RSB0
D3
GAC2/IO172PDB3
F7
VCC
A16
GND
D4
IO06RSB0
F8
VCC
B1
GAB2/IO173PDB3
D5
GNDQ
F9
VCC
B2
GAA2/IO174PDB3
D6
IO10RSB0
F10
VCC
B3
GNDQ
D7
IO19RSB0
F11
GND
B4
GAB1/IO03RSB0
D8
IO26RSB0
F12
VCCIB1
B5
IO13RSB0
D9
IO30RSB0
F13
IO62NDB1
B6
IO14RSB0
D10
IO40RSB0
F14
IO64NPB1
B7
IO21RSB0
D11
IO45RSB0
F15
IO65PPB1
B8
IO27RSB0
D12
GNDQ
F16
IO66NDB1
B9
IO32RSB0
D13
IO50RSB0
G1
IO165NDB3
B10
IO38RSB0
D14
GBB2/IO61PPB1
G2
IO165PDB3
B11
IO42RSB0
D15
IO53RSB0
G3
IO168PPB3
B12
GBC1/IO55RSB0
D16
IO63NDB1
G4
GFC1/IO164PPB3
B13
GBB0/IO56RSB0
E1
IO166PDB3
G5
VCCIB3
B14
IO52RSB0
E2
IO167NPB3
G6
VCC
B15
GBA2/IO60PDB1
E3
IO172NDB3
G7
GND
B16
IO60NDB1
E4
IO169NDB3
G8
GND
C1
IO173NDB3
E5
VMV0
G9
GND
C2
IO174NDB3
E6
VCCIB0
G10
GND
C3
VMV3
E7
VCCIB0
G11
VCC
C4
IO07RSB0
E8
IO25RSB0
G12
VCCIB1
R ev i si o n 1 5
4- 59
Package Pin Assignments
FG256
FG256
FG256
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
G13
GCC1/IO69PPB1
K1
GFC2/IO159PDB3
M5
VMV3
G14
IO65NPB1
K2
IO161NPB3
M6
VCCIB2
G15
IO75PDB1
K3
IO156PPB3
M7
VCCIB2
G16
IO75NDB1
K4
IO129RSB2
M8
IO117RSB2
H1
GFB0/IO163NPB3
K5
VCCIB3
M9
IO110RSB2
H2
GFA0/IO162NDB3
K6
VCC
M10
VCCIB2
H3
GFB1/IO163PPB3
K7
GND
M11
VCCIB2
H4
VCOMPLF
K8
GND
M12
VMV2
H5
GFC0/IO164NPB3
K9
GND
M13
IO94RSB2
H6
VCC
K10
GND
M14
GDB1/IO87PPB1
H7
GND
K11
VCC
M15
GDC1/IO86PDB1
H8
GND
K12
VCCIB1
M16
IO84NDB1
H9
GND
K13
IO73NPB1
N1
IO150NDB3
H10
GND
K14
IO80NPB1
N2
IO147PPB3
H11
VCC
K15
IO74NPB1
N3
GEC1/IO146PPB3
H12
GCC0/IO69NPB1
K16
IO72NDB1
N4
IO140RSB2
H13
GCB1/IO70PPB1
L1
IO159NDB3
N5
GNDQ
H14
GCA0/IO71NPB1
L2
IO156NPB3
N6
GEA2/IO143RSB2
H15
IO67NPB1
L3
IO151PPB3
N7
IO126RSB2
H16
GCB0/IO70NPB1
L4
IO158PSB3
N8
IO120RSB2
J1
GFA2/IO161PPB3
L5
VCCIB3
N9
IO108RSB2
J2
GFA1/IO162PDB3
L6
GND
N10
IO103RSB2
J3
VCCPLF
L7
VCC
N11
IO99RSB2
J4
IO160NDB3
L8
VCC
N12
GNDQ
J5
GFB2/IO160PDB3
L9
VCC
N13
IO92RSB2
J6
VCC
L10
VCC
N14
VJTAG
J7
GND
L11
GND
N15
GDC0/IO86NDB1
J8
GND
L12
VCCIB1
N16
GDA1/IO88PDB1
J9
GND
L13
GDB0/IO87NPB1
P1
GEB1/IO145PDB3
J10
GND
L14
IO85NDB1
P2
GEB0/IO145NDB3
J11
VCC
L15
IO85PDB1
P3
VMV2
J12
GCB2/IO73PPB1
L16
IO84PDB1
P4
IO138RSB2
J13
GCA1/IO71PPB1
M1
IO150PDB3
P5
IO136RSB2
J14
GCC2/IO74PPB1
M2
IO151NPB3
P6
IO131RSB2
J15
IO80PPB1
M3
IO147NPB3
P7
IO124RSB2
J16
GCA2/IO72PDB1
M4
GEC0/IO146NPB3
P8
IO119RSB2
4- 60
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG256
FG256
Pin Number
A3P600 Function
Pin Number
A3P600 Function
P9
IO107RSB2
T13
IO93RSB2
P10
IO104RSB2
T14
GDA2/IO89RSB2
P11
IO97RSB2
T15
TMS
P12
VMV1
T16
GND
P13
TCK
P14
VPUMP
P15
TRST
P16
GDA0/IO88NDB1
R1
GEA1/IO144PDB3
R2
GEA0/IO144NDB3
R3
IO139RSB2
R4
GEC2/IO141RSB2
R5
IO132RSB2
R6
IO127RSB2
R7
IO121RSB2
R8
IO114RSB2
R9
IO109RSB2
R10
IO105RSB2
R11
IO98RSB2
R12
IO96RSB2
R13
GDB2/IO90RSB2
R14
TDI
R15
GNDQ
R16
TDO
T1
GND
T2
IO137RSB2
T3
GEB2/IO142RSB2
T4
IO134RSB2
T5
IO125RSB2
T6
IO123RSB2
T7
IO118RSB2
T8
IO115RSB2
T9
IO111RSB2
T10
IO106RSB2
T11
IO102RSB2
T12
GDC2/IO91RSB2
R ev i si o n 1 5
4- 61
Package Pin Assignments
FG256
FG256
FG256
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
A1
GND
C7
IO25RSB0
E13
GBC2/IO80PDB1
A2
GAA0/IO00RSB0
C8
IO36RSB0
E14
IO83PPB1
A3
GAA1/IO01RSB0
C9
IO42RSB0
E15
IO86PPB1
A4
GAB0/IO02RSB0
C10
IO49RSB0
E16
IO87PDB1
A5
IO16RSB0
C11
IO56RSB0
F1
IO217NDB3
A6
IO22RSB0
C12
GBC0/IO72RSB0
F2
IO218NDB3
A7
IO28RSB0
C13
IO62RSB0
F3
IO216PDB3
A8
IO35RSB0
C14
VMV0
F4
IO216NDB3
A9
IO45RSB0
C15
IO78NDB1
F5
VCCIB3
A10
IO50RSB0
C16
IO81NDB1
F6
GND
A11
IO55RSB0
D1
IO222NDB3
F7
VCC
A12
IO61RSB0
D2
IO222PDB3
F8
VCC
A13
GBB1/IO75RSB0
D3
GAC2/IO223PDB3
F9
VCC
A14
GBA0/IO76RSB0
D4
IO223NDB3
F10
VCC
A15
GBA1/IO77RSB0
D5
GNDQ
F11
GND
A16
GND
D6
IO23RSB0
F12
VCCIB1
B1
GAB2/IO224PDB3
D7
IO29RSB0
F13
IO83NPB1
B2
GAA2/IO225PDB3
D8
IO33RSB0
F14
IO86NPB1
B3
GNDQ
D9
IO46RSB0
F15
IO90PPB1
B4
GAB1/IO03RSB0
D10
IO52RSB0
F16
IO87NDB1
B5
IO17RSB0
D11
IO60RSB0
G1
IO210PSB3
B6
IO21RSB0
D12
GNDQ
G2
IO213NDB3
B7
IO27RSB0
D13
IO80NDB1
G3
IO213PDB3
B8
IO34RSB0
D14
GBB2/IO79PDB1
G4
GFC1/IO209PPB3
B9
IO44RSB0
D15
IO79NDB1
G5
VCCIB3
B10
IO51RSB0
D16
IO82NSB1
G6
VCC
B11
IO57RSB0
E1
IO217PDB3
G7
GND
B12
GBC1/IO73RSB0
E2
IO218PDB3
G8
GND
B13
GBB0/IO74RSB0
E3
IO221NDB3
G9
GND
B14
IO71RSB0
E4
IO221PDB3
G10
GND
B15
GBA2/IO78PDB1
E5
VMV0
G11
VCC
B16
IO81PDB1
E6
VCCIB0
G12
VCCIB1
C1
IO224NDB3
E7
VCCIB0
G13
GCC1/IO91PPB1
C2
IO225NDB3
E8
IO38RSB0
G14
IO90NPB1
C3
VMV3
E9
IO47RSB0
G15
IO88PDB1
C4
IO11RSB0
E10
VCCIB0
G16
IO88NDB1
C5
GAC0/IO04RSB0
E11
VCCIB0
H1
GFB0/IO208NPB3
C6
GAC1/IO05RSB0
E12
VMV1
H2
GFA0/IO207NDB3
4- 62
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
H3
GFB1/IO208PPB3
K9
GND
M15
GDC1/IO111PDB1
H4
VCOMPLF
K10
GND
M16
IO107NDB1
H5
GFC0/IO209NPB3
K11
VCC
N1
IO194PSB3
H6
VCC
K12
VCCIB1
N2
IO192PPB3
H7
GND
K13
IO95NPB1
N3
GEC1/IO190PPB3
H8
GND
K14
IO100NPB1
N4
IO192NPB3
H9
GND
K15
IO102NDB1
N5
GNDQ
H10
GND
K16
IO102PDB1
N6
GEA2/IO187RSB2
H11
VCC
L1
IO202NDB3
N7
IO161RSB2
H12
GCC0/IO91NPB1
L2
IO202PDB3
N8
IO155RSB2
H13
GCB1/IO92PPB1
L3
IO196PPB3
N9
IO141RSB2
H14
GCA0/IO93NPB1
L4
IO193PPB3
N10
IO129RSB2
H15
IO96NPB1
L5
VCCIB3
N11
IO124RSB2
H16
GCB0/IO92NPB1
L6
GND
N12
GNDQ
J1
GFA2/IO206PSB3
L7
VCC
N13
IO110PDB1
J2
GFA1/IO207PDB3
L8
VCC
N14
VJTAG
J3
VCCPLF
L9
VCC
N15
GDC0/IO111NDB1
J4
IO205NDB3
L10
VCC
N16
GDA1/IO113PDB1
J5
GFB2/IO205PDB3
L11
GND
P1
GEB1/IO189PDB3
J6
VCC
L12
VCCIB1
P2
GEB0/IO189NDB3
J7
GND
L13
GDB0/IO112NPB1
P3
VMV2
J8
GND
L14
IO106NDB1
P4
IO179RSB2
J9
GND
L15
IO106PDB1
P5
IO171RSB2
J10
GND
L16
IO107PDB1
P6
IO165RSB2
J11
VCC
M1
IO197NSB3
P7
IO159RSB2
J12
GCB2/IO95PPB1
M2
IO196NPB3
P8
IO151RSB2
J13
GCA1/IO93PPB1
M3
IO193NPB3
P9
IO137RSB2
J14
GCC2/IO96PPB1
M4
GEC0/IO190NPB3
P10
IO134RSB2
J15
IO100PPB1
M5
VMV3
P11
IO128RSB2
J16
GCA2/IO94PSB1
M6
VCCIB2
P12
VMV1
K1
GFC2/IO204PDB3
M7
VCCIB2
P13
TCK
K2
IO204NDB3
M8
IO147RSB2
P14
VPUMP
K3
IO203NDB3
M9
IO136RSB2
P15
TRST
K4
IO203PDB3
M10
VCCIB2
P16
GDA0/IO113NDB1
K5
VCCIB3
M11
VCCIB2
R1
GEA1/IO188PDB3
K6
VCC
M12
VMV2
R2
GEA0/IO188NDB3
K7
GND
M13
IO110NDB1
R3
IO184RSB2
K8
GND
M14
GDB1/IO112PPB1
R4
GEC2/IO185RSB2
R ev i si o n 1 5
4- 63
Package Pin Assignments
FG256
Pin Number
A3P1000 Function
R5
IO168RSB2
R6
IO163RSB2
R7
IO157RSB2
R8
IO149RSB2
R9
IO143RSB2
R10
IO138RSB2
R11
IO131RSB2
R12
IO125RSB2
R13
GDB2/IO115RSB2
R14
TDI
R15
GNDQ
R16
TDO
T1
GND
T2
IO183RSB2
T3
GEB2/IO186RSB2
T4
IO172RSB2
T5
IO170RSB2
T6
IO164RSB2
T7
IO158RSB2
T8
IO153RSB2
T9
IO142RSB2
T10
IO135RSB2
T11
IO130RSB2
T12
GDC2/IO116RSB2
T13
IO120RSB2
T14
GDA2/IO114RSB2
T15
TMS
T16
GND
4- 64
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484 – Bottom View
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
R ev i si o n 1 5
4- 65
Package Pin Assignments
FG484
FG484
FG484
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
A1
GND
B15
NC
D7
GAB0/IO02RSB0
A2
GND
B16
NC
D8
IO16RSB0
A3
VCCIB0
B17
NC
D9
IO17RSB0
A4
NC
B18
NC
D10
IO22RSB0
A5
NC
B19
NC
D11
IO28RSB0
A6
IO15RSB0
B20
NC
D12
IO34RSB0
A7
IO18RSB0
B21
VCCIB1
D13
IO37RSB0
A8
NC
B22
GND
D14
IO41RSB0
A9
NC
C1
VCCIB3
D15
IO43RSB0
A10
IO23RSB0
C2
NC
D16
GBB1/IO57RSB0
A11
IO29RSB0
C3
NC
D17
GBA0/IO58RSB0
A12
IO35RSB0
C4
NC
D18
GBA1/IO59RSB0
A13
IO36RSB0
C5
GND
D19
GND
A14
NC
C6
NC
D20
NC
A15
NC
C7
NC
D21
NC
A16
IO50RSB0
C8
VCC
D22
NC
A17
IO51RSB0
C9
VCC
E1
NC
A18
NC
C10
NC
E2
NC
A19
NC
C11
NC
E3
GND
A20
VCCIB0
C12
NC
E4
GAB2/IO154UDB3
A21
GND
C13
NC
E5
GAA2/IO155UDB3
A22
GND
C14
VCC
E6
IO12RSB0
B1
GND
C15
VCC
E7
GAB1/IO03RSB0
B2
VCCIB3
C16
NC
E8
IO13RSB0
B3
NC
C17
NC
E9
IO14RSB0
B4
NC
C18
GND
E10
IO21RSB0
B5
NC
C19
NC
E11
IO27RSB0
B6
NC
C20
NC
E12
IO32RSB0
B7
NC
C21
NC
E13
IO38RSB0
B8
NC
C22
VCCIB1
E14
IO42RSB0
B9
NC
D1
NC
E15
GBC1/IO55RSB0
B10
NC
D2
NC
E16
GBB0/IO56RSB0
B11
NC
D3
NC
E17
IO44RSB0
B12
NC
D4
GND
E18
GBA2/IO60PDB1
B13
NC
D5
GAA0/IO00RSB0
E19
IO60NDB1
B14
NC
D6
GAA1/IO01RSB0
E20
GND
4- 66
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
E21
NC
G13
IO40RSB0
J5
IO149NPB3
E22
NC
G14
IO46RSB0
J6
IO09RSB0
F1
NC
G15
GNDQ
J7
IO152UDB3
F2
NC
G16
IO47RSB0
J8
VCCIB3
F3
NC
G17
GBB2/IO61PPB1
J9
GND
F4
IO154VDB3
G18
IO53RSB0
J10
VCC
F5
IO155VDB3
G19
IO63NDB1
J11
VCC
F6
IO11RSB0
G20
NC
J12
VCC
F7
IO07RSB0
G21
NC
J13
VCC
F8
GAC0/IO04RSB0
G22
NC
J14
GND
F9
GAC1/IO05RSB0
H1
NC
J15
VCCIB1
F10
IO20RSB0
H2
NC
J16
IO62NDB1
F11
IO24RSB0
H3
VCC
J17
IO49RSB0
F12
IO33RSB0
H4
IO150PDB3
J18
IO64PPB1
F13
IO39RSB0
H5
IO08RSB0
J19
IO66NDB1
F14
IO45RSB0
H6
IO153VDB3
J20
NC
F15
GBC0/IO54RSB0
H7
IO152VDB3
J21
NC
F16
IO48RSB0
H8
VMV0
J22
NC
F17
VMV0
H9
VCCIB0
K1
NC
F18
IO61NPB1
H10
VCCIB0
K2
NC
F19
IO63PDB1
H11
IO25RSB0
K3
NC
F20
NC
H12
IO31RSB0
K4
IO148NDB3
F21
NC
H13
VCCIB0
K5
IO148PDB3
F22
NC
H14
VCCIB0
K6
IO149PPB3
G1
NC
H15
VMV1
K7
GFC1/IO147PPB3
G2
NC
H16
GBC2/IO62PDB1
K8
VCCIB3
G3
NC
H17
IO65RSB1
K9
VCC
G4
IO151VDB3
H18
IO52RSB0
K10
GND
G5
IO151UDB3
H19
IO66PDB1
K11
GND
G6
GAC2/IO153UDB3
H20
VCC
K12
GND
G7
IO06RSB0
H21
NC
K13
GND
G8
GNDQ
H22
NC
K14
VCC
G9
IO10RSB0
J1
NC
K15
VCCIB1
G10
IO19RSB0
J2
NC
K16
GCC1/IO67PPB1
G11
IO26RSB0
J3
NC
K17
IO64NPB1
G12
IO30RSB0
J4
IO150NDB3
K18
IO73PDB1
R ev i si o n 1 5
4- 67
Package Pin Assignments
FG484
FG484
FG484
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
K19
IO73NDB1
M11
GND
P3
NC
K20
NC
M12
GND
P4
IO142NDB3
K21
NC
M13
GND
P5
IO141NPB3
K22
NC
M14
VCC
P6
IO125RSB2
L1
NC
M15
GCB2/IO71PPB1
P7
IO139RSB3
L2
NC
M16
GCA1/IO69PPB1
P8
VCCIB3
L3
NC
M17
GCC2/IO72PPB1
P9
GND
L4
GFB0/IO146NPB3
M18
NC
P10
VCC
L5
GFA0/IO145NDB3
M19
GCA2/IO70PDB1
P11
VCC
L6
GFB1/IO146PPB3
M20
NC
P12
VCC
L7
VCOMPLF
M21
NC
P13
VCC
L8
GFC0/IO147NPB3
M22
NC
P14
GND
L9
VCC
N1
NC
P15
VCCIB1
L10
GND
N2
NC
P16
GDB0/IO78VPB1
L11
GND
N3
NC
P17
IO76VDB1
L12
GND
N4
GFC2/IO142PDB3
P18
IO76UDB1
L13
GND
N5
IO144NPB3
P19
IO75PDB1
L14
VCC
N6
IO141PPB3
P20
NC
L15
GCC0/IO67NPB1
N7
IO120RSB2
P21
NC
L16
GCB1/IO68PPB1
N8
VCCIB3
P22
NC
L17
GCA0/IO69NPB1
N9
VCC
R1
NC
L18
NC
N10
GND
R2
NC
L19
GCB0/IO68NPB1
N11
GND
R3
VCC
L20
NC
N12
GND
R4
IO140PDB3
L21
NC
N13
GND
R5
IO130RSB2
L22
NC
N14
VCC
R6
IO138NPB3
M1
NC
N15
VCCIB1
R7
GEC0/IO137NPB3
M2
NC
N16
IO71NPB1
R8
VMV3
M3
NC
N17
IO74RSB1
R9
VCCIB2
M4
GFA2/IO144PPB3
N18
IO72NPB1
R10
VCCIB2
M5
GFA1/IO145PDB3
N19
IO70NDB1
R11
IO108RSB2
M6
VCCPLF
N20
NC
R12
IO101RSB2
M7
IO143NDB3
N21
NC
R13
VCCIB2
M8
GFB2/IO143PDB3
N22
NC
R14
VCCIB2
M9
VCC
P1
NC
R15
VMV2
M10
GND
P2
NC
R16
IO83RSB2
4- 68
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Pin Number
A3P400 Function
R17
GDB1/IO78UPB1
U9
IO122RSB2
W1
NC
R18
GDC1/IO77UDB1
U10
IO115RSB2
W2
NC
R19
IO75NDB1
U11
IO110RSB2
W3
NC
R20
VCC
U12
IO98RSB2
W4
GND
R21
NC
U13
IO95RSB2
W5
IO126RSB2
R22
NC
U14
IO88RSB2
W6
GEB2/IO133RSB2
T1
NC
U15
IO84RSB2
W7
IO124RSB2
T2
NC
U16
TCK
W8
IO116RSB2
T3
NC
U17
VPUMP
W9
IO113RSB2
T4
IO140NDB3
U18
TRST
W10
IO107RSB2
T5
IO138PPB3
U19
GDA0/IO79VDB1
W11
IO105RSB2
T6
GEC1/IO137PPB3
U20
NC
W12
IO102RSB2
T7
IO131RSB2
U21
NC
W13
IO97RSB2
T8
GNDQ
U22
NC
W14
IO92RSB2
T9
GEA2/IO134RSB2
V1
NC
W15
GDC2/IO82RSB2
T10
IO117RSB2
V2
NC
W16
IO86RSB2
T11
IO111RSB2
V3
GND
W17
GDA2/IO80RSB2
T12
IO99RSB2
V4
GEA1/IO135PDB3
W18
TMS
T13
IO94RSB2
V5
GEA0/IO135NDB3
W19
GND
T14
IO87RSB2
V6
IO127RSB2
W20
NC
T15
GNDQ
V7
GEC2/IO132RSB2
W21
NC
T16
IO93RSB2
V8
IO123RSB2
W22
NC
T17
VJTAG
V9
IO118RSB2
Y1
VCCIB3
T18
GDC0/IO77VDB1
V10
IO112RSB2
Y2
NC
T19
GDA1/IO79UDB1
V11
IO106RSB2
Y3
NC
T20
NC
V12
IO100RSB2
Y4
NC
T21
NC
V13
IO96RSB2
Y5
GND
T22
NC
V14
IO89RSB2
Y6
NC
U1
NC
V15
IO85RSB2
Y7
NC
U2
NC
V16
GDB2/IO81RSB2
Y8
VCC
U3
NC
V17
TDI
Y9
VCC
U4
GEB1/IO136PDB3
V18
NC
Y10
NC
U5
GEB0/IO136NDB3
V19
TDO
Y11
NC
U6
VMV2
V20
GND
Y12
NC
U7
IO129RSB2
V21
NC
Y13
NC
U8
IO128RSB2
V22
NC
Y14
VCC
R ev i si o n 1 5
4- 69
Package Pin Assignments
FG484
FG484
Pin Number
A3P400 Function
Pin Number
A3P400 Function
Y15
VCC
AB7
IO119RSB2
Y16
NC
AB8
IO114RSB2
Y17
NC
AB9
IO109RSB2
Y18
GND
AB10
NC
Y19
NC
AB11
NC
Y20
NC
AB12
IO104RSB2
Y21
NC
AB13
IO103RSB2
Y22
VCCIB1
AB14
NC
AA1
GND
AB15
NC
AA2
VCCIB3
AB16
IO91RSB2
AA3
NC
AB17
IO90RSB2
AA4
NC
AB18
NC
AA5
NC
AB19
NC
AA6
NC
AB20
VCCIB2
AA7
NC
AB21
GND
AA8
NC
AB22
GND
AA9
NC
AA10
NC
AA11
NC
AA12
NC
AA13
NC
AA14
NC
AA15
NC
AA16
NC
AA17
NC
AA18
NC
AA19
NC
AA20
NC
AA21
VCCIB1
AA22
GND
AB1
GND
AB2
GND
AB3
VCCIB2
AB4
NC
AB5
NC
AB6
IO121RSB2
4- 70
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
A1
GND
B15
NC
D7
GAB0/IO02RSB0
A2
GND
B16
IO47RSB0
D8
IO11RSB0
A3
VCCIB0
B17
IO49RSB0
D9
IO16RSB0
A4
NC
B18
NC
D10
IO18RSB0
A5
NC
B19
NC
D11
IO28RSB0
A6
IO09RSB0
B20
NC
D12
IO34RSB0
A7
IO15RSB0
B21
VCCIB1
D13
IO37RSB0
A8
NC
B22
GND
D14
IO41RSB0
A9
NC
C1
VCCIB3
D15
IO43RSB0
A10
IO22RSB0
C2
NC
D16
GBB1/IO57RSB0
A11
IO23RSB0
C3
NC
D17
GBA0/IO58RSB0
A12
IO29RSB0
C4
NC
D18
GBA1/IO59RSB0
A13
IO35RSB0
C5
GND
D19
GND
A14
NC
C6
NC
D20
NC
A15
NC
C7
NC
D21
NC
A16
IO46RSB0
C8
VCC
D22
NC
A17
IO48RSB0
C9
VCC
E1
NC
A18
NC
C10
NC
E2
NC
A19
NC
C11
NC
E3
GND
A20
VCCIB0
C12
NC
E4
GAB2/IO173PDB3
A21
GND
C13
NC
E5
GAA2/IO174PDB3
A22
GND
C14
VCC
E6
GNDQ
B1
GND
C15
VCC
E7
GAB1/IO03RSB0
B2
VCCIB3
C16
NC
E8
IO13RSB0
B3
NC
C17
NC
E9
IO14RSB0
B4
NC
C18
GND
E10
IO21RSB0
B5
NC
C19
NC
E11
IO27RSB0
B6
IO08RSB0
C20
NC
E12
IO32RSB0
B7
IO12RSB0
C21
NC
E13
IO38RSB0
B8
NC
C22
VCCIB1
E14
IO42RSB0
B9
NC
D1
NC
E15
GBC1/IO55RSB0
B10
IO17RSB0
D2
NC
E16
GBB0/IO56RSB0
B11
NC
D3
NC
E17
IO52RSB0
B12
NC
D4
GND
E18
GBA2/IO60PDB1
B13
IO36RSB0
D5
GAA0/IO00RSB0
E19
IO60NDB1
B14
NC
D6
GAA1/IO01RSB0
E20
GND
R ev i si o n 1 5
4- 71
Package Pin Assignments
FG484
FG484
FG484
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
E21
NC
G13
IO40RSB0
J5
IO168NPB3
E22
NC
G14
IO45RSB0
J6
IO167PPB3
F1
NC
G15
GNDQ
J7
IO169PDB3
F2
NC
G16
IO50RSB0
J8
VCCIB3
F3
NC
G17
GBB2/IO61PPB1
J9
GND
F4
IO173NDB3
G18
IO53RSB0
J10
VCC
F5
IO174NDB3
G19
IO63NDB1
J11
VCC
F6
VMV3
G20
NC
J12
VCC
F7
IO07RSB0
G21
NC
J13
VCC
F8
GAC0/IO04RSB0
G22
NC
J14
GND
F9
GAC1/IO05RSB0
H1
NC
J15
VCCIB1
F10
IO20RSB0
H2
NC
J16
IO62NDB1
F11
IO24RSB0
H3
VCC
J17
IO64NPB1
F12
IO33RSB0
H4
IO166PDB3
J18
IO65PPB1
F13
IO39RSB0
H5
IO167NPB3
J19
IO66NDB1
F14
IO44RSB0
H6
IO172NDB3
J20
NC
F15
GBC0/IO54RSB0
H7
IO169NDB3
J21
IO68PDB1
F16
IO51RSB0
H8
VMV0
J22
IO68NDB1
F17
VMV0
H9
VCCIB0
K1
IO157PDB3
F18
IO61NPB1
H10
VCCIB0
K2
IO157NDB3
F19
IO63PDB1
H11
IO25RSB0
K3
NC
F20
NC
H12
IO31RSB0
K4
IO165NDB3
F21
NC
H13
VCCIB0
K5
IO165PDB3
F22
NC
H14
VCCIB0
K6
IO168PPB3
G1
IO170NDB3
H15
VMV1
K7
GFC1/IO164PPB3
G2
IO170PDB3
H16
GBC2/IO62PDB1
K8
VCCIB3
G3
NC
H17
IO67PPB1
K9
VCC
G4
IO171NDB3
H18
IO64PPB1
K10
GND
G5
IO171PDB3
H19
IO66PDB1
K11
GND
G6
GAC2/IO172PDB3
H20
VCC
K12
GND
G7
IO06RSB0
H21
NC
K13
GND
G8
GNDQ
H22
NC
K14
VCC
G9
IO10RSB0
J1
NC
K15
VCCIB1
G10
IO19RSB0
J2
NC
K16
GCC1/IO69PPB1
G11
IO26RSB0
J3
NC
K17
IO65NPB1
G12
IO30RSB0
J4
IO166NDB3
K18
IO75PDB1
4- 72
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
K19
IO75NDB1
M11
GND
P3
IO153NDB3
K20
NC
M12
GND
P4
IO159NDB3
K21
IO76NDB1
M13
GND
P5
IO156NPB3
K22
IO76PDB1
M14
VCC
P6
IO151PPB3
L1
NC
M15
GCB2/IO73PPB1
P7
IO158PPB3
L2
IO155PDB3
M16
GCA1/IO71PPB1
P8
VCCIB3
L3
NC
M17
GCC2/IO74PPB1
P9
GND
L4
GFB0/IO163NPB3
M18
IO80PPB1
P10
VCC
L5
GFA0/IO162NDB3
M19
GCA2/IO72PDB1
P11
VCC
L6
GFB1/IO163PPB3
M20
IO79PPB1
P12
VCC
L7
VCOMPLF
M21
IO78PPB1
P13
VCC
L8
GFC0/IO164NPB3
M22
NC
P14
GND
L9
VCC
N1
IO154NDB3
P15
VCCIB1
L10
GND
N2
IO154PDB3
P16
GDB0/IO87NPB1
L11
GND
N3
NC
P17
IO85NDB1
L12
GND
N4
GFC2/IO159PDB3
P18
IO85PDB1
L13
GND
N5
IO161NPB3
P19
IO84PDB1
L14
VCC
N6
IO156PPB3
P20
NC
L15
GCC0/IO69NPB1
N7
IO129RSB2
P21
IO81PDB1
L16
GCB1/IO70PPB1
N8
VCCIB3
P22
NC
L17
GCA0/IO71NPB1
N9
VCC
R1
NC
L18
IO67NPB1
N10
GND
R2
NC
L19
GCB0/IO70NPB1
N11
GND
R3
VCC
L20
IO77PDB1
N12
GND
R4
IO150PDB3
L21
IO77NDB1
N13
GND
R5
IO151NPB3
L22
IO78NPB1
N14
VCC
R6
IO147NPB3
M1
NC
N15
VCCIB1
R7
GEC0/IO146NPB3
M2
IO155NDB3
N16
IO73NPB1
R8
VMV3
M3
IO158NPB3
N17
IO80NPB1
R9
VCCIB2
M4
GFA2/IO161PPB3
N18
IO74NPB1
R10
VCCIB2
M5
GFA1/IO162PDB3
N19
IO72NDB1
R11
IO117RSB2
M6
VCCPLF
N20
NC
R12
IO110RSB2
M7
IO160NDB3
N21
IO79NPB1
R13
VCCIB2
M8
GFB2/IO160PDB3
N22
NC
R14
VCCIB2
M9
VCC
P1
NC
R15
VMV2
M10
GND
P2
IO153PDB3
R16
IO94RSB2
R ev i si o n 1 5
4- 73
Package Pin Assignments
FG484
FG484
FG484
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Pin Number
A3P600 Function
R17
GDB1/IO87PPB1
U9
IO131RSB2
W1
NC
R18
GDC1/IO86PDB1
U10
IO124RSB2
W2
IO148PDB3
R19
IO84NDB1
U11
IO119RSB2
W3
NC
R20
VCC
U12
IO107RSB2
W4
GND
R21
IO81NDB1
U13
IO104RSB2
W5
IO137RSB2
R22
IO82PDB1
U14
IO97RSB2
W6
GEB2/IO142RSB2
T1
IO152PDB3
U15
VMV1
W7
IO134RSB2
T2
IO152NDB3
U16
TCK
W8
IO125RSB2
T3
NC
U17
VPUMP
W9
IO123RSB2
T4
IO150NDB3
U18
TRST
W10
IO118RSB2
T5
IO147PPB3
U19
GDA0/IO88NDB1
W11
IO115RSB2
T6
GEC1/IO146PPB3
U20
NC
W12
IO111RSB2
T7
IO140RSB2
U21
IO83NDB1
W13
IO106RSB2
T8
GNDQ
U22
NC
W14
IO102RSB2
T9
GEA2/IO143RSB2
V1
NC
W15
GDC2/IO91RSB2
T10
IO126RSB2
V2
NC
W16
IO93RSB2
T11
IO120RSB2
V3
GND
W17
GDA2/IO89RSB2
T12
IO108RSB2
V4
GEA1/IO144PDB3
W18
TMS
T13
IO103RSB2
V5
GEA0/IO144NDB3
W19
GND
T14
IO99RSB2
V6
IO139RSB2
W20
NC
T15
GNDQ
V7
GEC2/IO141RSB2
W21
NC
T16
IO92RSB2
V8
IO132RSB2
W22
NC
T17
VJTAG
V9
IO127RSB2
Y1
VCCIB3
T18
GDC0/IO86NDB1
V10
IO121RSB2
Y2
IO148NDB3
T19
GDA1/IO88PDB1
V11
IO114RSB2
Y3
NC
T20
NC
V12
IO109RSB2
Y4
NC
T21
IO83PDB1
V13
IO105RSB2
Y5
GND
T22
IO82NDB1
V14
IO98RSB2
Y6
NC
U1
IO149PDB3
V15
IO96RSB2
Y7
NC
U2
IO149NDB3
V16
GDB2/IO90RSB2
Y8
VCC
U3
NC
V17
TDI
Y9
VCC
U4
GEB1/IO145PDB3
V18
GNDQ
Y10
NC
U5
GEB0/IO145NDB3
V19
TDO
Y11
NC
U6
VMV2
V20
GND
Y12
NC
U7
IO138RSB2
V21
NC
Y13
NC
U8
IO136RSB2
V22
NC
Y14
VCC
4- 74
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484
FG484
Pin Number
A3P600 Function
Pin Number
A3P600 Function
Y15
VCC
AB7
IO128RSB2
Y16
NC
AB8
IO122RSB2
Y17
NC
AB9
IO116RSB2
Y18
GND
AB10
NC
Y19
NC
AB11
NC
Y20
NC
AB12
IO113RSB2
Y21
NC
AB13
IO112RSB2
Y22
VCCIB1
AB14
NC
AA1
GND
AB15
NC
AA2
VCCIB3
AB16
IO100RSB2
AA3
NC
AB17
IO95RSB2
AA4
NC
AB18
NC
AA5
NC
AB19
NC
AA6
IO135RSB2
AB20
VCCIB2
AA7
IO133RSB2
AB21
GND
AA8
NC
AB22
GND
AA9
NC
AA10
NC
AA11
NC
AA12
NC
AA13
NC
AA14
NC
AA15
NC
AA16
IO101RSB2
AA17
NC
AA18
NC
AA19
NC
AA20
NC
AA21
VCCIB1
AA22
GND
AB1
GND
AB2
GND
AB3
VCCIB2
AB4
NC
AB5
NC
AB6
IO130RSB2
R ev i si o n 1 5
4- 75
Package Pin Assignments
FG484
FG484
FG484
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
A1
GND
B15
IO63RSB0
D7
GAB0/IO02RSB0
A2
GND
B16
IO66RSB0
D8
IO16RSB0
A3
VCCIB0
B17
IO68RSB0
D9
IO22RSB0
A4
IO07RSB0
B18
IO70RSB0
D10
IO28RSB0
A5
IO09RSB0
B19
NC
D11
IO35RSB0
A6
IO13RSB0
B20
NC
D12
IO45RSB0
A7
IO18RSB0
B21
VCCIB1
D13
IO50RSB0
A8
IO20RSB0
B22
GND
D14
IO55RSB0
A9
IO26RSB0
C1
VCCIB3
D15
IO61RSB0
A10
IO32RSB0
C2
IO220PDB3
D16
GBB1/IO75RSB0
A11
IO40RSB0
C3
NC
D17
GBA0/IO76RSB0
A12
IO41RSB0
C4
NC
D18
GBA1/IO77RSB0
A13
IO53RSB0
C5
GND
D19
GND
A14
IO59RSB0
C6
IO10RSB0
D20
NC
A15
IO64RSB0
C7
IO14RSB0
D21
NC
A16
IO65RSB0
C8
VCC
D22
NC
A17
IO67RSB0
C9
VCC
E1
IO219NDB3
A18
IO69RSB0
C10
IO30RSB0
E2
NC
A19
NC
C11
IO37RSB0
E3
GND
A20
VCCIB0
C12
IO43RSB0
E4
GAB2/IO224PDB3
A21
GND
C13
NC
E5
GAA2/IO225PDB3
A22
GND
C14
VCC
E6
GNDQ
B1
GND
C15
VCC
E7
GAB1/IO03RSB0
B2
VCCIB3
C16
NC
E8
IO17RSB0
B3
NC
C17
NC
E9
IO21RSB0
B4
IO06RSB0
C18
GND
E10
IO27RSB0
B5
IO08RSB0
C19
NC
E11
IO34RSB0
B6
IO12RSB0
C20
NC
E12
IO44RSB0
B7
IO15RSB0
C21
NC
E13
IO51RSB0
B8
IO19RSB0
C22
VCCIB1
E14
IO57RSB0
B9
IO24RSB0
D1
IO219PDB3
E15
GBC1/IO73RSB0
B10
IO31RSB0
D2
IO220NDB3
E16
GBB0/IO74RSB0
B11
IO39RSB0
D3
NC
E17
IO71RSB0
B12
IO48RSB0
D4
GND
E18
GBA2/IO78PDB1
B13
IO54RSB0
D5
GAA0/IO00RSB0
E19
IO81PDB1
B14
IO58RSB0
D6
GAA1/IO01RSB0
E20
GND
4- 76
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
E21
NC
G13
IO52RSB0
J5
IO218NDB3
E22
IO84PDB1
G14
IO60RSB0
J6
IO216PDB3
F1
NC
G15
GNDQ
J7
IO216NDB3
F2
IO215PDB3
G16
IO80NDB1
J8
VCCIB3
F3
IO215NDB3
G17
GBB2/IO79PDB1
J9
GND
F4
IO224NDB3
G18
IO79NDB1
J10
VCC
F5
IO225NDB3
G19
IO82NPB1
J11
VCC
F6
VMV3
G20
IO85PDB1
J12
VCC
F7
IO11RSB0
G21
IO85NDB1
J13
VCC
F8
GAC0/IO04RSB0
G22
NC
J14
GND
F9
GAC1/IO05RSB0
H1
NC
J15
VCCIB1
F10
IO25RSB0
H2
NC
J16
IO83NPB1
F11
IO36RSB0
H3
VCC
J17
IO86NPB1
F12
IO42RSB0
H4
IO217PDB3
J18
IO90PPB1
F13
IO49RSB0
H5
IO218PDB3
J19
IO87NDB1
F14
IO56RSB0
H6
IO221NDB3
J20
NC
F15
GBC0/IO72RSB0
H7
IO221PDB3
J21
IO89PDB1
F16
IO62RSB0
H8
VMV0
J22
IO89NDB1
F17
VMV0
H9
VCCIB0
K1
IO211PDB3
F18
IO78NDB1
H10
VCCIB0
K2
IO211NDB3
F19
IO81NDB1
H11
IO38RSB0
K3
NC
F20
IO82PPB1
H12
IO47RSB0
K4
IO210PPB3
F21
NC
H13
VCCIB0
K5
IO213NDB3
F22
IO84NDB1
H14
VCCIB0
K6
IO213PDB3
G1
IO214NDB3
H15
VMV1
K7
GFC1/IO209PPB3
G2
IO214PDB3
H16
GBC2/IO80PDB1
K8
VCCIB3
G3
NC
H17
IO83PPB1
K9
VCC
G4
IO222NDB3
H18
IO86PPB1
K10
GND
G5
IO222PDB3
H19
IO87PDB1
K11
GND
G6
GAC2/IO223PDB3
H20
VCC
K12
GND
G7
IO223NDB3
H21
NC
K13
GND
G8
GNDQ
H22
NC
K14
VCC
G9
IO23RSB0
J1
IO212NDB3
K15
VCCIB1
G10
IO29RSB0
J2
IO212PDB3
K16
GCC1/IO91PPB1
G11
IO33RSB0
J3
NC
K17
IO90NPB1
G12
IO46RSB0
J4
IO217NDB3
K18
IO88PDB1
R ev i si o n 1 5
4- 77
Package Pin Assignments
FG484
FG484
FG484
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
K19
IO88NDB1
M11
GND
P3
IO199NDB3
K20
IO94NPB1
M12
GND
P4
IO202NDB3
K21
IO98NDB1
M13
GND
P5
IO202PDB3
K22
IO98PDB1
M14
VCC
P6
IO196PPB3
L1
NC
M15
GCB2/IO95PPB1
P7
IO193PPB3
L2
IO200PDB3
M16
GCA1/IO93PPB1
P8
VCCIB3
L3
IO210NPB3
M17
GCC2/IO96PPB1
P9
GND
L4
GFB0/IO208NPB3
M18
IO100PPB1
P10
VCC
L5
GFA0/IO207NDB3
M19
GCA2/IO94PPB1
P11
VCC
L6
GFB1/IO208PPB3
M20
IO101PPB1
P12
VCC
L7
VCOMPLF
M21
IO99PPB1
P13
VCC
L8
GFC0/IO209NPB3
M22
NC
P14
GND
L9
VCC
N1
IO201NDB3
P15
VCCIB1
L10
GND
N2
IO201PDB3
P16
GDB0/IO112NPB1
L11
GND
N3
NC
P17
IO106NDB1
L12
GND
N4
GFC2/IO204PDB3
P18
IO106PDB1
L13
GND
N5
IO204NDB3
P19
IO107PDB1
L14
VCC
N6
IO203NDB3
P20
NC
L15
GCC0/IO91NPB1
N7
IO203PDB3
P21
IO104PDB1
L16
GCB1/IO92PPB1
N8
VCCIB3
P22
IO103NDB1
L17
GCA0/IO93NPB1
N9
VCC
R1
NC
L18
IO96NPB1
N10
GND
R2
IO197PPB3
L19
GCB0/IO92NPB1
N11
GND
R3
VCC
L20
IO97PDB1
N12
GND
R4
IO197NPB3
L21
IO97NDB1
N13
GND
R5
IO196NPB3
L22
IO99NPB1
N14
VCC
R6
IO193NPB3
M1
NC
N15
VCCIB1
R7
GEC0/IO190NPB3
M2
IO200NDB3
N16
IO95NPB1
R8
VMV3
M3
IO206NDB3
N17
IO100NPB1
R9
VCCIB2
M4
GFA2/IO206PDB3
N18
IO102NDB1
R10
VCCIB2
M5
GFA1/IO207PDB3
N19
IO102PDB1
R11
IO147RSB2
M6
VCCPLF
N20
NC
R12
IO136RSB2
M7
IO205NDB3
N21
IO101NPB1
R13
VCCIB2
M8
GFB2/IO205PDB3
N22
IO103PDB1
R14
VCCIB2
M9
VCC
P1
NC
R15
VMV2
M10
GND
P2
IO199PDB3
R16
IO110NDB1
4- 78
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
R17
GDB1/IO112PPB1
U9
IO165RSB2
W1
NC
R18
GDC1/IO111PDB1
U10
IO159RSB2
W2
IO191PDB3
R19
IO107NDB1
U11
IO151RSB2
W3
NC
R20
VCC
U12
IO137RSB2
W4
GND
R21
IO104NDB1
U13
IO134RSB2
W5
IO183RSB2
R22
IO105PDB1
U14
IO128RSB2
W6
GEB2/IO186RSB2
T1
IO198PDB3
U15
VMV1
W7
IO172RSB2
T2
IO198NDB3
U16
TCK
W8
IO170RSB2
T3
NC
U17
VPUMP
W9
IO164RSB2
T4
IO194PPB3
U18
TRST
W10
IO158RSB2
T5
IO192PPB3
U19
GDA0/IO113NDB1
W11
IO153RSB2
T6
GEC1/IO190PPB3
U20
NC
W12
IO142RSB2
T7
IO192NPB3
U21
IO108NDB1
W13
IO135RSB2
T8
GNDQ
U22
IO109PDB1
W14
IO130RSB2
T9
GEA2/IO187RSB2
V1
NC
W15
GDC2/IO116RSB2
T10
IO161RSB2
V2
NC
W16
IO120RSB2
T11
IO155RSB2
V3
GND
W17
GDA2/IO114RSB2
T12
IO141RSB2
V4
GEA1/IO188PDB3
W18
TMS
T13
IO129RSB2
V5
GEA0/IO188NDB3
W19
GND
T14
IO124RSB2
V6
IO184RSB2
W20
NC
T15
GNDQ
V7
GEC2/IO185RSB2
W21
NC
T16
IO110PDB1
V8
IO168RSB2
W22
NC
T17
VJTAG
V9
IO163RSB2
Y1
VCCIB3
T18
GDC0/IO111NDB1
V10
IO157RSB2
Y2
IO191NDB3
T19
GDA1/IO113PDB1
V11
IO149RSB2
Y3
NC
T20
NC
V12
IO143RSB2
Y4
IO182RSB2
T21
IO108PDB1
V13
IO138RSB2
Y5
GND
T22
IO105NDB1
V14
IO131RSB2
Y6
IO177RSB2
U1
IO195PDB3
V15
IO125RSB2
Y7
IO174RSB2
U2
IO195NDB3
V16
GDB2/IO115RSB2
Y8
VCC
U3
IO194NPB3
V17
TDI
Y9
VCC
U4
GEB1/IO189PDB3
V18
GNDQ
Y10
IO154RSB2
U5
GEB0/IO189NDB3
V19
TDO
Y11
IO148RSB2
U6
VMV2
V20
GND
Y12
IO140RSB2
U7
IO179RSB2
V21
NC
Y13
NC
U8
IO171RSB2
V22
IO109NDB1
Y14
VCC
R ev i si o n 1 5
4- 79
Package Pin Assignments
FG484
FG484
Pin Number
A3P1000 Function
Pin Number
A3P1000 Function
Y15
VCC
AB7
IO167RSB2
Y16
NC
AB8
IO162RSB2
Y17
NC
AB9
IO156RSB2
Y18
GND
AB10
IO150RSB2
Y19
NC
AB11
IO145RSB2
Y20
NC
AB12
IO144RSB2
Y21
NC
AB13
IO132RSB2
Y22
VCCIB1
AB14
IO127RSB2
AA1
GND
AB15
IO126RSB2
AA2
VCCIB3
AB16
IO123RSB2
AA3
NC
AB17
IO121RSB2
AA4
IO181RSB2
AB18
IO118RSB2
AA5
IO178RSB2
AB19
NC
AA6
IO175RSB2
AB20
VCCIB2
AA7
IO169RSB2
AB21
GND
AA8
IO166RSB2
AB22
GND
AA9
IO160RSB2
AA10
IO152RSB2
AA11
IO146RSB2
AA12
IO139RSB2
AA13
IO133RSB2
AA14
NC
AA15
NC
AA16
IO122RSB2
AA17
IO119RSB2
AA18
IO117RSB2
AA19
NC
AA20
NC
AA21
VCCIB1
AA22
GND
AB1
GND
AB2
GND
AB3
VCCIB2
AB4
IO180RSB2
AB5
IO176RSB2
AB6
IO173RSB2
4- 80
R ev i sio n 1 5
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the ProASIC3 datasheet.
Revision
Revision 15
(July 2014)
Changes
Page
Added corner pad table note (3) to "QN132 – Bottom View" (SAR 47442).
4-6
Ambient temperature removed in Table 2-2, table notes and "ProASIC3 Ordering
Information" figure were modified (SAR 48343).
2-2
1-III
Other updates were made to maintain the style and consistency of the datasheet.
NA
Revision 14
(April 2014)
Note added for the discontinuance of QN132 package to the following tables and
section: "ProASIC3 Devices", "I/Os Per Package 1", "ProASIC3 FPGAs Package
Sizes Dimensions" and "QN132 – Bottom View" section (SAR 55118).
I, II, 4-6
Revision 13
(January 2013)
The "ProASIC3 Ordering Information" section has been updated to mention "Y" as
"Blank" mentioning "Device Does Not Include License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43104).
1-III
Added a note to Table 2-2 • Recommended Operating Conditions 1 (SAR 43644):
The programming temperature range supported is Tambient = 0°C to 85°C.
2-2
The note in Table 2-115 • ProASIC3 CCC/PLL Specification referring the reader to
SmartGen was revised to refer instead to the online help associated with the core
(SAR 42569).
2-89
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40284).
NA
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
Revision 12
(September 2012)
The Security section was modified to clarify that Microsemi does not support
read-back of programmed data.
1-1
Added a Note stating "VMV pins must be connected to the corresponding VCCI pins.
See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to
Table 2-1 • Absolute Maximum Ratings and Table 2-2 • Recommended Operating
Conditions 1 (SAR 38321).
2-1
2-2
Table 2-35 • Duration of Short Circuit Event Before Failure was revised to change
the maximum temperature from 110°C to 100°C, with an example of six months
instead of three months (SAR 37933).
2-30
In Table 2-93 • Minimum and Maximum DC Input and Output Levels, VIL and VIH
were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR
28549).
2-67
Figure 2-36 • FIFO Read and Figure 2-37 • FIFO Write are new (SAR 28371).
2-98
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions" chapter: "Within the package, the VMV plane is
decoupled from the simultaneous switching noise originating from the output buffer
VCCI domain" and replaced with “Within the package, the VMV plane biases the
input stage of the I/Os in the I/O banks” (SAR 38321). The datasheet mentions that
"VMV pins must be connected to the corresponding VCCI pins" for an ESD
enhancement.
3-1
R ev i si o n 1 5
5-1
Datasheet Information
Revision
Revision 11
(March 2012)
Revision 10
(September 2011)
Changes
Page
Note indicating that A3P015 is not recommended for new designs has been added.
The "Devices Not Recommended For New Designs" section is new (SAR 36760).
I to IV
The following sentence was removed from the Advanced Architecture section: "In
addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface" (SAR
34687).
NA
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Contribution—PCLOCK" section, was corrected to the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
User's Guide (SAR 34734).
2-11
Figure 2-3 • Input Buffer Timing Model and Delays (Example) has been modified for
the DIN waveform; the Rise and Fall time label has been changed to tDIN (35430).
2-15
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34883).
2-31
Added values for minimum pulse width and removed the FRMAX row from
Table 2-107 through Table 2-114 in the "Global Tree Timing Characteristics" section.
Use the software to determine the FRMAX for the device you are using (SARs
37279, 29269).
2-84
The "In-System Programming (ISP) and Security" section and Security section were
revised to clarify that although no existing security measures can give an absolute
guarantee, Microsemi FPGAs implement the best security available in the industry
(SAR 32865).
I
The value of 34 I/Os for the QN48 package in A3P030 was added to the "I/Os Per
Package 1" section (SAR 33907).
II
The Y security option and Licensed DPA Logo were added to the "ProASIC3
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a
product is covered by a DPA counter-measures license from Cryptography
Research (SAR 32151).
III
The "Specifying I/O States During Programming" section is new (SAR 21281).
Conditions 1,
In Table 2-2 • Recommended Operating
VPUMP programming voltage
in programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45" (SAR 30666).
It was corrected in v2.0 of this datasheet in April 2007 but inadvertently changed
back to “3.0 to 3.6 V” in v1.4 in August 2009. The following changes were made to
Table 2-2 • Recommended Operating Conditions 1:
1-7
2-2
VCCPLL analog power supply (PLL) was changed from "1.4 to 1.6" to "1.425 to
1.575" (SAR 33850).
For VCCI and VMV, values for 3.3 V DC and 3.3 V DC Wide Range were corrected.
The correct value for 3.3 V DC is "3.0 to 3.6 V" and the correct value for 3.3 V Wide
Range is "2.7 to 3.6" (SAR 33848).
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings was
update to restore values to the correct columns. Previously the Slew Rate column
was missing and data were aligned incorrectly (SAR 34034).
2-23
The notes regarding drive strength in the "Summary of I/O Timing Characteristics – 2-21, 2-38
Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range" section
tables were revised for clarification. They now state that the minimum drive strength
for the default software configuration when run in wide range is ±100 µA. The drive
strength displayed in software is supported in normal range only. For a detailed I/V
curve, refer to the IBIS models (SAR 25700).
5- 2
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
Revision
Revision 10
(continued)
Changes
Page
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-28 • I/O Output Buffer Maximum
Resistances1 through Table 2-30 • I/O Output Buffer Maximum Resistances1 was
replaced by "Same as regular 3.3 V" (SAR 33852).
2-25 to
2-27
The equations in the notes for Table 2-31 • I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 32470).
2-27
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-32 • I/O Short Currents IOSH/IOSL
through Table 2-34 • I/O Short Currents IOSH/IOSL was replaced by "Same as
regular 3.3 V LVCMOS" (SAR 33852).
2-28 to
2-30
In the "3.3 V LVCMOS Wide Range" section, values were added to Table 2-47
through Table 2-49 for IOSL and IOSH, replacing "TBD" (SAR 33852).
2-38 to
2-39
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916):
"It uses a 5 V–tolerant input buffer and push-pull output buffer."
2-46
The table notes were revised for Table 2-90 • LVDS Minimum and Maximum DC
Input and Output Levels (SAR 33859).
2-65
Values were added for FDDRIMAX and FDDOMAX in Table 2-102 • Input DDR 2-77, 2-79
Propagation Delays and Table 2-104 • Output DDR Propagation Delays (SAR
23919).
Table 2-115 • ProASIC3 CCC/PLL Specification was updated. A note was added to
indicate that when the CCC/PLL core is generated by Microsemi core generator
software, not all delay values of the specified delay increments are available (SAR
25705).
2-89
The following figures were deleted (SAR 29991). Reference was made to a new
application note, Simultaneous Read-Write Operations in Dual-Port SRAM for
Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 21770).
Figure 2-34 • Write Access after Write onto Same Address
Figure 2-35 • Read Access after Write onto Same Address
Figure 2-35 • Read Access after Write onto Same Address
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-38 • FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SARs 29991, 30510).
July 2010
2-92,
2-94,
2-99
2-101
The "Pin Descriptions" chapter has been added (SAR 21642).
3-1
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 27395).
4-1
The versioning system for datasheets has been changed. Datasheets are assigned
a revision number that increments each time the datasheet is revised. The
"ProASIC3 Device Status" table on page III indicates the status for each device in
the device family.
N/A
R ev i si o n 1 5
5-3
Datasheet Information
Revision
Changes
Page
Revision 9 (Oct 2009) The CS121 package was added to table under "Features and Benefits" section,
the "I/Os Per Package 1" table, Table 1 • ProASIC3 FPGAs Package Sizes
Product Brief v1.3
Dimensions, "ProASIC3 Ordering Information", and the "Temperature Grade
Offerings" table.
"ProASIC3 Ordering Information" was revised to include the fact that some RoHS
compliant packages are halogen-free.
Packaging v1.5
The "CS121 – Bottom View" figure and pin table for A3P060 are new.
Revision 8 (Aug 2009) All references to M7 devices (CoreMP7) and speed grade –F were removed from
this document.
Product Brief v1.2
DC and Switching
Characteristics v1.4
I – IV
III
4-15
N/A
Table 1-1 I/O Standards supported is new.
1-7
The I/Os with Advanced I/O Standards section was revised to add definitions of
hot-swap and cold-sparing.
1-7
3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
N/A
IIL and IIH input leakage current information was added to all "Minimum and
Maximum DC Input and Output Levels" tables.
N/A
–F was removed from the datasheet. The speed grade is no longer supported.
N/A
The notes in Table 2-2 • Recommended Operating
Conditions 1
were updated.
2-2
Table 2-4 • Overshoot and Undershoot Limits 1 was updated.
2-2
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
2-6
In Table 2-116 • RAM4K9, the following specifications were removed:
2-94
tWRO
tCCKH
In Table 2-117 • RAM512X18, the following specifications were removed:
2-96
tWRO
tCCKH
In the title of Table 2-74 • 1.8 V LVCMOS High Slew, VCCI had a typo. It was
changed from 3.0 V to 1.7 V.
2-57
Revision 7 (Feb 2009) The "Advanced I/O" section was revised to add a bullet regarding wide range
power supply voltage support.
Product Brief v1.1
I
The table under "Features and Benefits" section, was updated to include a value
for typical equivalent macrocells for A3P250.
I
The QN48 package was added to the following tables: the table under "Features
and Benefits" section, "I/Os Per Package 1" "ProASIC3 FPGAs Package Sizes
Dimensions", and "Temperature Grade Offerings".
N/A
The number of singled-ended I/Os for QN68 was added to the "I/Os Per
Package 1" table.
The Wide Range I/O Support section is new.
1-7
Revision 6 (Dec 2008) The "QN48 – Bottom View" section is new.
4-1
Packaging v1.4
4-5
5- 4
The "QN68" pin table for A3P030 is new.
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
Revision
Changes
Page
Revision 5 (Aug 2008) TJ, Maximum Junction Temperature, was changed to 100° from 110º in the
"Thermal Characteristics" section and EQ 1. The calculated result of Maximum
DC and Switching
Power Allowed has thus changed to 1.463 W from 1.951 W.
Characteristics v1.3
2-5
Values for the A3P015 device were added to Table 2-7 • Quiescent Supply
Current Characteristics.
2-6
Values for the A3P015 device were added to Table 2-14 • Different Components 2-10, 2-11
Contributing to Dynamic Power Consumption in ProASIC3 Devices. PAC14 was
removed. Table 2-15 • Different Components Contributing to the Static Power
Consumption in ProASIC3 Devices is new.
The "PLL Contribution—PPLL" section was updated to change the PPLL formula
from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT.
2-13
Both fall and rise values were included for tDDRISUD and tDDRIHD in Table 2-102 •
Input DDR Propagation Delays.
2-77
Table 2-107 • A3P015 Global Resource is new.
2-85
The typical value for Delay Increments in Programmable Delay Blocks was
changed from 160 to 200 in Table 2-115 • ProASIC3 CCC/PLL Specification.
2-89
Revision 4 (Jun 2008) Table note references were added to Table 2-2 • Recommended Operating
Conditions 1, and the order of the table notes was changed.
DC and Switching
2-2
Characteristics v1.2
The title for Table 2-4 • Overshoot and Undershoot Limits 1 was modified to
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os."
2-2
The "Power per I/O Pin" section was updated to include 3 additional tables
pertaining to input buffer power and output buffer power.
2-6
Table 2-29 • I/O Output Buffer Maximum Resistances 1 was revised to include
values for 3.3 V PCI/PCI-X.
2-26
Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels was
updated.
2-65
Revision 3 (Jun 2008) Pin numbers were added to the "QN68 – Bottom View" package diagram. Note 2
was added below the diagram.
Packaging v1.3
4-3
The "QN132 – Bottom View" package diagram was updated to include D1 to D4.
In addition, note 1 was changed from top view to bottom view, and note 2 is new.
4-6
Revision 2 (Feb 2008) This document was divided into two sections and given a version number, starting
at v1.0. The first section of the document includes features, benefits, ordering
Product Brief v1.0
information, and temperature and speed grade offerings. The second section is a
device family overview.
N/A
This document was updated to include A3P015 device information. QN68 is a
new package that was added because it is offered in the A3P015. The following
sections were updated:
N/A
"Features and Benefits"
"ProASIC3 Ordering Information"
"Temperature Grade Offerings"
"ProASIC3 Flash Family FPGAs"
"A3P015 and A3P030" note
Introduction and Overview (NA)
R ev i si o n 1 5
5-5
Datasheet Information
Revision
Revision 2 (cont’d)
Packaging v1.2
Changes
Page
The "ProASIC3 FPGAs Package Sizes Dimensions" table is new.
II
In the "ProASIC3 Ordering Information", the QN package measurements were
updated to include both 0.4 mm and 0.5 mm.
III
In the General Description section the number of I/Os was updated from 288 to
300.
1-1
The "QN68 – Bottom View" section is new.
4-3
1
Revision 1 (Feb 2008) In Table 2-2 • Recommended Operating Conditions , TJ was listed in the symbol
column and was incorrect. It was corrected and changed to TA.
DC and Switching
2-2
Characteristics v1.1
In Table 2-3 • Flash Programming Limits – Retention, Storage and Operating
Temperature, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
2-2
The "PLL Behavior at Brownout Condition" section is new.
2-3
In the "PLL Contribution—PPLL" section, the following was deleted:
2-13
FCLKIN is the input clock frequency.
In Table 2-21 • Summary of Maximum and Minimum DC Input Levels, the note
was incorrect. It previously said TJ and it was corrected and changed to TA.
2-20
In Table 2-115 • ProASIC3 CCC/PLL Specification, the SCLK parameter and note
1 are new.
2-89
Table 2-125 • JTAG 1532 was populated with the parameter data, which was not
in the previous version of the document.
2-107
In the "VQ100" A3P030 pin table, the function of pin 63 was incorrect and
changed from IO39RSB0 to GDB0/IO38RSB0.
4-19
Revision 0 (Jan 2008) This document was previously in datasheet v2.2. As a result of moving to the
handbook format, Actel has restarted the version numbers.
N/A
Packaging v1.1
v2.2
(July 2007)
v2.1
(May 2007)
5- 6
The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3
Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering
Information", "Temperature Grade Offerings", and "Speed Grade and
Temperature Grade Matrix".
i, ii, iii,
iii, iv
The words "ambient temperature" were added to the temperature range in the
"Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings",
and "Speed Grade and Temperature Grade Matrix" sections.
iii, iv
The TJ parameter in Table 3-2 • Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
3-2
In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input
Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).
i
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
i
In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and
A3P600 device I/Os were updated.
ii
Table 3-5 • Package Thermal Resistivities was updated with A3P1000
information. The note below the table is also new.
3-5
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
Revision
v2.0
(April 2007)
Changes
Page
In the "Packaging Tables", Ambient was deleted.
ii
The timing characteristics tables were updated.
N/A
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
2-15
The "PLL Macro" section was updated to include power-up information.
2-15
Table 2-11 • ProASIC3 CCC/PLL Specification was updated.
2-29
Figure 2-19 • Peak-to-Peak Jitter Definition is new.
2-18
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
2-21
The "RESET" section was updated with read and write information.
2-25
The "RESET" section was updated with read and write information.
2-25
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
2-28
PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible
Standards.
2-29
In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
2-34
Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3
Devices was updated.
2-64
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
2-40
The "VCCPLF PLL Supply Voltage" section was updated.
2-50
The "VPUMP Programming Supply Voltage" section was updated.
2-50
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
2-51
VJTAG was deleted from the "TCK Test Clock" section.
2-51
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
2-51
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on
quiet I/Os)1.
3-2
In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.
3-5
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-6
Table 3-5 • Package Thermal Resistivities was updated.
3-5
Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels 3-17 to 3Applicable to Commercial and Industrial Conditions—Software Default Settings
17
(Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input
Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were
updated.
R ev i si o n 1 5
5-7
Datasheet Information
Revision
v2.0
(continued)
Changes
Page
Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings
(Advanced) and Table 3-21 • Summary of I/O Timing Characteristics—Software
Default Settings (Standard Plus) were updated.
3-20 to
3-20
Table 3-11 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3 Devices was updated.
3-9
Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 325 • I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.
3-22 to
3-22
Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to
Commercial and Industrial Conditions was updated.
3-18
Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O
Short Currents IOSH/IOSL (Standard Plus) were updated.
3-24 to
3-26
The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-27
Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read
Access After Write onto Same Address, and Figure 3-35 • Write Access After
Read onto Same Address are new.
3-82 to
3-84
Figure 3-43 • Timing Diagram was updated.
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
iv
Notes were added to the package diagrams identifying if they were top or bottom
view.
N/A
The A3P030 "132-Pin QFN" table is new.
4-2
The A3P060 "132-Pin QFN" table is new.
4-4
The A3P125 "132-Pin QFN" table is new.
4-6
The A3P250 "132-Pin QFN" table is new.
4-8
The A3P030 "100-Pin VQFP" table is new.
4-11
Advance v0.7
(January 2007)
In the "I/Os Per Package" table, the I/O numbers were added for A3P060,
A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77.
Advance v0.6
(April 2006)
The term flow-through was changed to pass-through.
5- 8
3-96
ii
N/A
Table 1 was updated to include the QN132.
ii
The "I/Os Per Package" table was updated with the QN132. The footnotes were
also updated. The A3P400-FG144 I/O count was updated.
ii
"Automotive ProASIC3 Ordering Information" was updated with the QN132.
iii
"Temperature Grade Offerings" was updated with the QN132.
iii
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-7 • Efficient Long-Line Resources was updated.
2-7
The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF,
CLKBUF_LVDS/LVPECL, and CLKINT were updated.
2-16
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
R ev isio n 1 5
ProASIC3 Flash Family FPGAs
Revision
Advance v0.6
(continued)
Changes
Page
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
The "Introduction" of the "Advanced I/Os" section was updated.
2-28
The "I/O Banks" section is new. This section explains the following types of I/Os:
2-29
Advanced
Standard+
Standard
Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is
new. This table describes the standards listed above.
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 211 • VCCI Voltages and Compatible Standards
2-29
Table 2-13 • ProASIC3 I/O Features was updated.
2-30
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
2-32
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
2-35
Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
2-64
The notes in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3 Devices were updated.
2-64
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
2-41
A footnote was added to Table 2-14 • Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum
drive strength and high slew selected).
2-30
Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications
2-45
Table 2-50 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type
(A3P030 device)
2-83
Table 2-51 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated.
2-84
Table 2-54 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated.
2-84
The "x" was updated in the "User I/O Naming Convention" section.
2-48
The "VCC Core Supply Voltage" pin description was updated.
2-50
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected.
2-50
The "VJTAG JTAG Supply Voltage" pin description was updated.
2-50
The "VPUMP Programming Supply Voltage" pin description was updated to
include information on what happens when the pin is tied to ground.
2-50
The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused.
2-50
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
2-51
R ev i si o n 1 5
5-9
Datasheet Information
Revision
Advance v0.6
(continued)
Changes
Page
The "Programming" section was updated to include information concerning
serialization.
2-53
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information.
2-54
"DC and Switching Characteristics" chapter was updated with new information.
Advance v0.5
(November 2005)
The A3P060 "100-Pin VQFP" pin table was updated.
4-13
The A3P125 "100-Pin VQFP" pin table was updated.
4-13
The A3P060 "144-Pin TQFP" pin table was updated.
4-16
The A3P125 "144-Pin TQFP" pin table was updated.
4-18
The A3P125 "208-Pin PQFP" pin table was updated.
4-21
The A3P400 "208-Pin PQFP" pin table was updated.
4-25
The A3P060 "144-Pin FBGA" pin table was updated.
4-32
The A3P125 "144-Pin FBGA" pin table is new.
4-34
The A3P400 "144-Pin FBGA" is new.
4-38
The A3P400 "256-Pin FBGA" was updated.
4-48
The A3P1000 "256-Pin FBGA" was updated.
4-54
The A3P400 "484-Pin FBGA" was updated.
4-58
The A3P1000 "484-Pin FBGA" was updated.
4-68
The A3P250 "100-Pin VQFP*" pin table was updated.
4-14
The A3P250 "208-Pin PQFP*" pin table was updated.
4-23
The A3P1000 "208-Pin PQFP*" pin table was updated.
4-29
The A3P250 "144-Pin FBGA*" pin table was updated.
4-36
The A3P1000 "144-Pin FBGA*" pin table was updated.
4-32
The A3P250 "256-Pin FBGA*" pin table was updated.
4-45
The A3P1000 "256-Pin FBGA*" pin table was updated.
4-54
The A3P1000 "484-Pin FBGA*" pin table was updated.
4-68
The "I/Os Per Package" table was updated for the following devices and
packages:
Device
A3P250/M7ACP250
A3P250/M7ACP250
A3P1000
Advance v0.4
Advance v0.3
5- 10
3-1
ii
Package
VQ100
FG144
FG256
M7 device information is new.
N/A
The I/O counts in the "I/Os Per Package" table were updated.
ii
The "I/Os Per Package" table was updated.
ii
M7 device information is new.
N/A
Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include
the number or rows in each top or bottom spine.
2-16
EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options.
2-24
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
Revision
Advance v0.3
Changes
Page
The "PLL Macro" section was updated. EXTFB information was removed from
this section.
2-15
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 211 • ProASIC3 CCC/PLL Specification
2-29
EXTFB was removed from Figure 2-27 • CCC/PLL Macro.
2-28
Table 2-13 • ProASIC3 I/O Features was updated.
2-30
The "Hot-Swap Support" section was updated.
2-33
The "Cold-Sparing Support" section was updated.
2-34
"Electrostatic Discharge (ESD) Protection" section was updated.
2-35
The LVPECL specification in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3 Devices was updated.
2-64
In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was
changed to VCCIB1.
2-97
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
2-50
The "JTAG Pins" section was updated.
2-51
"128-Bit AES Decryption" section was updated to include M7 device information.
2-53
Table 3-6 was updated.
3-6
Table 3-7 was updated.
3-6
In Table 3-11, PAC4 was updated.
Table 3-20 was updated.
3-20
The note in Table 3-32 was updated.
3-27
All Timing Characteristics tables were updated from LVTTL to Register Delays
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
Advance v0.2
3-93-8
3-31 to 373
3-85 to
3-90
FTCKMAX was updated in Table 3-110.
3-97
Figure 2-11 was updated.
2-9
The "Clock Resources (VersaNets)" section was updated.
2-9
The "VersaNet Global Networks and Spine Access" section was updated.
2-9
The "PLL Macro" section was updated.
2-15
Figure 2-27 was updated.
2-28
Figure 2-20 was updated.
2-19
Table 2-5 was updated.
2-25
Table 2-6 was updated.
2-25
The "FIFO Flag Usage Considerations" section was updated.
2-27
Table 2-13 was updated.
2-30
Figure 2-24 was updated.
2-31
The "Cold-Sparing Support" section is new.
2-34
R ev i si o n 1 5
5- 11
Datasheet Information
Revision
Advance v0.2,
(continued)
5- 12
Changes
Page
Table 2-43 was updated.
2-64
Table 2-18 was updated.
2-45
Pin descriptions in the "JTAG Pins" section were updated.
2-51
The "User I/O Naming Convention" section was updated.
2-48
Table 3-7 was updated.
3-6
The "Methodology" section was updated.
3-10
Table 3-40 and Table 3-39 were updated.
3-33,3-32
The A3P250 "100-Pin VQFP*" pin table was updated.
4-14
The A3P250 "208-Pin PQFP*" pin table was updated.
4-23
The A3P1000 "208-Pin PQFP*" pin table was updated.
4-29
The A3P250 "144-Pin FBGA*" pin table was updated.
4-36
The A3P1000 "144-Pin FBGA*" pin table was updated.
4-32
The A3P250 "256-Pin FBGA*" pin table was updated.
4-45
The A3P1000 "256-Pin FBGA*" pin table was updated.
4-54
The A3P1000 "484-Pin FBGA*" pin table was updated.
4-68
R ev i sio n 1 5
ProASIC3 Flash Family FPGAs
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "ProASIC3 Device Status" table on page III, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
R ev i si o n 1 5
5- 13
Microsemi Corporate Headquarters
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