LODEV LSH33JC30 32-bit barrel shifter with register Datasheet

LSH33
LSH33
DEVICES INCORPORATED
32-bit Barrel Shifter with Registers
32-bit Barrel Shifter with Registers
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 32-bit Input, 32-bit Output Multiplexed to 16 Lines
❑ Full 0-31 Position Barrel Shift
Capability
❑ Integral Priority Encoder for 32-bit
Floating Point Normalization
❑ Sign-Magnitude or Two’s Complement Mantissa Representation
❑ 32-bit Linear Shifts with Sign or
Zero Fill
❑ Independent Priority Encoder
Outputs for Block Floating Point
❑ 68-pin PLCC, J-Lead
The LSH33 is a 32-bit high speed
shifter designed for use in floating
point normalization, word pack/
unpack, field extraction, and similar
applications. It has 32 data inputs,
and 16 output lines. Any shift configuration of the 32 inputs, including
circular (barrel) shifting, left shifts
with zero fill, and right shifts with
sign extension are possible. In addition, a built-in priority encoder is
provided to aid floating point normalization.
Input/Output registers provide
complete pipelined operation. Both
have independent bypass paths for
complete flexibility. When FTI = 1,
the input registers are bypassed.
Likewise, when FTO= 1, the output
registers are bypassed.
LSH33 BLOCK DIAGRAM
I 31 -I 0
SIGN
G
CLK
ENI
G
2:1
2:1
FTI
32
32:5
PRIORITY
ENCODE
32
2:1
5
32-bit
BARREL
SHIFT
ARRAY
RIGHT/LEFT
FILL/WRAP
16
16
G
2:1
G
5
CLK
ENO
G
2:1
2:1
FTO
5
NORM
2:1
MS/LS
SHIFT ARRAY
The 32 inputs, which can be registered, to the LSH33 are applied to a
32-bit shift array. The 32 outputs,
which can also be registered, of this
array are then multiplexed down to
16 lines for presentation at the device
outputs. The array may be configured
such that any contiguous 16-bit field
(including wraparound of the 32
inputs) may be presented to the
output pins under control of the shift
code field (wrap mode). Alternatively, the wrap feature may be
disabled, resulting in zero or sign bit
fill, as appropriate (fill mode). The
shift code control assignments and the
resulting input to output mapping for
the wrap mode are shown in Table 1.
Essentially the LSH33 is configured as
a left shift device. That is, a shift code
of 000002 results in no shift of the
input field. A code of 000012 provides
an effective left shift of 1 position, etc.
When viewed as a right shift, the shift
code corresponds to the two’s complement of the shift distance, i.e., a shift
code of 111112 (–110) results in a right
shift of one position, etc.
When not in the wrap mode, the
LSH33 fills bit positions for which
there is no corresponding input bit.
The fill value and the positions filled
depend on the RIGHT/LEFT (R/L)
direction pin. This pin is a don’t care
input when in wrap mode. For left
shifts in fill mode, lower bits are filled
with zero as shown in Table 2. For
right shifts, however, the SIGN input
is used as the fill value. Table 3
depicts the bits to be filled as a
function of shift code for the right shift
case. Note that the R/L input changes
only the fill convention, and does not
affect the definition of the shift code.
16
SI/O 4 -SI/O 0
OE
Y 15 -Y 0
Special Arithmetic Functions
1
08/16/2000–LDS.33-O
LSH33
DEVICES INCORPORATED
32-bit Barrel Shifter with Registers
TABLE 1. WRAP MODE SHIFT CODE DEFINITIONS
Shift Code
Y 31
Y 30
Y 29
•••
Y 16
Y 15
•••
Y2
Y1
Y0
00000
00001
00010
00011
I31
I30
I29
I28
I30
I29
I28
I27
I29
I28
I27
I26
•••
I15
I14
I13
I12
•••
•••
I16
I15
I14
I13
•••
I2
I1
I0
I31
I1
I0
I31
I30
I0
I31
I30
I29
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•••
•••
•••
•••
In fill mode, as in wrap mode, the shift
code input represents the number of
shift positions directly for left shifts,
but the two’s complement of the shift
code results in the equivalent right
shift. However, for fill mode the R/L
input can be viewed as the most
significant bit of a 6-bit two’s complement shift code, comprised of R/L
concatenated with the SI4–SI0 lines.
Thus, a positive shift code (R/L = 0)
results in a left shift of 0–31 positions,
and a negative code (R/L = 1) a right
shift of up to 32 positions. The LSH33
can thus effectively select any contiguous 32-bit field out of a (sign extended
and zero filled) 96-bit "input."
•
•
•
•
•••
•
•
•••
•
•
•
01111
10000
10001
10010
I16
I15
I14
I13
I15
I14
I13
I12
I14
I13
I12
I11
•••
I0
I31
I30
I29
•••
•••
I1
I0
I31
I30
•••
I19
I18
I17
I16
I18
I17
I16
I15
I17
I16
I15
I14
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
OUTPUT MULTIPLEXER
•
•
•
•
•••
•
•
•••
•
•
•
11100
11101
11110
11111
I3
I2
I1
I0
I2
I1
I0
I31
I1
I0
I31
I30
•••
I20
I19
I18
I17
I19
I18
I17
I16
•••
I6
I5
I4
I3
I5
I4
I3
I2
I4
I3
I2
I1
The shift array outputs can be registered and then applied to a 2:1 multiplexer controlled by the MS/LS select
line. This multiplexer makes available
at the output pins either the most
significant or least significant 16
outputs of the shift array.
TABLE 2.
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
FILL MODE SHIFT CODE DEFINITIONS — LEFT SHIFT
PRIORITY ENCODER
Shift Code
Y 31
Y 30
Y 29
•••
Y 16
Y 15
•••
Y2
Y1
Y0
00000
00001
00010
00011
I31
I30
I29
I28
I30
I29
I28
I27
I29
I28
I27
I26
•••
I15
I14
I13
I12
•••
•••
I16
I15
I14
I13
•••
I2
I1
I0
0
I1
I0
0
0
I0
0
0
0
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•••
•••
•••
•••
•
•
•
•
•••
•
•
•••
•
•
•
01111
10000
10001
10010
I16
I15
I14
I13
I15
I14
I13
I12
I14
I13
I12
I11
•••
I0
0
0
0
•••
•••
I1
I0
0
0
•••
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
11100
11101
11110
11111
I3
I2
I1
I0
I2
I1
I0
0
I1
I0
0
0
•••
0
0
0
0
0
0
0
0
•••
0
0
0
0
0
0
0
0
0
0
0
0
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
The 32-bit input bus drives a priority
encoder which is used to determine
the first significant position for
purposes of normalization. The
priority encoder produces a five-bit
code representing the location of the
first non-zero bit in the input word.
Code assignment is such that the
priority encoder output represents the
number of shift positions required to
left align the first non-zero bit of the
input word. Prior to the priority
encoder, the input bits are individually exclusive OR’ed with the SIGN
input. This allows normalization in
floating point systems using two’s
complement mantissa representation.
A negative value in two’s complement
representation will cause the exclusive
OR gates to invert the input data to
the encoder. As a result, the leading
significant digit will always be "1."
Special Arithmetic Functions
2
08/16/2000–LDS.33-O
LSH33
DEVICES INCORPORATED
TABLE 3.
32-bit Barrel Shifter with Registers
FILL MODE SHIFT CODE DEFINITIONS — RIGHT SHIFT
Shift Code
Y 31
Y 30
Y 29
•••
Y 16
Y 15
•••
Y2
Y1
Y0
00000
00001
00010
00011
S
S
S
S
S
S
S
S
S
S
S
S
•••
S
S
S
S
•••
•••
S
S
S
S
•••
S
S
S
I31
S
S
I31
I30
S
I31
I30
I29
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•••
•••
•••
•••
•
•
•
•
•••
•
•
•••
•
•
•
01111
10000
10001
10010
S
S
S
S
S
S
S
S
S
S
S
S
•••
S
I31
I30
I29
•••
•••
S
S
I31
I30
•••
I19
I18
I17
I16
I18
I17
I16
I15
I17
I16
I15
I14
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
11100
11101
11110
11111
S
S
S
S
S
S
S
I31
S
S
I31
I30
•••
I20
I19
I18
I17
I19
I18
I17
I16
•••
•••
I6
I5
I4
I3
I5
I4
I3
I2
I4
I3
I2
I1
TABLE 4.
•••
•••
•••
•••
•••
•••
•••
•••
•••
PRIORITY ENCODER FUNCTION TABLE
I31
I30
I29
•••
I16
I15
•••
I2
I1
I0
Shift Code
1
0
0
X
1
0
X
X
1
•••
X
X
X
•••
•••
X
X
X
•••
X
X
X
X
X
X
X
X
X
00000
00001
00010
•
•
•
•••
•
•
•••
•
•
•
•
•••
•••
•
•
•
•••
•
•
•••
•
•
•
•
0
0
0
0
0
0
0
0
0
•••
X
1
0
•••
•••
1
0
0
•••
X
X
X
X
X
X
X
X
X
01111
10000
10001
•
•
•
•••
•
•
•••
•
•
•
•
•
•
•
•••
•
•
•••
•
•
•
•
0
0
0
0
0
0
0
0
0
•••
0
0
0
0
0
0
•••
0
0
0
1
0
0
X
1
0
11110
11111
11111
•••
•••
•••
•••
•••
•••
This affects only the encoder inputs;
the shift array always operates on the
raw input data. The priority encoder
function table is shown in Table 4.
NORMALIZE MULTIPLEXER
The NORM input, when asserted,
results in the priority encoder output
driving the internal shift code inputs
directly. When using the NORM
function, the LSH33 should be placed
in fill mode, with the R/L input low.
When NORM is high (not asserted),
the SI/O 4–SI/O 0 port acts as the shift
code input to the shifter.
APPLICATIONS EXAMPLES
Normalization of mantissas up to 32
bits can be accomplished directly by a
single LSH33. To do this, the NORM
input is asserted, and fill mode and
left shift are selected. The normalized
mantissa is then available at the
device output in two 16-bit segments,
under the control of the output data
multiplexer select, the MS/LS signal.
If it is desirable to avoid the necessity
of multiplexing output data in 16-bit
segments, two LSH33 devices can be
used in parallel. Both devices receive
the same input word, with the MS/LS
select line of one wired high, and the
other low. Each device will then
independently determine the shift
distance required for normalization,
and the full 32 bits of output data will
be available simultaneously.
Special Arithmetic Functions
3
08/16/2000–LDS.33-O
LSH33
DEVICES INCORPORATED
32-bit Barrel Shifter with Registers
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
–55°C to +125°C
4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
2.4
Unit
V
0.4
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±20
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±20
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
30
mA
ICC2
VCC Current, Quiescent
(Note 7)
1.5
mA
10
Special Arithmetic Functions
4
08/16/2000–LDS.33-O
LSH33
DEVICES INCORPORATED
32-bit Barrel Shifter with Registers
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM C123456789012345678901234567
OMBINATIONAL DELAYS Notes 9, 10 (ns)
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Y15-Y0
SO4-SO0
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—
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To Output 123456789012345678901234567
LSH33-40*
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From Input
FTI = 0, FTO = 0
CLK
MS/LS
FTI = 0, FTO= 1
CLK (NORM = 0/1)
SI4-SI0
R/L, F/W
MS/LS
FTI = 1, FTO = 0
CLK
MS/LS
FTI = 1, FTO = 1
I31-I0, SIGN
(NORM = 0/1)
SI4-SI0
R/L, F/W
MS/LS
LSH33-30
Y15-Y0
SO4-SO0
24
24
24
—
58 / 30
40
40
24
42 / —
—
—
—
24
24
24
—
58 / 30
42 / —
—
—
—
40
40
24
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LSH33-20*
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Y15-Y0
SO4-SO0
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—
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—
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GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING E
DGE Notes 9, 10 (ns)
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Input
I31-I0, SIGN
SI4-SI0
R/L, F/W
ENI, ENO
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*
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LSH33-40
LSH33-30
LSH33-20*
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FTI = 0
FTI = 1
FTI = 0
FTI = 1
FTI = 0
FTI = 1 123456789012345678901234567
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Setup Hold Setup Hold Setup Hold Setup Hold 123456789012345678901234567
Setup Hold Setup Hold
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12
3
20
2
10
3
15
2 123456789012345678901234567
8
0
8
2
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17
0
17
0
15
0
15
0 123456789012345678901234567
8
0
8
0
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12
0
12
0
10
0
10
0 123456789012345678901234567
8
0
8
0
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12
0
12
0
10
0
10
0 123456789012345678901234567
8
0
8
0
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TRI-STATE1234567890123
ENABLE/DISABLE TIMES Notes1234567890123
9, 10, 11 (ns)
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LSH33-40*
LSH33-30 1234567890123
LSH33-20*
1234567890123
1234567890123
tENA
tDIS
1234567890123
1234567890123
1234567890123
20
1234567890123
1234567890123
1234567890123
1234567890123
20
1234567890123
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
17
17
1234567890123
1234567890123
1234567890123
15
1234567890123
1234567890123
1234567890123
1234567890123
15
1234567890123
CLOCK CYCLE TIME
AND PULSE WIDTH Notes1234567890123
9, 10 (ns)
1234567890123
1234567890123
1234567890123
1234567890123
LSH33-40*
LSH33-30 1234567890123
LSH33-20*
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
Minimum Cycle Time1234567890123
30
20
15
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
Highgoing Pulse 1234567890123
12
9
7
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
Lowgoing Pulse
12
9
7
1234567890123
1234567890123
1234567890123
1234567890123
Special Arithmetic Functions
5
08/16/2000–LDS.33-O
LSH33
DEVICES INCORPORATED
32-bit Barrel Shifter with Registers
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
GUARANTEED MAXIMUM C123456789012345678901234567890121234567890123456789012345678901212345678901234
OMBINATIONAL DELAYS Notes 9, 10 (ns)
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Y15-Y0
SO4-SO0
Y15-Y0
SO4-SO0
Y15-Y0
SO4-SO0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
28
28
24
24
32
32
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
28
—
24
—
32
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
55 / —
42 / —
73 / 40
58 / 30
80 / 50
65 / —
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
52
—
40
—
62
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
52
—
40
—
62
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
28
—
24
—
32
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
28
28
24
24
32
32
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
28
—
24
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
32
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
73 / 40
58 / 30
55 / —
42 / —
80 / 50
65 / —
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
52
—
40
—
62
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
52
—
40
—
62
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
28
—
24
—
62
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
LSH33-40*
LSH33-30*
To Output 123456789012345678901234567890121234567890123456789012345678901212345678901234
LSH33-50*
123456789012345678901234567890121234567890123456789012345678901212345678901234
From Input
FTI = 0, FTO = 0
CLK
MS/LS
FTI = 0, FTO= 1
CLK (NORM = 0/1)
SI4-SI0
R/L, F/W
MS/LS
FTI = 1, FTO = 0
CLK
MS/LS
FTI = 1, FTO = 1
I31-I0, SIGN
(NORM = 0/1)
SI4-SI0
R/L, F/W
MS/LS
GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
123456789012345678901234567890121234567890123456789012345678901212345678901234
Input
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
LSH33-50*
LSH33-40*
LSH33-30*
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTI = 0
FTI = 1
FTI = 0
FTI = 1
FTI = 0
FTI = 1
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
15
3
20
2
12
3
20
2
10
0
15
2
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
20
0
20
0
17
0
17
0
15
0
15
0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
15
0
15
0
12
0
12
0
10
0
10
0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
15
0
15
0
12
0
12
0
10
0
10
0
123456789012345678901234567890121234567890123456789012345678901212345678901234
I31-I0, SIGN
SI4-SI0
R/L, F/W
ENI, ENO
TRI-STATE1234567890123456789012345678901212345
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
tENA
tDIS
1234567890123456789012345678901212345
1234567890123456789012345678901212345
LSH33-50*
LSH33-40*
LSH33-30*
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
22
20
17
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
22
20
17
1234567890123456789012345678901212345
1234567890123456789012345678901212345
CLOCK CYCLE TIME
AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
LSH33-50*
LSH33-40*
LSH33-30*
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Minimum Cycle Time12345678901234567890123456789012123456
35
30
20
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Highgoing Pulse 12345678901234567890123456789012123456
15
12
9
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Lowgoing Pulse
15
12
9
12345678901234567890123456789012123456
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
Special Arithmetic Functions
6
08/16/2000–LDS.33-O
LSH33
DEVICES INCORPORATED
32-bit Barrel Shifter with Registers
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of I OH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a min-
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
imum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
VCC or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
any device always provides data within
but not 100% tested.
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
Special Arithmetic Functions
7
08/16/2000–LDS.33-O
LSH33
DEVICES INCORPORATED
32-bit Barrel Shifter with Registers
ORDERING INFORMATION
I29
I28
I27
I26
I25
I24
I23
I22
I21
I20
I19
I18
I17
I16
I15
I14
GND
68-pin
10
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
Top
View
18
19
53
52
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
GND
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
VCC
VCC
Y30/14
Y29/13
Y28/12
Y27/11
Y26/10
Y25/9
Y24/8
Y23/7
Y22/6
Y21/5
Y20/4
Y19/3
Y18/2
Y17/1
Y16/0
OE
MS/LS
I30
I31
SIGN
SI/O4
SI/O3
SI/O2
SI/O1
SI/O0
NORM
CLK
ENI
FTI
ENO
FTO
R/L
F/W
Y31/15
Speed
Plastic J-Lead Chip Carrier
(J2)
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
68-pin
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1
2
3
4
5
6
7
8
9
10
11
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
A
1234567890123456789012345678901212345678901234567
I29
I28
I14
I26
I24
I22
I20
I18
I16
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
B
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
I31
I30
I27
I25
I23
I21
I19
I17
I15 GND GND
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
C
1234567890123456789012345678901212345678901234567
SI/O4 SIGN
I12
I13
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
D
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
SI/O2 SI/O3
I10
I11
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
E
1234567890123456789012345678901212345678901234567
Top View
SI/O0 SI/O1
I8
I9
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
Through Package
F
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
CLK NORM
I6
I7
(i.e., Component Side Pinout)
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
G
1234567890123456789012345678901212345678901234567
FTI ENI
I4
I5
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
H
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
FTO ENO
I2
I3
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
J
1234567890123456789012345678901212345678901234567
F/W R/L
I0
I1
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
K
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
Y31/15 Y30/14 Y28/12 Y26/10 Y24/8 Y22/6 Y20/4 Y18/2 Y16/0 VCC VCC
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
L
1234567890123456789012345678901212345678901234567
Y29/13 Y27/11 Y25/9 Y23/7 Y21/5 Y19/3 Y17/1 OE MS/LS
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
Discontinued Package
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
1234567890123456789012345678901212345678901234567
Ceramic Pin Grid Array
(G1)
0°C to +70°C — COMMERCIAL SCREENING
30 ns
LSH33JC30
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Special Arithmetic Functions
8
08/16/2000–LDS.33-O
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