ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83026I-01 is a low skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer and HiPerClockS™ a member of the HiPerClockS ™ family of High Perfor mance Clock Solutions from ICS. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. • Two LVCMOS / LVTTL outputs ICS • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 350MHz • Output skew: 15ps (maximum) • Part-to-part skew: 600ps (maximum) • Additive phase jitter, RMS: 0.03ps (typical) • Small 8 lead SOIC package saves board space • 3.3V core, 3.3V, 2.5V or 1.8V output operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VDD CLK nCLK OE Q0 CLK nCLK 1 2 3 4 8 7 6 5 VDDO Q0 Q1 GND ICS83026I-01 Q1 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View OE VDD CLK nCLK OE 1 2 3 4 8 7 6 5 VDDO Q0 Q1 GND ICS83026I-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 83026BMI-01 www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD Power Type Description 2 CLK Input 3 nCLK Input 4 OE Input 5 GND Power 6 Q1 Output Clock output. LVCMOS / LVTTL interface levels. 7 Q0 Output Clock output. LVCMOS / LVTTL interface levels. 8 VDDO Power Output supply pin. Positive supply pin. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Output enable. When HIGH, outputs are enabled. When LOW, outputs are in Pullup High Impedance State. LVCMOS / LVTTL interface levels. Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units VDD, VDDO = 3.465V 17 pF VDD = 3.465V, VDDO = 2.625V 16 pF 4 CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor VDD = 3.465V, VDDO = 1.95V Output Impedance ROUT pF 15 pF 51 kΩ 51 kΩ VDD, VDDO = 3.3V 7 Ω VDD = 3.3V, VDDO = 2.5V 8 Ω VDD = 3.3V, VDDO = 1.8V 10 Ω TABLE 3. CONTROL FUNCTION TABLE Input Outputs OE Q0, Q1 0 HiZ 1 Active 83026BMI-01 www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 8 Lead SOIC 112.7°C/W (0 lfpm) 8 Lead TSSOP 101.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.71 1. 8 VDDO Output Supply Voltage 1.89 V IDD Power Supply Current 10 mA IDDO Output Supply Current 3 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.375V TO 3.465V, TA = -40°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage OE Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage OE -0.3 0.8 V IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V -150 5 µA µA VOH Output High Voltage; NOTE 1 VDDO = 3.135V 2.6 V VDDO = 2.375V 1.8 V VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section, "Output Load Test Circuit" diagrams. 0.5 V TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage OE IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V VOH Output High Voltage VOL Output Low Voltage 83026BMI-01 Minimum Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA OE Typical -150 µA IOH = -100µA VDDO - 0.2 V IOH = -2mA VDDO - 0.45 V IOL = 100µA 0. 2 V IOL = 2mA 0.45 V www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C Symbol Parameter Maximum Units nCLK VIN = VDD = 3.465V Test Conditions 150 µA CLK VIN = VDD = 3.465V 150 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 Minimum Typical nCLK VIN = 0V, VDD = 3.465V -150 µA CLK VIN = 0V, VDD = 3.465V -5 µA 0.15 VCMR Common Mode Input Voltage; NOTE 2, 3 GND + 0.5 NOTE 1: VPP can exceed 1.3V provided that there is sufficient offset level to keep VIL > 0V. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. 1.3 V VDD - 0.85 V TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section Output Rise/Fall Time tjit t R / tF Test Conditions Minimum Typical ƒ≤ 350MHz 1.3 1. 9 Maximum Units 350 MHz 2.5 ns 15 ps 900 ps 0.03 ps 20% to 80% 150 800 ps ƒ≤ 66MHz 48 52 % 67MHz ≤ ƒ≤ 166MHz 45 55 % 167MHz ≤ ƒ≤ 350MHz 40 60 NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 6. % odc 83026BMI-01 Output Duty Cycle www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section Output Rise/Fall Time tjit tR / tF odc Output Duty Cycle Test Conditions ƒ≤ 350MHz Minimum 1. 5 Typical 2.0 Maximum Units 350 MHz 2.6 ns 15 ps 750 ps 0.03 ps 20% to 80% 150 800 ps ƒ≤ 66MHz 48 52 % 67MHz ≤ ƒ≤ 166MHz 46 54 % 167MHz ≤ ƒ≤ 350MHz 40 60 NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter Section Output Rise/Fall Time tjit tR / tF odc Output Duty Cycle Test Conditions ƒ≤ 350MHz Minimum 1.9 Typical 2.5 Maximum Units 350 MHz 3.1 ns 15 ps 600 ps 0.03 ps 20% to 80% 200 900 ps ƒ≤ 66MHz 48 52 % 67MHz ≤ ƒ≤ 166MHz 43 57 % 167MHz ≤ ƒ≤ 350MHz 40 60 NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 83026BMI-01 www.icst.com/products/hiperclocks.html 5 % REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 Input/Output Additive Phase Jitter at 155.52MHz -10 -20 = 0.03ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 83026BMI-01 vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±0.103V 1.25V±5% SCOPE VDD, VDDO VDDO Qx LVCMOS SCOPE VDD Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3VCORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.4±0.125V 0.9V±0.45V V DD SCOPE V DD VDDO nCLK V Cross Points PP Qx LVCMOS V CMR CLK GND GND -0.9V±0.45V 3.3VCORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 V DDO Qx Qx 2 PART 2 V Qy 2 tsk(o) OUTPUT SKEW 83026BMI-01 DDO 2 V DDO DDO Qy V 2 tsk(pp) PART-TO-PART SKEW www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER nCLK CLK 80% Q0, Q1 VDDO 2 t Clock Outputs PD PROPAGATION DELAY 80% 20% 20% tR tF OUTPUT RISE/FALL TIME V DDO 2 Q0, Q1 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 83026BMI-01 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. 83026BMI-01 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 83026BMI-01 www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER SCHEMATIC EXAMPLE LVCMOS drivers. In this example, series termination approach is shown. Additional termination approaches are shown in the LVCMOS Termination Application Note. Figure 3 shows an application schematic example of ICS83026I01. The ICS83026I-01 CLK/nCLK input can directly accepts various types of differential signal. In this example, the input is driven by an LVDS driver. The ICS83026I-01 outputs are VDD 3.3V R3 1K Zo = 50 Ohm VDD R4 100 1 2 3 4 VDD CLK nCLK OE VDDO Q0 Q1 GND VDDO 8 7 6 5 R1 43 Zo = 50 Ohm LVCMOS C2 0.1u LVDS U1 ICS83026I-01 C1 0.1u Zo = 50 Ohm Zo = 50 Ohm VDD=3.3V R2 43 VDDO= 3.3V, 2.5V or 1.8V LVCMOS FIGURE 3. ICS83026I-01 SCHEMATIC EXAMPLE RELIABILITY INFORMATION TABLE 5A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 112.7°C/W 200 500 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE5B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS83026I-0I is: 260 83026BMI-01 www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 6A. PACKAGE DIMENSIONS SYMBOL MINIMUM N A TABLE 6B. PACKAGE DIMENSIONS Millimeters SYMBOL MAXIMUM 8 Millimeters Minimum N Maximum 8 1.35 1.75 A -- 1.20 A1 0.10 0.25 A1 0.05 0.15 B 0.33 0.51 A2 0.80 1.05 C 0.19 0.25 b 0.19 0.30 D 4.80 5.00 c 0.09 0.20 E 3.80 4.00 D 2.90 3.10 e 1.27 BASIC E 6.40 BASIC H 5.80 6.20 E1 h 0.25 0.50 e L 0.40 1.27 L 0.45 0.75 α 0° 8° α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-012 4.30 4.50 0.65 BASIC Reference Document: JEDEC Publication 95, MO-153 83026BMI-01 www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 16, 2006 ICS83026I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83026BMI-01 3026BI01 8 lead SOIC tube -40°C to 85°C ICS83026BMI-01T 3026BI01 8 lead SOIC 2500 tape & reel -40°C to 85°C ICS83026BMI-01LF 026BI01L 8 lead "Lead-Free" SOIC tube -40°C to 85°C ICS83026BMI-01LFT 026BI01L 8 lead "Lead-Free" SOIC 2500 tape & reel -40°C to 85°C ICS83026BGI-01 26B01 8 lead TSSOP tube -40°C to 85°C ICS83026BGI-01T 26B01 8 lead TSSOP 2500 tape & reel -40°C to 85°C ICS83026BGI-01LF TBD 8 lead "Lead-Free" TSSOP tube -40°C to 85°C ICS83026BGI-01LFT TBD 8 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83026BMI-01 www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 16, 2006 Integrated Circuit Systems, Inc. ICS83026I-01 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table A T7 A A T3C A T7 83026BMI-01 Page 1 3 11 12 13 6 Description of Change Added 8 Lead TSSOP package to Pin Assignment. Absolute Maximum Ratings - added 8 Lead TSSOP to Package Thermal Impedance. Added 8 Lead TSSOP Reliability Information table. Added 8 Lead TSSOP Package Outline and Package Dimensions. Ordering Information Table - added 8 Lead TSSOP ordering information. Additive Phase Jitter - corrected X axis on plot. 3 1 9 13 LVCMOS DC Characteristics - corrected Test Conditions for IIH and IIL. Features Section - added lead-free bullet Added Recommendations for Unused Output Pins. Ordering Information Table - added lead-free par t number, marking, and note. www.icst.com/products/hiperclocks.html 14 Date 6/25/04 8/2/05 8/12/05 1/16/06 REV. A JANUARY 16, 2006