Austin AS5SP1M36DQR-200/IT 36mb pipelined sync sram Datasheet

SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FIGURE 1: PIN ASSIGNMENT
(Top View)
36Mb Pipelined Sync SRAM
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
FEATURES
• Supports bus operation up to 200 MHz
• Available speed grades are 200 and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O power supply
• Fast clock-to-output times
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
• Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-pin TQFP package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
MARKING
/XT
/IT
/ET
SELECTION GUIDE
MaximumAccessTime
MaximumOperatingCurrent
MaximumCMOSStandbyCurrent
AS5SP1M36DQ
CY7C1440AV33
(1Mx36)
(1M x 36)
200MHz
3.2
425
120
166MH
3.4
375
120
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Temperature Range
Military Temp (-55oC to +125oC)
Industrial (-40oC to +85oC)
Enhanced (-40oC to +105oC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
50
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
OPTION
AS5SP1M36DQ
Unit
ns
mA
mA
GENERAL DESCRIPTION
The AS5SP1M36DQ SRAM integrates 1M x 36/2M x 18 and
512K x 72 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK).
The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depthexpansion Chip Enables (CE2 and CE3), Burst Control
inputs (ADSC, ADSP, and ADV), Write Enables (BWX
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge
of clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
AS5SP1M36DQ
Rev. 1.2 4/09
burst addresses can be internally generated as controlled
by the Advance pin (ADV).
Address, data inputs, and write controls are registered onchip to initiate a self-timed Write cycle.This part supports
Byte Write operations (see Pin Descriptions and Truth
Table for further details). Write cycles can be one to two or
four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The AS5SP1M36DQ operates from a +3.3V core power
supply while all outputs may operate with either a +2.5 or
+3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
LOGIC BLOCK DIAGRAM
A0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
GW
CE1
CE2
CE3
OE
ZZ
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
BWA
BWE
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
PIN DEFINITIONS
I/O
Description
A0, A1, A
Name
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active.
A1: A0 are fed to the two-bit counter.
BWA,
BWC,
BWE,
BWG,
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BWX and
BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
SSRAM
AS5SP1M36DQ
PIN DEFINITIONS (continued)
Name
I/O
Description
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not
connected for BGA. Where referenced, CE3 is assumed active throughout this document
for BGA. CE3 is sampled only when a new external address is loaded.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
InputAsynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPX
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
Power supply inputs to the core of the device.
VDD
Power Supply
VSS
Ground
VSSQ
I/O Ground
VDDQ
MODE
TDO
Ground for the core of the device.
Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
JTAGClock
NC
–
NC/72M
AS5SP1M36DQ
Rev. 1.2 4/09
–
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die
No Connects. Not internally connected to thedie. NC/72M are address expansion pins &
are not internally connected to the die.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
SSRAM
AS5SP1M36DQ
FUNCTIONAL OVERVIEW
All synchronous inputs pass through input registers
controlled by the rising edge of the clock. All data outputs
pass through output registers controlled by the rising edge
of the clock. Maximum access delay from the clock rise (tCO)
is 3.2ns (200-MHz device).
The AS5SP1M36DQ supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486∀!
processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst
order is user selectable, and is determined by sampling the
MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a
burst sequence and automatically increments the address
for the rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data
to all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
Address Register while being presented to the memory array.
The corresponding data is allowed to propagate to the input
of the Output Registers. At the rising edge of the next clock
the data is allowed to propagate through the output register
and onto the data bus within 3.2ns (200-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always tri-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will tri-state immediately.
AS5SP1M36DQ
Rev. 1.2 4/09
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
The Write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise,
the data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW
is HIGH, then the Write operation is controlled by BWE and
BWX signals.
The AS5SP1M36DQ provides Byte Write capability that is
described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BWX) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because AS5SP1M36DQ is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting
data to the DQs inputs.Doing so will tri-state the output drivers.
As a safety precaution, DQs are utomatically tri-stated
whenever a Write cycle is detected, regardless of the state of
OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following
conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP
is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BWX) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because AS5SP1M36DQ is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting
data to the DQs inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQs are automatically tri-stated
whenever a Write cycle is detected, regardless of the state of
OE.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
FUNCTIONAL OVERVIEW (continued)
Burst Sequences
The AS5SP1M36DQ provides a two-bit wraparound counter,
fed by A1: A0, that implements either an interleaved or linear
burst sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow
a linear burst sequence. The burst sequence is user
selectable through the MODE input. Asserting ADV LOW at
clock rise will automatically
increment the burst counter to the next address in the
burst sequence. Both Read and Write burst operations are
supported.
InterleavedBurstAddressTable
(MODE=FloatingorVDD)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
00
11
10
Third
Address
A1:A0
10
11
00
01
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
LinearBurstAddressTable
(MODE=GND)
First
Second
Third
Address Address Address
A1:A0
A1:A0
A1:A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1:A0
11
10
01
00
ZZModeElectricalCharacteristics
Parameter
Description
IDDZZ
Sleepmodestandbycurrent
TestConditions
ZZшVDDͲ0.2V
tZZS
DeviceoperationtoZZ
ZZшVDDͲ0.2V
tZZREC
ZZrecoverytimes
ZZч0.2V
Max
Unit
mA
2tCYC
ns
2tCYC
tZZI
ZZactivetosleepcurrent
Thisparameterissamples
tRZZI
ZZinactivetoexitsleepcurrent
Thisparameterissamples
AS5SP1M36DQ
Rev. 1.2 4/09
Min
Fourth
Address
A1:A0
11
10
01
00
ns
2tCYC
0
ns
ns
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
SSRAM
AS5SP1M36DQ
[2,3,4,5,6,7]
TruthTable
Operation
DeselectCycle,PowerDown
DeselectCycle,PowerDown
DeselectCycle,PowerDown
DeselectCycle,PowerDown
DeselectCycle,PowerDown
SleepMode,PowerDown
READCycle,BeginBurst
READCycle,BeginBurst
WRITECycle,BeginBurst
READCycle,BeginBurst
READCycle,BeginBurst
READCycle,ContinueBurst
READCycle,ContinueBurst
READCycle,ContinueBurst
READCycle,ContinueBurst
WRITECycle,ContinueBurst
WRITECycle,ContinueBurst
READCycle,SuspendBurst
READCycle,SuspendBurst
READCycle,SuspendBurst
READCycle,SuspendBurst
WRITECycle,SuspendBurst
WRITECycle,SuspendBurst
Add.Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE1\ CE2 CE3\
H
X
X
L
L
X
L
X
H
L
L
X
L
X
H
X
X
X
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
X
X
X
X
X
X
H
X
X
H
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
H
X
X
X
X
X
H
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK
DQ
X
L
X
X
X
LͲH TRIͲSTATE
L
X
X
X
X
LͲH TRIͲSTATE
L
X
X
X
X
LͲH TRIͲSTATE
H
L
X
X
X
LͲH TRIͲSTATE
H
L
X
X
X
LͲH TRIͲSTATE
X
X
X
X
X
X TRIͲSTATE
Q
L
X
X
X
L
LͲH
L
X
X
X
H
LͲH TRIͲSTATE
H
L
X
L
X
LͲH
D
Q
H
L
X
H
L
LͲH
H
L
X
H
H
LͲH TRIͲSTATE
Q
H
H
L
H
L
LͲH
H
H
L
H
H
LͲH TRIͲSTATE
Q
X
H
L
H
L
LͲH
X
H
L
H
H
LͲH TRIͲSTATE
H
H
L
L
X
LͲH
D
C
H
L
L
X
LͲH
D
Q
H
H
H
H
L
LͲH
H
H
H
H
H
LͲH TRIͲSTATE
Q
X
H
H
H
L
LͲH
X
H
H
H
H
LͲH TRIͲSTATE
H
H
H
L
X
LͲH
D
X
H
H
L
X
LͲH
D
Notes:
2.X=Don'tCare,H=LogicHIGH,L=LogicLOW
3.WRITE\=LwhenanyoneormoreByteWriteenablesignalsandBWE\=LorGW\=L.WRITE\=HwhenallBytewriteenablesignals,BWE\,GW\=H.
4.TheDQpinsarecontrolledbythecurrentcycleandtheOEsignal.OEisasynchronousandisnotsampleswiththeclock.
5.CE1\,CE2,CE3\areavailableonlyintheTQFPpackage.BGApackagehasonly2chipselectsCE1\andCE2.
6.TheSRAMalwaysinitiatesareadcyclewhenADSP\isasserted,regardlessofthestateofGW\,BWE\,orBWX\.Writesmayoccuronlyonsubsequentclocks
aftertheADSP\orwiththeassertionofADSC\.Asaresult,OE\mustbedrivenHIGHpriortothestartofthewritecycletoallowtheoutputstotriͲstate.OE\
isadon'tcarefortheremainderofthewritecycles.
7.OE\isasynchronousandisnotsampledwiththeclockrise.Itismaskedinternallyduringwritecycles.DuringareadcyclealldatabitsaretriͲstatewhenOE\
isinactiveorwhenthedeviceisdeselected,andalldatabitsbehaveasoutputwhenOE\isactive(LOW).
TruthTableforRead/Write[4,8,9]
Function
Read
Read
WriteByteAͲ(DQAandDQPA)
WriteByteBͲ(DQBandDQPB)
WriteBytesB,A
WriteByteCͲ(DQCandDQPC)
WriteBytesC,A
WriteBytesC,B
WriteBytesC,B,A
WriteByteDͲ(DQDandDQPD)
WriteBytesD,A
WriteBytesD,B
WriteBytesD,B,A
WriteBytesD,C
WriteBytesD,C,A
WriteBytesD,C,B
WriteAllBytes
WriteAllBytes
GW\
H
H
H
BWE\
H
L
L
BWD\
X
H
H
BWC\
X
H
H
BWB\
X
H
H
BWA\
X
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Notes:
8.BWX\representsanybytewritesignal.ToenableanybytewriteBWX\,aLogicLOWsignalshouldbe
appliedatclockrise.Anynumberofbytewritescanbeenabledatthesametimeforanygivenwrite.
9.Tableonlylistsapartiallistingofthebytewritecombinations.AnycombinationofBWX\isvalid.
Appropriatewritewillbedonebasedonwhichbytewriteisactive.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The AS5SP1M36DQ incorporates a serial boundary scan
test access port (TAP). This part is fully compliant with IEEE
Standard 1149.1. The TAP operates using JEDEC-standard
3.3V or 2.5V I/O logic levels. The AS5SP1M36DQ contains a
TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor.
TDO should be left unconnected. Upon power-up, the device
will come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
g
1
TEST-LOGIC
RESET
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
CAPTURE-DR
CAPTURE-IR
0
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by
the instruction that is loaded into the TAP instruction register.
TDI is internally pulled up and can be unconnected if the TAP
is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
0
SHIFT-DR
0
SHIFT-IR
1
0
TAP Controller Block Diagram
1
EXIT1-DR
1
EXIT1-IR
0
1
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
1
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from
the registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
0
0
Bypass Register
0
1
EXIT2-DR
0
2 1 0
EXIT2-IR
TDI
1
1
UPDATE-DR
1
AS5SP1M36DQ
0
Instruction Register
31 30 29 . . . 2 1 0
UPDATE-IR
1
Selection
Circuitry
Selection
Circuitr y
TDO
Identification Register
0
x . . . . . 2 1 0
Boundary Scan Register
The 0/1 next to each state represents the value of TMS at
the rising edge of TCK.
TCK
TMS
TAP CONTROLLER
Note: The JTAG feature is not tested. GBNT.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while the SRAM
is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls
and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI
ball on the rising edge of TCK. Data is output on the TDO ball
on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is placed
between the TDI and TDO balls as shown in the Tap
Controller Block Diagram. Upon power-up, the instruction
register is loaded with the IDCODE instruction. It is also
loaded with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it
is sometimes advantageous to skip certain chips. The
bypass register is a single-bit register that can be placed
between the TDI and TDO balls. This allows data to be shifted
through the SRAM with minimal delay. The bypass register is
set LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of
the RAM I/O ring when the TAP controller is in the CaptureDR state and is then placed between the TDI and TDO balls
when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can
be used to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
AS5SP1M36DQ
Rev. 1.2 4/09
SSRAM
AS5SP1M36DQ
during the Capture-DR state when the IDCODE command
is loaded in the instruction register. The IDCODE is
hardwired into the SRAM and can be shifted out when the
TAP controller is in the Shift-DR state. The ID register has a
vendor code and other information described in the
Identification Register Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five
instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO
balls. To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also places
the instruction register between the TDI and TDO balls and
allows the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction
register upon power-up or whenever the TAP controller is
given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. The SAMPLE
Z command puts the output bus into a High-Z state until the
next command is given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
When the SAMPLE/PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can
only operate at a frequency up to 20 MHz, while the SRAM
clock operates more than an order of magnitude faster.
Because there is a large difference in the clock frequencies,
it is possible that during the Capture-DR state, an input or
output will undergo a transition. The TAP may then try to
capture a signal while in transition (metastable state). This
will not harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not be
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
possible. To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal must
be stabilized long enough to meet the TAP controller’s capture
set-up plus hold times (tCS and tCH). The SRAM clock input
might not be captured correctly if there is no way in a design
to stop (or slow) the clock during a SAMPLE/PRELOAD
instruction. If this is an issue, it is still possible to capture all
other signals and simply ignore the value of the CK and CK
captured in the boundary scan register.
AS5SP1M36DQ
alsoselects the boundary scan register to be connected for
serial access between the TDI and TDO in the shift-DR
controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at, bit
#89 (for 165-FBGA package) or bit #138 (for 209-FBGA
package). When this scan cell, called the “extest output bus
tri-state”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control
the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable
the output buffers to drive the output bus. When LOW, this bit
will place the output bus into a High-Z condition.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction
Tap Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
AS5SP1M36DQ
Rev. 1.2 4/09
UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SSRAM
AUSTIN SEMICONDUCTOR, INC.
AS5SP1M36DQ
Austin Semiconductor, Inc.
TAPACSwitchingCharacteristicsOvertheoperatingrange
Parameter
Description
Clock
tTCYC
TCKClockCycleTime
tTF
TCKClockFrequency
tTH
TCKClockHIGHTime
Min
[10,11]
Max
50
Unit
ns
20
MHz
20
ns
TCKClockLOWTime
OutputTimes
tTDOV
TCKClockLOWtoTDOValid
20
ns
tTDOX
0
ns
SetͲupTimes
tTMSS
TMSSetͲuptoTCKClockRise
5
ns
tTDIS
TDISetͲuptoTCKClockRise
5
ns
tCS
CaptureSetͲupotoTCKRise
5
ns
HoldTimes
tTMSH
TMSHoldafterTCKClockRise
5
ns
tTDIH
TDIHoldafterClockRise
5
ns
tCH
CaptureHoldafterClockRise
5
ns
tTL
TCKClockLOWtoTDOInvalid
10
ns
3.3V TAP AC Test Conditions
2.5 TAP AC Test Conditions
Input pulse levels....................................Vss to 3.3V
Input rise and fall times.......................................1ns
Input timing reference levels...............................1.5V
Output reference levels......................................1.5V
Test load termination supply voltage ...................1.5V
Input pulse levels....................................Vss to 2.5V
Input rise and fall times.......................................1ns
Input timing reference levels..............................1.25V
Output reference levels.....................................1.25V
Test load termination supply voltage .................1.25V
3.3V TAP AC Output Load Equivalent
2.5 TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO = 50Ω
ZO = 50Ω
20pF
20pF
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
TAODCElectricalCharacteristicsandOperatingConditons
0oC<TA<+70oC;VDD=3.135to3.6Vunlessotherwisenoted) [12]
Parameter
Description
TestConditions
IOH=Ͳ4.0mA,VDDQ=3.3V
Min
2.4
IOH=Ͳ1.0mA,VDDQ=2.5V
2.0
V
VDDQ=3.3V
2.9
V
VDDQ=2.5V
2.1
V
VOH1
OutputHIGHVoltage
VOH2
OutputHIGHVoltage IOH=Ͳ100μA
VOL1
OutputLOWVoltage
VOL2
OutputLOWVoltage IOH=100μA
VIH
InputHIGHVoltage
VIL
InputLOWVoltage
IX
InputLoadCurrent
Max
Unit
V
IOL=8.0mA
VDDQ=3.3V
0.4
V
IOL=1.0mA
VDDQ=2.5V
0.4
V
VDDQ=3.3V
0.2
V
VDDQ=2.5V
0.2
V
VDDQ=3.3V
2.0
VDD+0.3
V
VDDQ=2.5V
1.7
VDD+0.3
V
VDDQ=3.3V
Ͳ0.3
0.8
V
VDDQ=2.5V
Ͳ0.3
Ͳ5
0.7
5
V
μA
GNDчVINчVDDQ
IdentificationRegisterDefinitions
InstructionField
RevisionNumber(31:29)
DeviceDepth(28:24)[13]
Architecture/MemoryType(23:18)
BusWidth/Density(17:12)
JEDECIDCode(11:1) +
IDRegisterPresenceIndicator(0)
1Mx36
000
01011
000000
100111
00000110100
1
Description
Describestheversionnumber
ReservedforInternalUse
Definesmemorytypeandarchitecture
Defineswidthanddensity
AllowsuniqueidentificationofSRAMvendor
IndicatesthepresenceofanIDregister
ScanRegisterSizes
RegisterName
Instruction
Bypass
ID
BitSize(x36)
3
1
32
Notes:
12. All voltages referenced to VSS (GND).
13. Bit #24 is '1' in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
+
Austin Semiconductor uses Cypress die so this code reflects Cypress.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
SSRAM
AS5SP1M36DQ
IdentificationCodes
Instruction
EXTEST
IDCODE
SAMPLEZ
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Code
000
001
010
011
100
101
110
111
Description
CapturestheI/Oringcontents.
LoadstheIDregisterwiththevendorIDcodeandplacestheregisterbetweenTDIandTDO.
ThisoperationdoesnotaffectSRAMoperations.
CapturesI/Oringcontents.PlacestheboundaryscanregisterbetweenTDIandTDO.Forcesall
SRAMoutputdriverstoaHighͲZstate.
Donotuse:Thisinstructionisreservedforfutureuse.
CapturesI/Oringcontents.PlacestheboundaryscanregisterbetweenTDIandTDO.Doesnot
affectSRAMoperation.
Donotuse:Thisinstructionisreservedforfutureuse.
Donotuse:Thisinstructionisreservedforfutureuse.
PlacesthebypassregisterbetweenTDIandTDO.ThisoperationdoesnotaffectSRAM
operations.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .....................................–65°C to +150°C
Ambient Temperature with
Power Applied..................................................–55°C to +125°C
Supply Voltage on VDD Relative to GND.......... –0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND ........ –0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State.................................................. –0.5V to VDDQ + 0.5V
DC Input Voltage ........................................ –0.5V to VDD + 0.5V
Current into Outputs (LOW)............................................. 20 mA
Static Discharge Voltage............................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current........................................................... > 200 mA
OperatingRange
Range
Commercial
Ambient
Temperature
0oCto+70oC
Industrial
Ͳ40oCto+85oC
Enhanced
Ͳ40oCto+105oC
Military
Ͳ55oCto+125oC
AS5SP1M36DQ
Rev. 1.2 4/09
VDD
VDDQ
3.3VͲ5%/+10%
2.5VͲ5%toVDD
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
ElectricalCharacteristicsOvertheOperatingRange[17,18]
DCElectricalCharacteristicsOvertheOperatingRange
Parameter
Description
VDD
PowerSupplyVoltage
VDDQ
VOH
I/OSupplyVoltage
OutputHIGHVoltage
TestConditions
Min
3.135
Max
3.6
Unit
V
for3.3VI/O
3.135
VDD
V
for2.5VI/O
for3.3VI/O,IOH=Ͳ4.0mA
2.375
2.4
2.625
V
V
for2.5VI/O,IOH=Ͳ1.0ma
2.0
0.4
V
for2.5VI/O,IOH=1.0ma
0.4
V
2.0
VDD+0.3V
V
for2.5VI/O
1.7
VDD+0.3V
V
Ͳ0.3
Ͳ0.3
0.8
0.7
V
V
5
VOL
OutputLOWVoltage
VIH
InputHIGHVoltage[17]
VIL
InputLOWVoltage[17]
for3.3VI/O
for2.5VI/O
InputLeakageCurrent
exceptZZandMODE
GNDчV1чVDDQ
Ͳ5
Input=VSS
Ͳ30
IX
InputCurrentofMODE
InputCurrentofZZ
Ioz
OutputLeakCurrent
IDD
VDDOperatingSupply
Current
V
for3.3VI/O,IOH=8.0mA
for3.3VI/O
Input=VDD
μA
5
Input=VSS
Ͳ5
Input=VDD
GNDчV1чVDDQ,OutputDisabled
Ͳ5
μA
μA
μA
30
5
μA
μA
VDD=Max,IOUT=0mA,
5Ͳnscycle,200MHz
425
mA
f=fMAX=1/tCYC
6Ͳnscycle,167MHz
375
mA
AllSpeeds
225
mA
AllSpeeds
120
mA
AllSpeeds
200
mA
AllSpeeds
135
mA
AutomaticCE VDD=Max,DeviceDeselected
ISB1
ISB2
ISB3
ISB4
PowerDownCurrentͲVINшVIHorVINчVIL
TTLInputs
f=fMAX=1/tCYC
AutomaticCE VDD=Max,DeviceDeselected
PowerDownCurrentͲVINч0.3VorVINшVDDQͲ0.3V,
CMOSInputs
f=0
AutomaticCE VDD=Max,DeviceDeselected
PowerDownCurrentͲVINч0.3VorVINшVDDQͲ0.3V,
CMOSInputs
f=fMAX=1/tCYC
AutomaticCE VDD=Max,DeviceDeselected
PowerDownCurrentͲVINшVIHorVINчVIL,f=0
TTLInputs
Notes:
17.Overshoot:VIH(AC)<VDD+1.5V(PulsewidthlessthanTCYC/2),undershoot:VIL(AC)>Ͳ2V(PulsewidthlessthantCYC/2)
18.TpowerͲup:Assumesalinearrampfrom0VtoVDD(min)within200ms.DuringthistimeVIH<VDDandVDDQчVDD.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
SSRAM
AUSTIN SEMICONDUCTOR, INC.
AS5SP1M36DQ
Austin Semiconductor, Inc.
Capacitance[19]
Parameter
CIN
Description
InputCapacitance
CCLK
ClockInputCapacitance
CI/O
Input/OutputCapacitance
100TQFP
Max.
TestConditions
TA=25oC,f=1MHz,
6.5
Unit
pF
VDD=3.3V
3
pF
VDDQ=2.5V
5.5
pF
ThermalResistance[19]
Parameter
ȺJA
ȺJC
Description
ThermalResistance
(JunctiontoAmbient)
ThermalResistance
(JunctiontoCase)
100TQFP
Package
TestConditions
Testconditionsfollowstandardtestmethods
andproceduresformeasuringthermal
impedance,perEIA/JESD51
Unit
25.21
o
2.28
o
C/W
C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
3.3V
OUTPUT
R = 317:
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50:
Z0 = 50:
VT = 1.5V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
GND
R = 351:
d 1ns
d 1ns
(b)
(c)
2.5V I/O Test Load
2.5V
OUTPUT
R = 1667:
VT = 1.25V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50:
Z0 = 50:
10%
90%
10%
90%
GND
R = 1538:
(b)
d 1ns
d 1ns
(c)
Note:
19. Tested initially and after any design or process change that may affect these parameters.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
[24,25]
SwitchingCharacteristicsOvertheOperatingRange
Ͳ200
Parameter
tPOWER
Clock
tCYC
Description[20]
[20]
VDD(Typical)tothefirstaccess
Min
1
Min
1
Max
Unit
ms
5
6
ns
2.0
2.4
ns
tCL
ClockLOW
OutputTimes
tCO
DataOutputValidAfterCLKRise
2.0
2.4
ns
tDOH
1.5
1.5
ns
1.3
1.5
ns
tCH
tCLZ
ClockCycleTime
Ͳ166
Max
ClockHIGH
3.2
DataOutputHoldAfterCLKRise
ClocktoLowͲZ[21,22,23]
[21,22,23]
3.4
ns
tCHZ
ClocktoHighͲZ
3.0
3.4
ns
tOEV
OE\LOWtoOutputValid
OE\LOWtoOutputLowͲZ[21,22,23]
3.0
3.4
ns
tOELZ
0
[21,22,23]
0
ns
OE\HIGHtoOutputLowͲZ
tOEHZ
SetͲUpTimes
tAS
AddressSetͲupBeforeCLKRise
1.4
1.5
ns
tADS
ADSC\,ADSP\SetͲupBeforeCLKRise
1.4
1.5
ns
tADVS
ADV\SetͲupBeforeCLKRise
1.4
1.5
ns
tWES
GW\,BWE\BWx\SetͲupBeforeCLKRise
1.4
1.5
ns
tDS
DataInputSetͲupBeforeCLKRise
1.4
1.5
ns
tCES
HoldTimes
tAH
ChipEnableSetͲupBeforeCLKRise
1.4
1.5
ns
AddressHoldAfterCLKRise
0.4
0.5
ns
tADH
ADSP\,ADSC\HoldAfterCLKRise
0.4
0.5
ns
tADVH
ADV\HoldAfterCLKRise
0.4
0.5
ns
tWEH
GW\,BWE\BWx\SetͲupAfterCLKRise
0.4
0.5
ns
tDH
DataInputSetͲupAfterCLKRise
0.4
0.5
ns
tCEH
ChipEnableSetͲupAfterCLKRise
0.4
0.5
ns
3.0
3.4
ns
Notes:
20.Thisparthasavoltageregulatorinternally;tPOWERisthetimethatthepowerneedstobesuppliedaboveVDD(minimum)initiallybeforeareadorwrite
operationcanbeinitiated.
21.tCHZ,tCLZ,tOELZ,andtOEHZarespecifiedwithACtestconditionsshownin(b)ofACTestLoads.Transitionismeasured±200mVfromsteadyͲstatevoltage.
22.Atanygivenvoltageandtemperature,tOEHZislessthantOELZandtCHZislessthantCLZtoeliminatebuscontentionbetweenSRAMswhensharingthesame
databus.Thesespecificationsdonotimplyabuscontentioncondition,butreflectparametersguaranteedoverworstcaseuserconditions.Deviceisdesignedto
achieveHighͲZpriortoLowͲZunderthesamesystemconditions.
23.Thisparameterissampledandnot100%tested.
24.Timingreferencelevelis1.5VwhenVDDQ=3.3Vandis1.25VwhenVDDQ=2.5V.
25.Testconditionsshownin(a)ofACTestLoadsunlessotherwisenoted.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
Switching Waveforms
Read Cycle Timing[26]
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
ADDRESS
tAH
A1
A2
A3
Burst continued with
new base address
t WES tWEH
GW, BWE,
BWx
Deselect
cycle
t CES tCEH
CE
t ADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
Q(A1)
High-Z
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
Switching Waveforms (continued)
Write Cycle Timing[26, 27]
t CYC
CLK
t CH
t ADS
t CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BWX
t WES tWEH
GW
t CES tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
Switching Waveforms (continued)
Read/Write Cycle Timing[26, 28, 29]
t CYC
CLK
t CL
t CH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
t WES tWEH
BWE,
BWX
t CES tCEH
CE
ADV
OE
t DS t DH
tCO
t OELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
Switching Waveforms (continued)
ZZ Mode Timing[30, 31]
CLK
t ZZ
t ZZREC
ZZ
t ZZI
I
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
SSRAM
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
AS5SP1M36DQ
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
0.10
1.60 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
R 0.08 MIN.
0.20 MAX.
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
AS5SP1M36DQ
Rev. 1.2 4/09
A
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
SSRAM
AS5SP1M36DQ
ORDERINGINFORMATION
PartNumber
Configuration
o
o
Industrial(Ͳ40 Cto+85 C)
AS5SP1M36DQͲ167/IT
1Mx36PipelinedSynchSRAM
AS5SP1M36DQͲ200/IT
1Mx36PipelinedSynchSRAM
o
o
Enhanced(Ͳ40 Cto+105 C)
AS5SP1M36DQͲ167/ET
1Mx36PipelinedSynchSRAM
AS5SP1M36DQͲ200/ET
1Mx36PipelinedSynchSRAM
o
o
MilitaryTemp(Ͳ55 Cto+125 C)
AS5SP1M36DQͲ167/XT
1Mx36PipelinedSynchSRAM
AS5SP1M36DQͲ200/XT
1Mx36PipelinedSynchSRAM
Speed(MHz)
Pkg.
167
200
100PinTQFP
100PinTQFP
167
200
100PinTQFP
100PinTQFP
167
200
100PinTQFP
100PinTQFP
Speed(MHz)
Pkg.
167
200
100PinTQFP
100PinTQFP
167
200
100PinTQFP
100PinTQFP
167
200
100PinTQFP
100PinTQFP
PBOPTION(WHEREAVAILABLE)
PartNumber
Configuration
o
o
Industrial(Ͳ40 Cto+85 C)
AS5SP1M36DQRͲ167/IT
1Mx36PipelinedSynchSRAM
AS5SP1M36DQRͲ200/IT
1Mx36PipelinedSynchSRAM
o
o
Enhanced(Ͳ40 Cto+105 C)
AS5SP1M36DQRͲ167/ET
1Mx36PipelinedSynchSRAM
AS5SP1M36DQRͲ200/ET
1Mx36PipelinedSynchSRAM
o
o
MilitaryTemp(Ͳ55 Cto+125 C)
AS5SP1M36DQRͲ167/XT
1Mx36PipelinedSynchSRAM
AS5SP1M36DQRͲ200/XT
1Mx36PipelinedSynchSRAM
Temperature Range
Military Temp (-55oC to +125oC)
Industrial (-40oC to +85oC)
Enhanced (-40oC to +105oC)
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
21
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
SSRAM
AS5SP1M36DQ
DOCUMENT TITLE
36Mb Pipelined Sync SRAM
REVISION HISTORY
Rev #
1.0
1.1
1.2
+
History
Datasheet Creation+
updated order chart
updated speeds (pg1, 15)
Release Date
January 2009
March 2009
April 2009
Status
Release
Release
Release
From baseline Cypress datasheet doc# 38-05383 Rev E
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22