Fairchild GTLP10B320 10-bit lvttl/gtlp transceiver with split lvttl port and feedback path Datasheet

Revised May 2001
GTLP10B320
10-Bit LVTTL/GTLP Transceiver
with Split LVTTL Port and Feedback Path
General Description
Features
The GTLP10B320 is a 10-bit Universal bus driver and
receiver, with separate LVTTL inputs and outputs and a
feedback path for diagnostics, that provides LVTTL to
GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing
(<1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the
Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
■ Bidirectional interface between GTLP and LVTTL logic
levels
Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output low level is typically less than 0.5V, the output level high is 1.5V and the
receiver threshold is 1.0V.
■ Variable edge rate control pin to select desired edge rate
on GTLP port (VERC)
■ VREF pin provides external supply reference voltage for
receiver threshold adjustibility
■ Split LVTTL inputs and outputs
■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
■ A feedback path for control and diagnostics monitoring
■ TTL compatible driver and control inputs
■ Designed using Fairchild advanced BiCMOS technology
■ Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
■ Power up/down and power off high impedance for live
insertion
■ Open drain on GTLP to support wired-or connection
■ Flow through pinout optimizes PCB layout
■ A Port source/sink −24mA/+24mA
■ B Port sink +50mA
Ordering Code:
Order Number
Package Number
Package Description
GTLP10B320MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500483
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GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
May 2001
GTLP10B320
Pin Descriptions
Pin Names
OEB, OEC
Connection Diagram
Description
B Port, C Port Output Enable
respectively (Active LOW)
VCC, GND, VREF Device Supplies
LECLKAB,
LECLKBC
A-to-B, B-to-C Latch CLK respectively
(Transparent Active HIGH)
SEL
Selects Internal Feedback Path
SAB, SBC
Selects Register or Latch/Transparent
Path for A-to-B and B-to-C respectively
B0-B9
B Port GTLP I/O
A0-A9
A Port LVTTL Inputs
C0-C9
C Port LVTTL Outputs
VERC
Edge Rate Control Pin
(GND = Slow Edge Rate)
(VCC = Fast Edge Rate)
Functional Description
The GTLP10B320 is a 10-bit Universal driver and receiver
containing D-Type flip-flop, latch, and transparent modes of
operation for the data paths. In addition there is an internal
feedback path that can be used for diagnostic monitoring or
caching schemes. Data flow in each direction is controlled
by the clock signals (LECLKAB and LECLKBC) and output
enables (OEB and OEC). The internal feedback path is
controlled by the SEL pin and allows data transfer from
Port A to Port C without requiring data to be output to the
backplane. The internal feedback path is selected with SEL
LOW and the B Port pin is selected with SEL HIGH. The
data paths can also be configured for latch/transparent or
register mode for each direction with the SAB and SBC
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pins. Data polarity is non-inverting with the GTLP outputs
enabled via the OEB pin and the LVTTL outputs being
enabled via the OEC pin.
For A-to-B data flow the device is configured into a latch/
transparent or register mode by pin SAB. If SAB is LOW
then the register mode is selected and the device operates
on the LOW-to-HIGH transition of LECLKAB. If SAB is
HIGH then the latch/transparent configuration is selected
and a HIGH-to-LOW transition of LECLKAB stores data in
the latch. If LECLKAB is HIGH the device is in transparent
mode. When OEB is LOW the outputs are active and when
OEB is HIGH the outputs are high impedance.
2
I/O Path: SEL = 1 (External Feedback Path) (Note 2)
Inputs
Outputs
OEB
OEC
SAB
SBC
LECLKAB LECLKBC
Mode
(AB)
An
0
1
0
X
↑
X
Register
L
X
L
0
1
0
X
↑
X
Register
H
X
H
0
1
0
X
L
X
Register
L
X
B0 (Note 1)
0
1
0
X
L
X
Register
H
X
B0 (Note 1)
L
Cn
Bn
0
1
1
X
↓
X
Latch
L
X
0
1
1
X
H
X
Buffer
L
X
L
0
1
1
X
↓
X
Latch
H
X
H
0
1
1
X
H
X
Buffer
H
X
H
1
1
X
X
X
X
High Impedance
X
X
Z
An
Bn
Note 1: Output level before the indicated steady state input conditions were established.
Note 2: The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used.
Internal Feedback Path: SEL = 0 (Internal Feedback Path) (Note 3)
Inputs
Outputs
LECLKAB LECLKBC
Mode
(AB/BC)
Cn
OEB
OEC
SAB
SBC
0
0
0
0
↑
↑
Register/Register
L
L
L
0
0
0
0
↑
↑
Register/Register
H
H
H
0
0
0
0
L
↑
Register/Register
X
0
0
0
0
↑
L
Register/Register
L
L
B0 (Note 4)
0
0
0
0
↑
L
Register/Register
H
H
B0 (Note 4)
0
0
0
0
L
L
Register/Register
X
B0 (Note 4) B0 (Note 4)
B0 (Note 4) B0 (Note 4)
0
0
0
1
↑
↓
Register/Latch
L
L
L
0
0
0
1
↑
H
Register/Buffer
L
L
L
0
0
0
1
↑
↓
Register/Latch
H
H
H
0
0
0
1
↑
H
Register/Buffer
H
H
H
0
0
0
1
L
↓
Register/Latch
X
B0 (Note 4) B0 (Note 4)
0
0
0
1
L
H
Register/Buffer
X
B0 (Note 4) B0 (Note 4)
0
0
0
1
L
L
Register/Latch
X
B0 (Note 4) B0 (Note 4)
0
0
1
0
↓
↑
Latch/Register
L
L
L
0
0
1
0
↓
↑
Latch/Register
H
H
H
0
0
1
0
↓
L
Latch/Register
L
L
B0 (Note 4)
0
0
1
0
↓
L
Latch/Register
H
H
B0 (Note 4)
0
0
1
0
H
↑
Buffer/Register
L
L
L
0
0
1
0
H
↑
Buffer/Register
H
H
H
0
0
1
0
L
L
Latch/Register
X
0
0
1
1
↓
↓
Latch/Latch
L
L
L
0
0
1
1
↓
↓
Latch/Latch
H
H
H
0
0
1
1
H
H
Buffer/Buffer
L
L
L
0
0
1
1
H
H
Buffer/Buffer
H
H
H
1
1
X
X
X
X
High Impedance
X
Z
Z
B0 (Note 4) B0 (Note 4)
Note 3: Function identical for SEL = 1 if timing requirements for propagation delay to output and set-up to LECLKBC are met at B Port.
Note 4: Output level before the indicated steady state input conditions were established.
3
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GTLP10B320
Functional Tables
GTLP10B320
Logic Diagram
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4
Supply Voltage (VCC)
−0.5V to +4.6V
DC Input Voltage (VI)
−0.5V to +4.6V
Recommended Operating
Conditions
Outputs 3-STATE
−0.5V to +4.6V
Outputs Active (Note 6)
−0.5V to +4.6V
Bus Termination Voltage (VTT)
DC Output Sink Current into
GTLP
1.47V to 1.53V
VREF
0.98V to 1.02V
Input Voltage (VI)
C Port IOL
48 mA
on A Port and Control Pins
DC Output Source Current from
−48 mA
C Port IOH
0.0V to VCC
HIGH Level Output Current (IOH)
−24 mA
C Port
DC Output Sink Current into
LOW Level Output Current (IOL)
100 mA
B Port in the LOW State, IOL
+24 mA
C Port
DC Input Diode Current (IIK)
+50 mA
B Port
VI < 0V
−50 mA
VO < 0V
Note 5: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum rating. The
“Recommended Operating Conditions” table will define the conditions for
actual device operation.
−50 mA
>2000V
ESD Rating
−40°C to +85°C
Operating Temperature (TA)
DC Output Diode Current (IOK)
Storage Temperature (TSTG)
3.15V to 3.45V
Supply Voltage VCC
DC Output Voltage (VO)
−65°C to +150°C
Note 6: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Symbol
VIH
VIL
Min
Test Conditions
Typ
Max
Units
(Note 7)
B Port
VREF + 0.05
Others
2.0
B Port
0.0
VTT
VREF − 0.05
Others
0.8
V
V
VREF
B Port
0.7
1.0
1.3
VTT
B Port
VREF + 50 mV
1.5
VCC
V
−1.2
V
VIK
VOH
VOL
C Port
C Port
B Port
II
Control Pins
VCC = 3.15V
II = −18 mA
VCC = Min to Max (Note 8)
IOH = −100 µA
VCC = 3.15V
IOH = −8 mA
2.4
IOH = -24mA
2.2
IOFF
V
IOL = 100 µA
0.2
VCC = 3.15V
IOL = 8 mA
0.4
IOL = 24 mA
0.5
IOL = 40 mA
0.4
IOL = 50 mA
0.5
VCC = 3.45V
and A Port
B Port
VCC –0.2
VCC = Min to Max (Note 8)
VCC = 3.15V
VCC = 3.45V
A or C Ports, VCC = 0
V
VI = 3.45V
10
VI = 0V
−10
V
V
µA
VI = VTT
5
VI = 0
−5
VI or VO = 0 to 3.45V
30
µA
30
µA
µA
Control Pins
II (HOLD)
IOZH
B Port
VCC = 0
VI or VO = 0 to 1.5V
A Port
VCC = 3.15V
VI = 0.8V
C Port
VCC = 3.45V
B Port
IOZL
C Port
VCC = 3.45V
B Port
IPU/PD
All Ports
VCC = 0 to 1.5V
75
VI = 2.0V
−75
VO = 3.45V
10
VO = 1.5V
5
VO = 0V
−10
VO = 0.55V
−5
VI = 0 to 3.45V
30
5
µA
µA
µA
µA
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GTLP10B320
Absolute Maximum Ratings(Note 5)
GTLP10B320
DC Electrical Characteristics
Symbol
ICC
(Continued)
Min
Test Conditions
Max
A or B Ports
VCC = 3.45V
Outputs HIGH
27
45
or C Port
IO = 0
Outputs LOW
27
45
VI = VCC/VTT or GND
Outputs Disabled
27
45
One Input at VCC
∆ICC
A Port and
VCC = 3.45V,
(Note 9)
Control Pins
A or Control Inputs at VCC or GND −0.6V
Ci
Typ
2
VI = VCC or 0
4.5
C Port
VI = VCC or 0
6
B Port
VI = VCC or 0
9
Control Pins
Units
(Note 7)
and A Port
mA
mA
pF
Note 7: All typical values are at VCC = 3.3V and TA = 25°C.
Note 8: For conditions shown as Min, use the appropriate value specified under recommended operating conditions.
Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Note: GTLP V REF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In
addition, VTT and RTERM can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50Ω, but must remain
within the boundaries of the DC Absolute Maximum Ratings. Similarly, VREF can be adjusted to optimize noise margin.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
Symbol
Test Conditions
fMAX
Maximum Clock Frequency
tWIDTH
Pulse Duration
tSET
Setup Time
tHOLD
Unit
MHz
ns
LECLKAB, LECLKBC HIGH or LOW
3.0
SAB = 0
A before LECLKAB↑
2.1
SBC = 0
B before LECLKBC↑
2.6
A before LECLKBC↑
6.8
SAB = 1, SEL = 0, SBC = 0
A before LECLKBC↑
3.0
SAB = 1
A before LECLKAB↓
1.7
SBC = 1
B before LECLKBC↓
2.2
SAB = 1, SEL = 1, SBC = 1
A before LECLKBC↓
6.4
SAB = 1, SEL = 0, SBC = 1
A before LECLKBC↓
2.8
SAB = 0
A after LECLKAB↑
2.0
SBC = 0
B after LECLKBC↑
1.6
SAB = 1, SEL = 1, SBC = 0
A after LECLKBC↑
−1.4
SAB = 1, SEL = 0, SBC = 0
A after LECLKBC↑
1.4
SAB = 1
A after LECLKAB↓
2.5
SBC = 1
B after LECLKBC↓
2.1
SAB = 1, SEL = 1, SBC = 1
A after LECLKBC↓
−1.0
SAB = 1, SEL = 0, SBC = 1
A after LECLKBC↓
1.6
6
Max
150
SAB = 1, SEL = 1, SBC = 0
Hold Time
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Min
ns
ns
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = GND. CL = 30 pF for B Port and CL = 50 pF for C Port.
Symbol
tPLH
From
To
(Input)
(Output)
An
Bn
LECLKAB
Bn
SAB = 1
tPHL
tPLH
LECLKAB
Bn
SAB = 0
tPHL
tPLH
Bn
Cn
SBC = 1
tPHL
tPLH
LECLKBC
Cn
SBC = 1
tPHL
tPLH
LECLKBC
Cn
An
Cn
SBC = 0
tPHL
tPLH
SEL = 1, SAB = 1, SBC = 1
tPHL
tPLH
An
LECLKAB
LECLKAB
LECLKAB
LECLKAB
Cn
SEL = 0, SAB = 0, SBC = 1
tPHL
tRISE
Cn
SEL = 1, SAB = 0, SBC = 1
tPHL
tPLH
Cn
SEL = 0, SAB = 1, SBC = 1
tPHL
tPLH
Cn
SEL = 1, SAB = 1, SBC = 1
tPHL
tPLH
Cn
SEL = 0, SAB = 1, SBC = 1
tPHL
tPLH
Typ
2.0
4.2
7.5
1.1
2.7
4.9
2.2
4.5
6.7
1.3
3.0
5.6
2.5
4.8
7.1
1.4
3.1
5.7
1.4
2.6
4.4
1.6
2.9
5.0
1.2
2.5
4.5
1.5
2.9
5.0
1.3
2.6
4.6
1.5
2.9
5.0
3.3
6.1
10.3
2.4
5.1
8.0
1.5
3.0
5.4
1.9
3.4
5.8
2.6
6.5
9.5
3.0
5.5
8.6
1.8
3.4
6.0
1.9
3.6
6.3
2.7
6.8
10.0
2.9
5.5
8.6
1.8
3.5
6.3
3.7
6.5
2.0
Transition Time, B Outputs (20% to 80%)
2.2
tFALL
Transition Time, B Outputs (80% to 20%)
1.8
tRISE
Transition Time, C Outputs (10% to 90%)
1.5
tFALL
Transition Time, C Outputs (90% to 10%)
tPLH
SEL
Cn
tPHL
tPZH, tPZL
OEB
Bn
tPHZ, tPLZ
tPZH, tPZL
OEC
Cn
tPHZ, tPLZ
Max
Unit
(Note 10)
SAB = 1
tPHL
tPLH
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.6
1.2
2.8
4.9
1.5
2.8
5.3
1.1
2.8
5.2
2.0
4.3
8.9
1.2
2.9
5.3
1.4
2.8
4.9
ns
ns
ns
Note 10: All typical values are at VCC = 3.3V, and TA = 25°C.
7
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GTLP10B320
AC Electrical Characteristics
GTLP10B320
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = GND. CL = 10 pF for B Port and CL = 10 pF for C Port.
Symbol
tPLH
From
To
(Input)
(Output)
An
Bn
LECLKAB
Bn
SAB = 1
tPHL
tPLH
LECLKAB
Bn
SAB = 0
tPHL
tPLH
Bn
Cn
SBC = 1
tPHL
tPLH
LECLKBC
Cn
SBC = 1
tPHL
tPLH
LECLKBC
Cn
An
Cn
SBC = 0
tPHL
tPLH
SEL = 1, SAB = 1, SBC = 1
tPHL
tPLH
An
tPLH
LECLKAB
LECLKAB
LECLKAB
LECLKAB
Cn
SEL = 0, SAB = 0, SBC = 1
tPHL
tRISE
Cn
SEL = 1, SAB = 0, SBC = 1
tPHL
tPLH
Cn
SEL = 0, SAB = 1, SBC = 1
tPHL
tPLH
Cn
SEL = 1, SAB = 1, SBC = 1
tPHL
tPLH
Cn
SEL = 0, SAB = 1, SBC = 1
tPHL
Typ
1.6
3.9
7.2
0.7
2.4
4.7
1.7
4.1
6.3
0.9
2.7
5.4
2.0
4.4
6.7
1.0
2.7
5.4
0.4
1.8
3.7
0.6
2.2
4.3
0.2
1.8
3.9
0.4
2.0
4.3
0.3
1.8
4.0
0.4
2.1
4.3
2.1
5.1
9.3
1.0
4.1
7.1
0.5
2.3
4.8
0.8
2.6
5.2
1.1
5.3
8.5
1.4
4.3
7.6
0.8
2.6
5.4
0.9
2.8
5.6
1.2
5.6
9.0
1.3
4.3
7.6
0.9
2.8
5.6
2.9
5.8
0.9
Transition Time, B Outputs (20% to 80%)
tFALL
Transition Time, B Outputs (80% to 20%)
1.8
Transition Time, C Outputs (10% to 90%)
0.6
tFALL
Transition Time, C Outputs (90% to 10%)
tPLH
SEL
tPHL
tPZH, tPZL
OEB
Bn
tPHZ, tPLZ
tPZH, tPZL
OEC
Cn
tPHZ, tPLZ
Note 11: All typical values are at VCC = 3.3V, and TA = 25°C.
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8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
tRISE
Cn
Max
(Note 11)
SAB = 1
tPHL
tPLH
Min
ns
0.7
0.3
1.7
4.3
0.4
2.3
4.6
0.8
2.5
4.8
1.6
4.0
8.5
0.6
2.0
4.0
0.6
1.9
3.7
ns
ns
ns
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = VCC. CL = 30 pF for B Port and CL = 50 pF for C Port.
Symbol
tPLH
From
To
(Input)
(Output)
An
Bn
Min
LECLKAB
3.3
7.3
0.8
2.3
4.5
1.4
3.7
6.0
1.0
2.6
5.1
1.6
3.9
6.3
1.1
2.7
5.2
1.6
5.3
8.1
2.0
4.7
7.5
1.7
5.7
8.8
2.2
5.1
8.1
Cn
1.8
5.9
9.1
SEL = 1, SAB = 0, SBC = 1
2.3
5.1
8.2
Bn
SAB = 1
tPHL
LECLKAB
tPLH
Bn
SAB = 0
tPHL
An
tPLH
Cn
SEL = 1, SAB = 1, SBC = 1
tPHL
tPLH
LECLKAB
Cn
SEL = 1, SAB = 1, SBC = 1
tPHL
tPLH
LECLKAB
tPHL
Max
1.2
SAB = 1
tPHL
tPLH
Typ
Unit
(Note 12)
tRISE
Transition Time, B Outputs (20% to 80%)
1.8
tFALL
Transition Time, B Outputs (80% to 20%)
1.4
tPZH, tPZL
OEB
Bn
tPHZ, tPLZ
ns
ns
ns
ns
ns
ns
ns
0.5
2.4
4.7
1.7
3.4
5.9
ns
Note 12: All typical values are at VCC = 3.3V, and TA = 25°C.
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted).
VERC = VCC. CL = 10 pF for B Port and CL = 10 pF for C Port.
Symbol
tPLH
From
To
(Input)
(Output)
An
Bn
LECLKAB
3.0
7.0
0.5
2.1
4.3
0.6
3.2
5.7
0.6
2.3
4.8
0.8
3.5
6.0
0.7
2.4
4.9
0.2
4.2
8.1
0.6
3.7
6.6
0.2
4.5
7.7
0.7
3.9
7.2
Cn
0.3
4.8
8.0
SEL = 1, SAB = 0, SBC = 1
0.8
3.9
7.2
Bn
SAB = 1
LECLKAB
Bn
SAB = 0
tPHL
tPLH
An
tPLH
LECLKAB
Cn
SEL = 1, SAB = 1, SBC = 1
tPHL
tPLH
Cn
SEL = 1, SAB = 1, SBC = 1
tPHL
LECLKAB
tPHL
Max
0.8
tPHL
tPLH
Typ
tRISE
Transition Time, B Outputs (20% to 80%)
1.4
tFALL
Transition Time, B Outputs (80% to 20%)
1.2
tPZH, tPZL
OEB
Bn
tPHZ, tPLZ
Unit
(Note 13)
SAB = 1
tPHL
tPLH
Min
ns
ns
ns
ns
ns
ns
ns
0.2
2.1
4.4
1.3
3.0
5.5
ns
Note 13: All typical values are at VCC = 3.3V, and TA = 25°C.
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GTLP10B320
AC Electrical Characteristics
GTLP10B320
AC Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free air temperature VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for C Port.
Symbol
tOSLH (Note 14)
Path
From
To
Mode
Max
A
Bn
B(n+1)
SAB = 1
0.5
A
Bn
B(n+1)
SAB = 1
2.0
LECLKAB
Bn
B(n+1)
SAB = 1
0.5
tOSHL (Note 14)
tPVHL (Note 15)(Note 16)
tOSLH (Note 14)
0.4
tOSHL (Note 14)
0.4
tPVHL (Note 15)(Note 16)
LECLKAB
Bn
B(n+1)
SAB = 1
2.0
tOSLH (Note 14)
LECLKAB
Bn
B(n+1)
SAB = 0
0.5
LECLKAB
Bn
B(n+1)
SAB = 0
2.0
B
Cn
C(n+1)
SBC = 1
0.4
tOSHL (Note 14)
tPVHL (Note 14)(Note 15)
tOSLH (Note 14)
0.4
tOSHL (Note 14)
0.4
Unit
ns
ns
ns
ns
ns
ns
ns
tOST (Note 14)
B
Cn
C(n+1)
SBC = 1
1.0
ns
tPV (Note 15)
B
Cn
C(n+1)
SBC = 1
1.5
ns
LECLKBC
Cn
C(n+1)
SBC = 1
0.4
tOSLH (Note 14)
tOSHL (Note 14)
0.4
ns
tOST (Note 14)
LECLKBC
Cn
C(n+1)
SBC = 1
1.0
ns
tPV (Note 15)
LECLKBC
Cn
C(n+1)
SBC = 1
1.5
ns
tOSLH (Note 14)
LECLKBC
Cn
C(n+1)
SBC = 0
0.4
tOSHL (Note 14)
0.4
ns
tOST (Note 14)
LECLKBC
Cn
C(n+1)
SBC = 0
1.0
ns
tPV (Note 15)
LECLKBC
Cn
C(n+1)
SBC = 0
1.5
ns
SEL
Cn
C(n+1)
tOSLH (Note 14)
tOSHL (Note 14)
0.4
0.4
ns
tOST (Note 14)
SEL
Cn
C(n+1)
1.0
ns
tPV (Note 15)
SEL
Cn
C(n+1)
1.2
ns
Note 14: tOSHL/tOSLH and tOST - Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs
within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same
direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and
statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the
device.
Note 15: tPV - Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device.
The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual
skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
Note 16: Due to the open drain structure on GTLP outputs tOST and t PV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the
VTT and RT values on the backplane.
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10
Test Circuit for A Outputs
Test
Test Circuit for B Outputs
S
tPLH/tPHL Open
tPLZ/tPZL
6V
Note B: For B Port, CL = 30 pF or 10 pF.
tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output.
Output Waveform 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output.
Input and Measure Conditions
A or LVTTL
Pins
B or GTLP
Pins
VinHIGH
VCC
1.5
VinLOW
0.0
0.0
VM
VCC/2
1.0
VX
VOL + 0.3V
N/A
VY
VOH − 0.3V
N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω
The outputs are measured one at a time with one transition per measurement.
11
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GTLP10B320
Test Circuits and Timing Waveforms
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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12