FAN6747 Highly Integrated Green-Mode PWM Controller Features Description High-Voltage JFET Startup Two-Level Over-Current Protection (OCP) with 220ms Delay The highly integrated FAN6747 PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to decrease the switching frequency with load condition. AC-Line Brownout Protection by HV Pin Constant Output Power Limit by HV Pin (Full AC-Line Range) Short-Circuit Protection (SCP) with 15ms Delay as Output Short Peak-Current Mode Operation with Cycle-by-Cycle Current Limiting Low Startup Current: 30µA PWM Frequency Decreasing at Green-Mode Low Operating Current: 1.7mA Over-Temperature Protection (OTP) with an External Negative-Temperature-Coefficient (NTC) Thermistor VDD Over-Voltage Protection (OVP) Internal Latch Circuit for OVP, OTP, SCP, and OCP Applications General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters AC/DC NB Adapters SMPS with Peak-Current Output, such as for Printers, Scanners, Motor Drivers Open-Frame SMPS Under zero-load condition, the power supply enters burst mode and burst frequency can be low to save more power. Green-mode function enables the power supply to meet international power conservation requirements. The FAN6747 is especially designed for SMPS with peak-current output. It incorporates a cycle-by-cycle current limiting and two-level Over-Current-Protection (OCP) that can handle peak load with a delay time. Once the current is over the threshold level, it triggers the first counter 15ms and checks if VDD is below 10V; if it is, the PWM latches off for SCP. If VDD is higher than 10V; it keeps counting to 220ms, then the PWM latches off for OCP. FAN6747 also integrates a frequency-hopping function internally to help reduce EMI emission of a power supply with minimum line filters. Built-in proprietary internal synchronized slope compensation achieves constant output power limit over universal AC line range. The gate output is clamped at 14V to protect the external MOSFET from over-voltage damage. Other protection functions include AC-line brownout protection with hysteresis and VDD over-voltage protection. For over-temperature protection, an external NTC thermistor can be applied to sense the ambient temperature. When OCP, OVP, SCP, or OTP is activated, an internal latch circuit latches off the controller. The latch is reset when the VDD supply is removed. Ordering Information Part Number Operating Temperature Range Eco Status FAN6747LMY -40 to +105°C Green Package 8-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, .15-Inch Narrow Body Packing Method Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 www.fairchildsemi.com FAN6747 — Highly Integrated Green-Mode PWM Controller January 2010 FAN6747 — Highly Integrated Green-Mode PWM Controller Application Diagram Figure 1. Typical Application Internal Block Diagram HV NC 4 3 SCP OVP OTP OCP Line Voltage Sample Circuit Latch Protection Brownout Protection 8 Vlimit Adjustment HV Start-up VDD Soft Driver 7 Internal BIAS UVLO Q S OSC Green Mode R 16.5V/9V 5.2V PWM Comparator 3R 2 Debounce OVP Soft-start Circuit VDD-OVP RT FB 1R Current Limit Comparator Slope Compensation Blanking Circuit SCP IRT GATE 6 SENSE VDD-SCP 5 Debounce1 1.05V SCP Delay OTP OCP Comparator OCP Delay OCP Debounce2 OLP Comparator 0.7V 4.6V GND Figure 2. Functional Block Diagram © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 www.fairchildsemi.com 2 FAN6747 — Highly Integrated Green-Mode PWM Controller Marking Information ZXYTT 6747F TPM : Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Die Run Code F: L = OCP latch T: Package Type (N =DIP, M = SOP) P: Y = Green Compound M: Manufacturing Flow Code Figure 3. Top Mark Pin Configuration Figure 4. Pin Assignments Pin Definitions Pin # Name 1 GND 2 FB Feedback. The output voltage feedback information from the external compensation circuit is fed into this pin. The PWM duty cycle is determined from this pin and the current-sense signal from Pin 6. 3 NC No Connection. HV High-Voltage Startup. This pin is connected to the line input via diodes and resistors to achieve brownout and high/low line compensation. Once the voltage of the HV pin is lower than the brownout voltage, PWM output is turned off. High/low line compensation dominates the OCP level and cycle-by-cycle current limit, to solves the unequal OCP level and power limit problem under universal input. 5 RT Over-Temperature Protection. For over-temperature protection, an external NTC thermistor is connected from this pin to GND. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below the threshold voltage, the controller latches off the PWM. 6 SENSE Current Sense. This pin is used to sense the MOSFET current for the current mode PWM and OCP. If the switching current is higher than OCP threshold and lasts 220ms, the controller latches off the PWM. 7 VDD Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external bulk capacitor of typically 10µF. The threshold voltages for startup and turn-off are 16.5V and 9V, respectively. The operating current is lower than 2mA. 8 GATE 4 Description Ground. This pin is used for the ground potential of all the pins. A 0.1µF decoupling capacitor placed between VDD and GND is recommended. Gate Driver Output. The totem-pole output driver for the power MOSFET. It is internally clamped below 14V. © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Parameter Min. DC Supply Voltage Max. Unit 30 V 640 V 7.0 V VHV Suddenly Input Voltage to HV Pin within 1 Second (Series connect with RHV) VL Input Voltage to FB, SENSE, RT Pin PD Power Dissipation (TA<50°C) 400 mW Thermal Resistance (Junction-to-Ambient) 141 °C/W ΘJA TJ TSTG TL ESD -0.3 Operating Junction Temperature -40 +125 °C Storage Temperature Range -55 +150 °C +260 °C Lead Temperature (Soldering, 10 Seconds) Electrostatic Discharge Capability, All Pins Except HV Pin Human Body Model, JESD22-A114 4.50 Charge Device Model, JESD22-C101 1.5 kV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to the network ground terminal. Recommended Operating Conditions FAN6747 — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter TA Operating Ambient Temperature VHV Input Voltage to HV Pin RHV HV Startup Resistor © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 Conditions Min. Typ. -40 150 200 Max. Unit +105 °C 500 V 250 kΩ www.fairchildsemi.com 4 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 24 V VDD Section VOP Continuously Operating Voltage VDD-ON Turn-On Threshold Voltage VDD-OFF PWM Turn-Off Threshold Voltage 15.5 16.5 17.5 V 8 9 10 V VDD-OLP Threshold Voltage on VDD for HV JFET Turn-On in Protection Condition 5.5 6.5 7.5 V VDD-LH Threshold Voltage on VDD Pin for Latch-Off Release Voltage 3.5 4.0 4.5 V VDD-AC Threshold Voltage on VDD Pin for Disable AC Recovery to Avoid Startup Failed VDD-OFF +2.5 VDD-OFF +3.0 VDD-OFF +3.5 V VDD-SCP Threshold Voltage on VDD Pin for VFB > VFBO Short-Circuit Protection (SCP) VDD-OFF +0.5 VDD-OFF +1.0 VDD-OFF +1.5 V 80 100 120 μA 30 μA 270 305 μA After Trigger OCP/ SCP/ OVP/ OTP Holding Current Under Latch-Off Conduction VDD=5V IDD-ST Startup Current VDD-ON – 0.16V IDD-OLP Holding Current at PWM-Off Phase VDD-OLP+0.1V IDD-OP1 Operating Supply Current when PWM Operating VDD=20V, VFB=3V Gate Open 1.7 2.0 mA IDD-OP2 Operating Supply Current when PWM Stop VDD=20V, VFB=3V Gate Open 1.2 1.5 mA VDD-OVP Threshold Voltage on VDD Pin for VDD Over-Voltage Protection (Latch-Off) 24 25 26 V 75 160 245 μs ILH tD-OVP VDD OVP Debounce Time VFB > VFB-N 235 FAN6747 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics Figure 5. UVLO Specification Continued on the following page… © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 www.fairchildsemi.com 5 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units Figure 6. Normal UVLO and Two-Step UVLO Behavior HV Section Supply Current Drawn from HV Pin VHV=120V, VDD=0V 1.50 2.75 4.00 mA VIN-OFF PWM Turn-Off Threshold DC Source Series R=200k to HV Pin 92 102 112 V VIN-ON PWM Turn-On Threshold DC Source Series R=200k to HV Pin 104 114 124 V Change in VIN, VIN-ON - VIN-OFF DC Source Series R=200k to HV Pin 6 12 18 V VFB > VFB-N 170 205 240 μs VFB < VFB-G 450 615 780 IHV ∆VIN tS-CYCLE tS-TIME tD_VIN-OFF Line Voltage Sample cycle Line Voltage Sample Period 20 PWM Turn-Off Debounce Time FAN6747 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics μs VFB > VFB-N 65 75 85 ms VFB < VFB-G 180 235 290 ms Figure 7. Brownout Circuit © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 www.fairchildsemi.com 6 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units Figure 8. Brownout Behavior FAN6747 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics Figure 9. VDD-AC and AC Recovery Oscillator Section fOSC Normal PWM Frequency Center Frequency (VFB>VFB-N) 61 65 69 kHz tJTR-1 Jitter Period 1 VFB > VFB-N 3.9 4.4 4.9 ms VFB=VFB-G 10.2 11.5 12.8 ms 19 22 25 kHz Pin, FB Voltage (VFB=VFB-N), fOSC – 5KHz 2.6 2.8 3.0 V Jitter Range ±3.7 ±4.2 ±4.7 kHz 2.1 2.3 2.5 V tJTR-3 Jitter Period 3 fOSC-G Green-Mode Minimum Frequency VFB-N FB Threshold Voltage for Frequency Reduction Beginning VFB-G FB Threshold Voltage for Turn-Off Pin, FB Voltage (VFB=VFB-G) Jitter and Frequency Reduction Destination Jitter Range © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 ±1.45 kHz www.fairchildsemi.com 7 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Conditions SG Slope for Green-Mode Modulation Min. Typ. Max. 85 Units Hz/mV- VOZ-ON FB Threshold Voltage for ZeroDuty Recovery 1.6 1.8 2.0 V VFB-ZDC (VOZ-OFF) FB Threshold Voltage for ZeroDuty 1.5 1.7 1.9 V VOZ-ON - VOZ-OFF FB Voltage Hysteresis for VOZ-ON to VOZ-OFF 50 100 150 mV fDV Frequency Variation vs. VDD Deviation VDD=12V to 22V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-40 to 105°C 5 % FAN6747 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics Figure 10. PWM Frequency Figure 11. Burst-Mode Diagram Feedback Input Section AV Input-Voltage to Current-Sense Attenuation ZFB VFBO VFB-OLP tD-OLP VFB < VFB-G 1/4.5 1/4.0 1/3.5 V/V Input Impedance 13.4 15.5 17.6 kΩ FB Pin Open Voltage 4.8 5.0 5.2 V FB Open-Loop Protection Threshold Voltage 4.3 4.6 4.9 V Open-Loop Protection Delay 190 215 240 ms © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 www.fairchildsemi.com 8 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 65 200 ns 230 270 310 ns Current Sense Section tPD Delay to Output tLEB Leading-Edge Blanking Time Vlimit-L Current Limit at Low Line (VAC-RMS=86V) VDC=122V, Series R=200kΩ to HV 0.790 0.825 0.860 V Vlimit-H Current Limit at High Line (VAC-RMS=259V) VDC=366V, Series R=200kΩ to HV 0.690 0.725 0.760 V VOCP-L OCP Trigger Level at Low Line (VAC-RMS=86V) VDC=122V, Series R=200kΩ to HV 0.450 0.480 0.510 V VOCP-H OCP Trigger Level at High Line (VAC=259V) VDC=366V, Series R=200kΩ to HV 0.390 0.420 0.450 V tSOFT-START Period During Startup Startup Time 7 8 9 ms tD-OCP Delay Time for Output OCP VCS>VOCP 190 215 240 ms tD-SCP Delay Time for Output SCP VCS>VOCP and VDD< VDD-SCP 12 15 18 ms 88.0 89.5 91.0 % 1.5 V PWM Output Section DCYMAX Maximum Duty Cycle VOL Output Voltage Low VDD = 15V, IO=50mA VOH Output Voltage High VDD = 12V, IO=50mA tR Rising Time GATE=1nF tF Falling Time GATE=1nF Gate Output Clamping Voltage VDD=22V VCLAMP 8 V 95 ns 30 FAN6747 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics ns 11.0 13.5 16.0 V 92 100 108 μA 1.00 1.05 1.10 V VFB > VFB-N 14 16 18 ms VFB < VFB-G 40 51 62 ms 0.65 0.70 0.75 V VFB > VFB-N 110 185 260 VFB < VFB-G 320 605 890 Over-Temperature Protection Section IRT VOTP-LATCH- Output Current of RT Pin OFF Threshold Voltage for OverTemperature Protection tD_OTP-LATCH Over-Temperature Latch-Off Debounce VOTP2-LATCHOFF tD_OTP2-LATCH Second Threshold Voltage for Over-Temperature Protection Second Over-Temperature Latch-Off Debounc © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 µs www.fairchildsemi.com 9 50 2.6 45 2.4 40 2.2 IDD-OP1 (mA) IDD-ST (μA) 35 30 25 20 15 2 1.8 1.6 1.4 10 1.2 5 0 1 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 Temperature (℃ ) 18 11 17.5 10.5 50 65 80 95 110 125 10 17 VDD-OFF (V) VDD-ON (V) 35 Figure 13. Operation Supply Current (IDD-OP1) vs. Temperature Figure 12. Startup Current (IDD-ST) vs. Temperature 16.5 16 9.5 9 8.5 15.5 8 15 7.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 14. Start Threshold Voltage (VDD-ON) vs. Temperature Figure 15. Minimum Operating Voltage (VDD-OFF) vs. Temperature 10 7 6 IHV-LC (uA) 8 IHV (mA) 20 Temperature (℃ ) FAN6747 — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics 6 4 2 5 4 3 2 0 1 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 Temperature (℃ ) 35 50 65 80 95 110 125 Temperature (℃ ) Figure 16. Supply Current Drawn from HV Pin (IHV) vs. Temperature Figure 17. HV Pin Leakage Current After Startup (IHV-LC) vs. Temperature 69 91 68 90.5 67 DCYMAX (%) fOSC (KHz) 66 65 64 63 62 61 90 89.5 89 88.5 60 59 88 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 Temperature (℃ ) -10 5 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 18. Frequency in Normal Mode (fOSC) vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 -25 Figure 19. Maximum Duty Cycle (DCYMAX) vs. Temperature www.fairchildsemi.com 10 6 300 285 270 255 5 tD-OLP (ms) VFB-OLP (V) 5.5 4.5 4 240 225 210 195 180 3.5 165 3 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 20. FB Open-Loop Trigger Level (VFB-OLP) vs. Temperature Figure 21. Delay Time of FB Pin Open-Loop Protection (tD-OLP) vs. Temperature 27 120 115 110 105 IRT (μA) VDD-OVP (V) 26 25 100 95 90 85 24 80 75 23 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 35 50 65 80 95 110 125 Figure 23. Output Current from RT Pin (IRT) vs. Temperature 1.2 0.9 1.1 0.8 VOTP2 (V) VOTP (V) Figure 22. VDD Over-Voltage Protection (VDD-OVP) vs. Temperature 1 0.9 0.7 0.6 0.8 0.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 122 120 VIN-OFF (V) 118 116 114 112 110 108 106 104 -25 -10 5 20 35 50 65 80 95 110 50 65 80 95 110 125 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 -40 125 Temperature (℃ ) -25 -10 5 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 26. Brown-In (VIN-ON) vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 35 Figure 25. Over-Temperature Protection Threshold Voltage (VOTP2) vs. Temperature 124 -40 20 Temperature (℃ ) Figure 24. Over-Temperature Protection Threshold Voltage (VOTP) vs. Temperature VIN-ON (V) 20 Temperature (℃ ) FAN6747 — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics Figure 27. Brownout (VIN-OFF) vs. Temperature www.fairchildsemi.com 11 Startup Current Short-Circuit Protection (SCP) For startup, the HV pin is connected to the line input through an external diode and resistor, RHV, (1N4007 / 200KΩ recommended). Peak startup current drawn from the HV pin is (VAC × 2 )/RHV and charges the hold-up capacitor through the diode and resistor. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6747 to maintain the VDD before the auxiliary winding of the main transformer provides the operating current. This protection is used to handle the huge output demand if the power supply output is suddenly shorted to ground. If VDD drops under 10V and the sensed voltage is higher than the limited threshold voltage, SCP is triggered and PWM output is latched off. This latch condition is reset only if VDD is discharged under 4V or by unplugging AC power line. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16.5V and 9V, respectively. During startup, the hold-up capacitor must be charged to 16.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 9V during startup. This UVLO hysteresis window ensures that the hold-up capacitor is adequate to supply VDD during startup. Operating Current Operating current is around 2mA. The low operating current enables better efficiency, power saving, and reduces the requirement of VDD hold-up capacitance. Green-Mode Operation The proprietary green-mode function provides off-time modulation to reduce the switching frequency in lightload and no-load conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and can not switch off the gate driver. Two-Level Over-Current Protection (OCP) The cycle-by-cycle current limiting shuts down the PWM immediately when the sense voltage is over the limited threshold voltage (0.825V at low line). Additionally, when the sense voltage is higher than the OCP threshold (0.48V at low line), the internal counter counts for 220ms, then latches off PWM. When OCP occurs, PWM output is turned off and VDD begins decreasing. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 13.5V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. When VDD goes below the turn-off threshold (~9V), the controller is totally shut down. VDD continues to discharge below VDD-OLP by IDD-OLP. Then VDD is charged up to the turn-on threshold voltage of 16.5V through the startup resistor. When VDD is charged to 16.5V, it cycles again. This phenomenon is called two-level UVLO. VDD Over-Voltage Protection (OVP) VDD over-voltage protection is built in to prevent damage due to abnormal conditions. If the VDD voltage is over the over-voltage protection voltage (VDD-OVP) and lasts for tD-OVP, the PWM pulses are disabled until the VDD voltage drops below 4V, then restarts again. Brownout and Constant Power Limited HV Pin Unlike previous PWM controllers, FAN6747’s HV pin isn’t only used for startup; it can also detect the AC line voltage to perform brownout function and set the current limit level. Through a fast diode and startup resistor to sample the AC line voltage, the peak value refreshes and stores in register at each sampling cycle. When internal update time is met, this peak value is used to for brownout and current-limit level judgment. Equations 1 and 2 can be used to calculate out the level of brown-in or brownout converted to RMS value. For power saving, FAN6747 enlarges the sampling cycle to lower the power loss from HV sampling at light-load condition. RHV + 1.6 )/ 2 1.6 R + 1 .6 VAC −OFF (RMS ) = (0.81× HV )/ 2 1.6 V AC −ON (RMS ) = (0.9 × © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 FAN6747 — Highly Integrated Green-Mode PWM Controller Operation Description Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. (1) (2) www.fairchildsemi.com 12 Over-Temperature Protection (OTP) The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6747 inserts a synchronized, positive-going, ramp at every switching cycle. A NTC thermistor, RNTC, in series with a resistor, RA, is connected from the RT pin to GND pin. A constant current IRT is output from this pin. The voltage of the RT pin can be expressed as VRT = IRT • (RNTC + RA), where IRT is 100µA, the headroom of VRT is limited at around 5V by internal circuitry. As high ambient temperatures occur, RNTC is smaller, such that the VRT decreases. When VRT is less than 1.05V(VOTP) but over 0.7V, the PWM turns off after tD_OTP-LATCH. The other threshold, VDD under 0.7V, is used for fast shut down of FAN6747 after a short time. Constant Output Power Limit When the SENSE voltage across sense resistor RS reaches the threshold voltage, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD • VIN / LP. Since the delay is nearly constant regardless of the input voltage VIN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a power-limiter is controlled by HV pin to solve the unequal power-limit problem. The power limiter is fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line input than at low-line input. © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 Noise Immunity Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN6747, and increasing the power MOS gate resistance improve performance. FAN6747 — Highly Integrated Green-Mode PWM Controller Built-In Slope Compensation www.fairchildsemi.com 13 5.00 4.80 A 0.65 3.81 8 5 B 6.20 5.80 1.75 4.00 3.80 1 PIN ONE INDICATOR 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 Figure 28. 8-Lead, Small Outline Integrated Circuit (SOIC) Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.0 www.fairchildsemi.com FAN6747 — Highly Integrated Green-Mode PWM Controller Physical Dimensions FAN6747 — Highly Integrated Green-Mode PWM Controller © 2009 Fairchild Semiconductor Corporation FAN6747 • Rev. 1.0.1 www.fairchildsemi.com 15