LINER LT1818 12-bit, 500ksps serial sampling adc in tsot Datasheet

LTC2312-12
12-Bit, 500ksps Serial
Sampling ADC in TSOT
Features
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Description
500ksps Throughput Rate
No Cycle Latency
Guaranteed 12-Bit No Missing Codes
Single 3V or 5V Supply
Low Noise: 73dB SNR
Low Power: 8mW at 500ksps and 3V Supply
Low Drift (20ppm/°C Maximum) 2.048V or 4.096V
Internal Reference
Sleep Mode with < 1µA Typical Supply Current
Nap Mode with Quick Wake-Up < 1 Conversion
Separate 1.8V to 5V Digital I/O Supply
High Speed SPI-Compatible Serial I/O
Guaranteed Operation from –40°C to 125°C
8-Lead TSOT-23 Package
Applications
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Communication Systems
High Speed Data Acquisition
Handheld Terminal Interface
Medical Imaging
Uninterrupted Power Supplies
Battery Operated Systems
Automotive
The LTC®2312-12 is a 12-bit, 500ksps, serial sampling
A/D converter that draws only 3mA from a single 3V or
5V supply. The LTC2312-12 contains an integrated low
drift reference and reference buffer providing a low cost,
high performance (20ppm/°C maximum) and space saving solution. The LTC2312-12 achieves outstanding AC
performance of 72.7dB SINAD and –84dB THD while
sampling at 500ksps. The extremely high sample rate-topower ratio makes the LTC2312-12 ideal for compact, low
power, high speed systems. The supply current decreases
at lower sampling rates as the device automatically enters
nap mode after conversions.
The LTC2312-12 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3V and 5V logic. The
fast 500ksps throughput with no-cycle latency makes
the LTC2312-12 ideally suited for a wide variety of high
speed applications.
Complete 14-/12-Bit Pin-Compatible SAR ADC Family
500ksps
2.5Msps
4.5Msps
14-Bit
LTC2312-14 LTC2313-14 LTC2314-14
12-Bit
LTC2312-12 LTC2313-12
5Msps
LTC2315-12
Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
16k Point FFT, fS = 500ksps, fIN = 259kHz
5V Supply, Internal Reference, 500ksps, 12-Bit Sampling ADC
2.2µF
LTC2312-12
VDD
–40
CONV
2.2µF
ANALOG INPUT
0V TO 4.096V
REF
SCK
GND
SDO
AIN
VDD = 5V
SNR = 73dBFS
SINAD = 72.7dBFS
THD = –84dB
SFDR = 88dB
–20
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
OVDD
2.2µF
DIGITAL OUTPUT SUPPLY
1.8V TO 5V
231212 TA01a
AMPLITUDE (dBFS)
5V
0
–60
–80
–100
–120
–140
–160
0
50
100
200
150
INPUT FREQUENCY (kHz)
250
231212 TA01b
231212fa
For more information www.linear.com/LTC2312-12
1
LTC2312-12
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
Supply Voltage (VDD, OVDD)........................................6V
Reference (REF) and Analog Input (AIN) Voltage
(Note 3).......................................(–0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 3).... (–0.3V) to (OVDD + 0.3V)
Digital Output Voltage.............. (–0.3V) to (OVDD + 0.3V)
Power Dissipation................................................100mW
Operating Temperature Range
LTC2312C................................................. 0°C to 70°C
LTC2312I...............................................–40°C to 85°C
LTC2312H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature Range (Soldering, 10 sec)......... 300°C
TOP VIEW
VDD
REF
GND
AIN
1
2
3
4
8
7
6
5
CONV
SCK
SDO
OVDD
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 195°C/W
Order Information
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2312CTS8-12#TRMPBF
LTC2312CTS8-12#TRPBF
LTFZM
8-Lead Plastic TSOT-23
0°C to 70°C
LTC2312ITS8-12#TRMPBF
LTC2312ITS8-12#TRPBF
LTFZM
8-Lead Plastic TSOT-23
LTC2312HTS8-12#TRMPBF
LTC2312HTS8-12#TRPBF
LTFZM
8-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
–40˚C to 85˚C
–40˚C to 125˚C
231212fa
For more information www.linear.com/LTC2312-12
LTC2312-12
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
VAIN
Absolute Input Range
VIN
Input Voltage Range
IIN
Analog Input DC Leakage Current
CIN
Analog Input Capacitance
CONDITIONS
(Note 11)
MIN
TYP
MAX
UNITS
l
–0.05
VDD + 0.05
V
l
0
VREF
V
l
–1
1
µA
Sample Mode
Hold Mode
13
3
pF
pF
Converter Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
Resolution
No Missing Codes
MIN
l
12
l
12
TYP
MAX
UNITS
Bits
Bits
Transition Noise
(Note 6)
0.33
LSBRMS
INL
Integral Linearity Error
VDD = 5V (Note 5)
VDD = 3V (Note 5)
l
l
–1.25
–1.5
±0.3
±0.4
1.25
1.5
LSB
LSB
DNL
Differential Linearity Error
VDD = 5V
VDD = 3V
l
l
–0.99
–0.99
±0.2
±0.25
0.99
0.99
LSB
LSB
Offset Error
VDD = 5V
VDD = 3V
l
l
–4
–7
±0.5
±1
4
7
LSB
LSB
Full-Scale Error
VDD = 5V
VDD = 3V
l
l
–8
–12
±1
±2
8
12
LSB
LSB
Total Unadjusted Error
VDD = 5V
VDD = 3V
l
l
–9
–14
±2
±3
9
14
LSB
LSB
Dynamic Accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 20kHz, VDD = 5V
fIN = 20kHz, VDD = 3V
SNR
Signal-to-Noise Ratio
THD
l
l
70
67
72.7
70.3
dB
dB
fIN = 20kHz, VDD = 5V
fIN = 20kHz, VDD = 3V
l
l
70.5
67.5
73
70.6
dB
dB
Total Harmonic Distortion
First 5 Harmonics
fIN = 20kHz, VDD = 5V
fIN = 20kHz, VDD = 3V
l
l
SFDR
Spurious Free Dynamic Range
fIN = 20kHz, VDD = 5V
fIN = 20kHz, VDD = 3V
l
l
IMD
Intermodulation Distortion
2nd Order Terms
3rd Order Terms
–84
–84
78
76
MAX
–76
–75
UNITS
dB
dB
87
87
dB
dB
fIN1 = 53kHz, fIN2 = 58kHz,
AIN1, AIN2 = –7dBFS
–80
–92
dBc
dBc
Full Power Bandwidth
At 3dB
At 0.1dB
130
20
MHz
MHz
–3dB Input Linear Bandwidth
SINAD ≥ 68dB
5
MHz
tAP
Aperture Delay
1
ns
tJITTER
Aperture Jitter
10
psRMS
231212fa
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3
LTC2312-12
Reference Input/Output
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
VREF
CONDITIONS
VREF Output Voltage
2.7V ≤ VDD ≤ 3.6V
4.75 ≤ VDD ≤ 5.25V
VREF Temperature Coefficient
l
l
MIN
TYP
MAX
UNITS
2.040
4.080
2.048
4.096
2.056
4.112
V
V
7
20
l
ppm/°C
VREF Output Resistance
Normal Operation, ILOAD = 0mA to 5mA
Overdrive Condition
(VREFIN ≥ VREFOUT + 50mV)
1
52
Ω
kΩ
VREF Line Regulation
2.7V ≤ VDD ≤ 3.6V
4.75 ≤ VDD ≤ 5.25V
0.4
0.2
mV/V
mV/V
4.15
V
VREF 2.048V/4.096V Supply Threshold
VREF 2.048V/4.096V Supply Threshold Hysteresis
VREF Input Voltage Range
(External Reference Input)
150
2.7V ≤ VDD ≤ 3.6V
4.75 ≤ VDD ≤ 5.25V
l
l
VREF + 50mV
VREF + 50mV
mV
V
V
VDD
4.3
Digital Inputs and Digital Outputs
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
l
–10
OVDD–0.2
CIN
Digital Input Capacitance
High Level Output Voltage
IO = –500µA (Source)
l
MAX
UNITS
0.8 • OVDD
VIN = 0V to OVDD
VOH
TYP
V
0.2 • OVDD
V
10
μA
5
VOL
Low Level Output Voltage
IO = 500µA (Sink)
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD, CONV = High
l
COZ
Hi-Z Output Capacitance
CONV = High
ISOURCE
Output Source Current
ISINK
Output Sink Current
pF
V
–10
0.2
V
10
µA
4
pF
VOUT = 0V, OVDD = 1.8V
–20
mA
VOUT = OVDD = 1.8V
20
mA
Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VDD
Supply Voltage
3V Operational Range
5V Operational Range
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
2.7
4.75
3
5
3.6
5.25
V
V
l
1.71
OVDD
Digital Output Supply Voltage
ITOTAL =
IVDD + IOVDD
Supply Current, Static Mode
Operational Mode
Nap Mode
Sleep Mode
CONV = 0V, SCK = 0V
l
l
PD
Power Dissipation, Static Mode
Operational Mode
Nap Mode
Sleep Mode
CONV = 0V, SCK = 0V
l
l
4
l
l
5.25
V
3.4
3
2
0.2
4.3
4
mA
mA
mA
µA
17
15
10
1
21.5
20
5
25
mW
mW
mW
µW
231212fa
For more information www.linear.com/LTC2312-12
LTC2312-12
ADC Timing Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX) Maximum Sampling Frequency
fSCK
Shift Clock Frequency
tSCK
Shift Clock Period
MIN
TYP
MAX
UNITS
(Notes 7, 8)
l
500
kHz
(Notes 7, 8)
l
20
MHz
l
tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV
50
ns
2000
l
ns
tCONV
Conversion Time
l
1400
ns
tACQ
Acquisition Time
l
600
ns
t1
Minimum CONV Pulse Width
(Note 7), Valid for Nap and Sleep Modes Only
l
10
ns
t2
SCK↑ Setup Time After CONV↓
(Note 7), Valid for Nap and Sleep Modes Only
l
10
t3
SDO Enable Time After CONV↓
(Notes 7, 8)
l
10
ns
t4
SDO Data Valid Access Time after SCK↓
(Notes 7, 8, 9)
l
11
ns
ns
t5
SCK Low Time
l
10
ns
t6
SCK High Time
l
10
ns
t7
SDO Data Valid Hold Time After SCK↓
(Notes 7, 8, 9)
l
1
ns
t8
SDO into Hi-Z State Time After CONV↑
(Notes 7, 8, 10)
l
3
t9
CONV↑ Quiet Time After 12th SCK↓
(Note 7)
l
15
tWAKE_NAP
Power-Up Time from Nap Mode
See Nap Mode Section
50
ns
tWAKE_SLEEP
Power-Up Time from Sleep Mode
See Sleep Mode Section
1.1
ms
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to ground.
Note 3. When these pin voltages are taken below ground or above VDD
(AIN, REF) or OVDD (SCK, CONV, SDO) they will be clamped by internal
diodes. This product can handle input currents up to 100mA below ground
or above VDD or OVDD without latch-up.
Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 500kHz, fSCK = 20MHz,
AIN = –1dBFS and internal reference unless otherwise noted.
Note 5. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
10
ns
ns
Note 6. Typical RMS noise at code transitions.
Note 7. Parameter tested and guaranteed at OVDD = 2.5V. All input signals
are specified with tr = tf = 1ns (10% to 90% of OVDD) and timed from a
voltage level of OVDD/2.
Note 8. All timing specifications given are with a 10pF capacitance load.
Load capacitances greater than this will require a digital buffer.
Note 9. The time required for the output to cross the VOH or VOL voltage.
Note 10. Guaranteed by design, not subject to test.
Note 11. Recommended operating conditions.
231212fa
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5
LTC2312-12
Typical Performance Characteristics
unless otherwise noted.
0.75
0.75
0.50
0.50
0.25
0.25
0.0
–0.25
–0.75
–0.75
16k Point FFT, fS = 500ksps
fIN = 259kHz
–120
50
100
200
150
INPUT FREQUENCY (kHz)
VDD = 5V
71
VDD = 3V
SNR
SNR
SINAD
70
231212 G04
THD, Harmonics vs Input
Frequency (50kHz to 1MHz)
–75
74
RIN/CIN = 50Ω/47pF
fS = 500ksps
VDD = 3V
–80
73
–85
2ND
SNR, SINAD (dBFS)
THD
3RD
–90
–95
0
250
500
750
INPUT FREQUENCY (kHz)
250
500
750
INPUT FREQUENCY (kHz)
1000
231212 G07
1000
RIN/CIN = 50Ω/47pF
fS = 500ksps
V = 5V
–80 DD
THD
–85
2ND
3RD
–90
–100
VDD = 5V
250
500
750
INPUT FREQUENCY (kHz)
VDD = 3V
SNR
SINAD
5 25 45 65 85 105 125
TEMPERATURE (°C)
231212 G08
1000
231212 G06
–75
SNR
72
69
–55 –35 –15
0
231212 G05
SNR, SINAD vs Temperature,
fIN = 259kHz
70
0
231212 G03
–95
SINAD
71
2049
–75
72
68
250
2048
THD, Harmonics vs Input
Frequency (50kHz to 1MHz)
–80
THD, HARMONICS (dB)
0
2047
2046
CODE
69
–140
THD, HARMONICS (dB)
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
231212 G02
SINAD
–100
6
0
73
–80
–100
4000
74
–60
–160
8000
THD, HARMONICS (dB)
–40
σ = 0.33
12000
SNR, SINAD vs Input Frequency
(50kHz to 1MHz)
VDD = 5V
SNR = 73dBFS
SINAD = 72.7dBFS
THD = –84dB
SFDR = 88dB
–20
AMPLITUDE (dBFS)
–1.00
SNR, SINAD (dBFS)
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
231212 G01
DC Histogram Near Mid-Scale
(Code 2048)
–0.25
–0.50
0
16000
0.00
–0.50
–1.00
Differential Nonlinearity
vs Output Code
COUNTS
1.00
DNL (LSB)
INL (LSB)
1.00
Integral Nonlinearity
vs Output Code
TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 500ksps,
–85
THD, Harmonics vs Temperature,
fIN = 259kHz
VDD = 3V
THD
3RD
–90
2ND
–95
–100
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
231212 G09
231212fa
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LTC2312-12
Typical Performance Characteristics
unless otherwise noted.
THD, Harmonics vs Temperature,
fIN = 259kHz
–85
–90
SNR, SINAD vs Reference Voltage
fIN = 259kHz
Reference Current
vs Reference Voltage
200
SNR
THD
3RD
2ND
72
70
5 25 45 65 85 105 125
TEMPERATURE (°C)
SINAD
VDD = 5V
SNR
SINAD
VDD = 3.6V
71
–95
–100
–55 –35 –15
VDD = 5V
73
2
OPERATION
NOT ALLOWED
2.5
3
3.5
4
REFERENCE VOLTAGE (V)
231212 G10
Full-Scale Error vs Temperature
REFERENCE CURRENT (µA)
THD, HARMONICS (dB)
–80
74
VDD = 5V
SNR, SINAD (dBFS)
–75
TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 500ksps,
VDD = 3.6V
OPERATION
NOT ALLOWED
150
125
100
4.5
2
231212 G11
Offset Error vs Temperature
2.5
3
3.5
4
REFERENCE VOLTAGE (V)
4.5
231212 G12
Supply Current vs Temperature
1
4
3.5
3.4
3
1
0
–1
–2
3.3
0.5
SUPPLY CURRENT (mA)
OFFSET ERROR (LSB)
2
0
–0.5
3.2
3.1
VDD = 5V
3.0
2.9
VDD = 3V
2.8
2.7
–3
2.6
–4
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
231212 G13
–1
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
231212 G14
Shutdown Current vs Temperature
1
IVDD + IOVDD
SUPPLY CURRENT (mA)
0.75
0.5
0.25
VDD = 3V
5 25 45 65 85 105 125
TEMPERATURE (°C)
231212 G15
VDD = 5V
OVDD = 2.5V
ITOT
IVDD
2.5
2.0
1.5
1.0
0.5
VDD = 5V
0
–55 –35 –15
2.5
–55 –35 –15
Supply Current vs Sample Rate
3.5
3.0
SHUTDOWN CURRENT (µA)
FULL-SCALE ERROR (LSB)
175
5 25 45 65 85 105 125
TEMPERATURE (°C)
231212 G16
0
IOVDD
0
100
200
300
400
SAMPLE RATE (kHz)
500
231212 G17
231212fa
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7
LTC2312-12
Typical Performance Characteristics
unless otherwise noted.
0.5
OUTPUT SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
3.50
Supply Current (IVDD)
vs Supply Voltage (VDD)
3.25
3.00
OPERATION
NOT ALLOWED
2.75
2.50
2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3
SUPPLY VOLTAGE (V)
231212 G18
TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 500ksps,
Output Supply Current (IOVDD)
vs Output Supply Voltage (OVDD)
0.4
0.3
0.2
0.1
0
1.8
2.2
2.6 3.0 3.4 3.8 4.2 4.6 5.0
OUTPUT SUPPLY VOLTAGE (V) 231212 G19
Pin Functions
VDD (Pin 1): Power Supply. The ranges of VDD are 2.7V
to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a
2.2µF ceramic chip capacitor.
REF (Pin 2): Reference Input/Output. The REF pin voltage defines the input span of the ADC, 0V to VREF. By
default, REF is an output pin and produces a reference
voltage VREF of either 2.048V or 4.096V depending on
VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR,
high quality ceramic chip capacitor. The REF pin may be
overdriven with a voltage at least 50mV higher than the
internal reference voltage output.
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 4): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VREF.
OVDD (Pin 5): I/O Interface Digital Power. The OVDD range
is 1.71V to 5.25V. This supply is nominally set to the
same supply as the host interface (1.8V, 2.5V, 3.3V or
5V). Bypass to GND with a 2.2µF ceramic chip capacitor.
8
SDO (Pin 6): Serial Data Output. The A/D conversion result
is shifted out on SDO as a serial data stream with the MSB
first through the LSB last. The data stream consists of 12
bits of conversion data followed by trailing zeros. There
is no cycle latency. Logic levels are determined by OVDD.
SCK (Pin 7): Serial Data Clock Input. The SCK serial clock
synchronizes the serial data transfer. SDO data transitions
on the falling edge of SCK. Logic levels are determined
by OVDD.
CONV (Pin 8): Convert Input. This active high signal starts
a conversion on the rising edge. The conversion is timed
via an internal oscillator. The device automatically powers
down following the conversion process. The SDO pin is
in high impedance when CONV is a logic high. Bringing
CONV low enables the SDO pin and outputs the MSB.
Subsequent bits of the conversion data are read out serially on the falling edge of SCK. A logic low on CONV also
places the sample-and-hold into sample mode. Logic levels
are determined by OVDD.
231212fa
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LTC2312-12
Block Diagram
2.2µF
2.2µF
ANALOG SUPPLY
3V OR 5V
I/O INTERFACE SUPPLY
RANGE 1.8V TO 5V
1
5
VDD
OVDD
2.5V LDO
ANALOG
INPUT RANGE
0V TO VREF
AIN
+
4
THREE-STATE
SERIAL
OUTPUT
PORT
12-BIT SAR ADC
S/H
–
SDO
6
REF
SCK
2
2.2µF
GND
3
2×/4×
7
TIMING
LOGIC
1.024V
BANDGAP
CONV
8
TS8 PACKAGE
231212 BD
ALL CAPACITORS UNLESS
NOTED ARE HIGH QUALITY,
CERAMIC CHIP TYPE
Timing Diagrams
t3
CONV
SDO
CONV
OVDD/2
Hi-Z
MSB
VOH
VOL
Figure 1. SDO Enabled After CONV↓
t8
OVDD/2
Hi-Z
SDO
Figure 2. SDO Into Hi-Z After CONV↑
231312 TD01
SCK
t7
231312 TD02
SCK
OVDD/2
V
SDO OH
VOL
SDO
Figure 3. SDO Data Valid Hold After SCK↓
t4
OVDD/2
VOH
VOL
Figure 4. SDO Data Valid Access After SCK↓
231312 TD03
231212 TD04
231212fa
For more information www.linear.com/LTC2312-12
9
LTC2312-12
Applications Information
Overview
Serial Data Output (SDO)
The LTC2312-12 is a low noise, high speed, 12-bit successive approximation register (SAR) ADC. The LTC2312-12
operates from a single 3V or 5V supply and provides a low
drift (20ppm/°C maximum), internal reference and reference buffer. The internal reference buffer is automatically
configured with a 2.048V span in low supply range (2.7V
to 3.6V) and with a 4.096V span in the high supply range
(4.75V to 5.25V). The LTC2312-12 samples at a 500ksps
rate and supports a 20MHz serial data read clock. The
LTC2312-12 achieves excellent dynamic performance
(72.7dB SINAD, –84dB THD) while dissipating only 15mW
from a 5V supply up to the 500ksps conversion rate. The
LTC2312-12 outputs the conversion data with no cycle
latency onto the SDO pin. The SDO pin output logic levels are supplied by the dedicated OVDD supply pin which
has a wide supply range (1.71V to 5.25V) allowing the
LTC2312-12 to communicate with 1.8V, 2.5V, 3V or 5V
systems. The LTC2312-12 automatically switches to nap
mode following the conversion process to save power. The
device also provides a sleep power-down mode through
serial interface control to reduce power dissipation during
long inactive periods.
The SDO output is always forced into the high impedance state while CONV is high. The falling edge of CONV
enables SDO and also places the sample and hold into
sample mode. The A/D conversion result is shifted out
on the SDO pin as a serial data stream with the MSB first.
The MSB is output on SDO on the falling edge of CONV.
Delay t3 is the data valid access time for the MSB. The
following 11 bits of conversion data are shifted out on
SDO on the falling edge of SCK. Delay t4 is the data valid
access time for output data shifted out on the falling edge
of SCK. There is no data latency. Subsequent falling SCK
edges applied after the LSB is output will output zeros
indefinitely on the SDO pin.
Serial Interface
The LTC2312-12 communicates with microcontrollers,
DSPs and other external circuitry via a 3-wire interface.
A rising CONV edge starts the conversion process which
is timed via an internal oscillator. Following the conversion process the device automatically switches to nap
mode to save power as shown in Figure 7. This feature
saves considerable power for the LTC2312-12 operating
at lower sampling rates. As shown in Figures 5 and 6, it
is recommended to hold SCK static low or high during
tCONV. Note that CONV must be held high for the entire
minimum conversion time (tCONV). A falling CONV edge
enables SDO and outputs the MSB. Subsequent SCK
falling edges clock out the remaining data as shown in
Figures 5 and 6. Data is serially output MSB first through
LSB last, followed by trailing zeros if further SCK falling
edges are applied.
10
The output swing on the SDO pin is controlled by the
OVDD pin voltage and supports a wide operating range
from 1.71V to 5.25V independent of the VDD pin voltage.
Power Considerations
The LTC2312-12 provides two sets of power supply pins:
the analog power supply (VDD) and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2312-12 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Entering Nap/Sleep Mode
Pulsing CONV two times and holding SCK static places the
LTC2312-12 into nap mode. Pulsing CONV four times and
holding SCK static places the LTC2312-12 into sleep mode.
In sleep mode, all bias circuitry is shut down, including the
internal bandgap and reference buffer, and only leakage
currents remain (0.2µA typical). Because the reference
buffer is externally bypassed with a large capacitor (2.2µF),
the LTC2312-12 requires a significant wait time (1.1ms) to
recharge this capacitance before an accurate conversion
can be made. In contrast, nap mode does not power down
the internal bandgap or reference buffer allowing for a fast
wake-up and accurate conversion within one conversion clock
cycle. Supply current during nap mode is nominally 2mA.
231212fa
For more information www.linear.com/LTC2312-12
LTC2312-12
Applications Information
t9
tACQ-MIN = 11.5 • tSCK + t2 + t9
CONV
tCONV-MIN
t2
tACQ
t6
SCK
1
t8
t3
HI-Z STATE
SDO
2
3
t5
B11
4
t4
B10
B9
10
11
12
t7
B8
B1
B0
0
(MSB)
tTHROUGHPUT
231212 F05
Figure 5. LTC2312-12 Serial Interface Timing Diagram (SCK Low During tCONV)
t9
tACQ-MIN = 11.5 • tSCK + t2 + t9
CONV
tCONV-MIN
t2
SCK
1
HI-Z STATE
SDO
2
3
t5
t3
t8
tACQ
t6
B11
4
t4
B10
B9
10
11
12
t7
B8
B1
B0
0
(MSB)
tTHROUGHPUT
231212 F06
Figure 6. LTC2312-12 Serial Interface Timing Diagram (SCK High During tCONV)
t9
t2
CONV
CONVERT
POWER-DOWN
tCONV-MIN
NAP MODE
tACQ
SCK
t8
SDO
HI-Z STATE
tCONV > tCONV-MIN
t3
B11
B10
(MSB)
231212 F07
Figure 7. LTC2312-12 Nap Mode Power-Down Following Conversion for tCONV > tCONV-MIN
231212fa
For more information www.linear.com/LTC2312-12
11
LTC2312-12
Applications Information
Exiting Nap/Sleep Mode
Waking up the LTC2312-12 from either nap or sleep
mode, as shown in Figures 8 and 9, requires SCK to be
pulsed one time. A conversion cycle (tACQ) may be started
immediately following nap mode as shown in Figure 8. A
period of time allowing the reference voltage to recover
must follow waking up from sleep mode as shown in Figure
9. The wait period required before initiating a conversion
for the recommended value of CREF of 2.2µF is 1.1ms.
Power Supply Sequencing
The LTC2312-12 does not have any specific power supply sequencing requirements. Care should be taken to
observe the maximum voltage relationships described in
the Absolute Maximum Ratings section.
Single-Ended Analog Input Drive
The analog input of the LTC2312-12 is easy to drive. The
input draws only one small current spike while charging
the sample-and-hold capacitor following the falling edge
of CONV. During the conversion, the analog input draws
only a small leakage current. If the source impedance of
the driving circuit is low, then the input of the LTC2312-12
can be driven directly. As the source impedance increases,
so will the acquisition time. For minimum acquisition time
1
with high source impedance, a buffer amplifier should be
used. The main requirement is that the amplifier driving
the analog input must settle after the small current spike
before the next conversion starts. Settling time must be
less than tACQ-MIN (600ns) for full performance at the
maximum throughput rate. While choosing an input amplifier, also keep in mind the amount of noise and harmonic
distortion the amplifier contributes.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<50Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain
of 1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 50Ω. The
second requirement is that the closed-loop bandwidth
must be greater than 50MHz to ensure adequate small
signal settling for full throughput rate. If slower op amps
are used, more time for settling can be provided by increasing the time between conversions. The best choice
for an op amp to drive the LTC2312-12 will depend on the
application. Generally, applications fall into two categories:
AC applications where dynamic specifications are most
tACQ-MIN
2
CONV
START tCONV
NAP MODE
SCK
START tACQ
HOLD STATIC HIGH or LOW
HI-Z STATE
Z
SDO
Z
231212 F08
Figure 8. LTC2312-12 Entering/Exiting Nap Mode
CONV
1
2
3
NAP MODE
SCK
SDO
4
VREF RECOVERY
SLEEP MODE
START tCONV
tWAIT
HOLD STATIC HIGH or LOW
Z
HI-Z STATE
Z
231212 F09
Figure 9. LTC2312-12 Entering/Exiting Sleep Mode
12
231212fa
For more information www.linear.com/LTC2312-12
LTC2312-12
Applications Information
critical and time domain applications where DC accuracy
and settling time are most critical. The following list is a
summary of the op amps that are suitable for driving the
LTC2312-12. (More detailed information is available on
the Linear Technology website at www.linear.com.)
LT6230: 215MHz GBWP, –80dBc Distortion at 1MHz,
Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/
Amplifier, 1.1nV/√Hz.
LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz, UnityGain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/√Hz.
LT1818/1819: 400MHz GBWP, –85dBc Distortion at 5MHz,
Unity-Gain Stable, 9mA/Amplifier, Single/Dual Voltage
Mode Operational Amplifier.
Input Drive Circuits
The analog input of the LTC2312-12 is designed to be driven
single-ended with respect to GND. A low impedance source
can directly drive the high impedance analog input of the
LTC2312-12 without gain error. A high impedance source
should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC.
For best performance, a buffer amplifier should be used
to drive the analog input of the LTC2312-12. The amplifier
provides low output impedance to allow for fast settling
of the analog signal during the acquisition phase. It also
provides isolation between the signal source and the ADC
inputs which draw a small current spike during acquisition.
gain mode. The 470pF capacitor from AIN to ground and
50Ω source resistor limits the input bandwidth to 7MHz.
The 470pF capacitor also acts as a charge reservoir for
the input sample-and-hold and isolates the LT1818 from
sampling glitch kick-back. The 50Ω source resistor is
used to help stabilize the settling response of the drive
amplifier. When choosing values of source resistance and
shunt capacitance, the drive amplifier data sheet should be
consulted and followed for optimum settling response. If
lower input bandwidths are desired, care should be taken
to optimize the settling response of the driver amplifier with
higher values of shunt capacitance or series resistance.
High quality capacitors and resistors should be used in the
RC filter since these components can add distortion. NP0/
C0G and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems. When high
amplitude unwanted signals are close in frequency to the
desired signal frequency, a multiple pole filter is required.
High external source resistance, combined with external
shunt capacitance at Pin 4 will significantly reduce the
input bandwidth and may increase the required acquisition time beyond the minimum acquisition time (tACQ-MIN)
of 600ns.
ANALOG IN
Input Filtering
The noise and distortion of the buffer amplifier and other
circuitry must be considered since they add to the ADC
noise and distortion. Noisy input circuitry should be filtered
prior to the analog inputs to minimize noise. A simple
1-pole RC filter is sufficient for many applications.
Large filter RC time constants slow down the settling at
the analog inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle to >12-bit resolution within the minimum
acquisition time (tACQ-MIN) of 600ns.
A simple 1-pole RC filter is sufficient for many applications.
For example, Figure 10 shows a recommended singleended buffered drive circuit using the LT1818 in unity
+
–
LT1818
LTC2312-12
50Ω
AIN
470pF
GND
231212 F10
Figure 10. RC Input Filter
ADC Reference
A low noise, low temperature drift reference is critical to
achieving the full data sheet performance of the ADC. The
LTC2312-12 provides an excellent internal reference with
a guaranteed 20ppm/°C maximum temperature coefficient.
For added flexibility, an external reference may also be used.
The high speed, low noise internal reference buffer is used
only in the internal reference configuration. The reference
For more information www.linear.com/LTC2312-12
231212fa
13
LTC2312-12
Applications Information
buffer must be overdriven in the external reference configuration with a voltage 50mV higher than the nominal
reference output voltage in the internal configuration.
Using the Internal Reference
The internal bandgap and reference buffer are active by
default when the LTC2312-12 is not in sleep mode. The
reference voltage at the REF pin scales automatically with
the supply voltage at the VDD pin. The scaling of the reference voltage with supply is shown in Table 2.
Table 2. Reference Voltage vs Supply Range
SUPPLY VOLTAGE (VDD)
REF VOLTAGE (VREF)
2.7V < VDD < 3.6V
2.048V
4.75V < VDD < 5.25V
4.096V
The reference voltage also determines the full-scale analog
input range of the LTC2312-12. For example, a 2.048V
reference voltage will accommodate an analog input range
from 0V to 2.048V. An analog input voltage that goes below
0V will be coded as all zeros and an analog input voltage
that exceeds 2.048V will be coded as all ones.
It is recommended that the REF pin be bypassed to ground
with a low ESR, 2.2µF ceramic chip capacitor for optimum
performance.
External Reference
An external reference can be used with the LTC2312-12
if better performance is required or to accommodate a
larger input voltage span. The only constraints are that
the external reference voltage must be 50mV higher than
the internal reference voltage (see Table 2) and must be
less than or equal to the supply voltage (or 4.3V for the 5V
supply range). For example, a 3.3V external reference may
be used with a 3.3V VDD supply voltage to provide a 3.3V
analog input voltage span (i.e. 3.3V > 2.048V + 50mV).
Or alternatively, a 2.5V reference may be used with a 3V
supply voltage to provide a 2.5V input voltage range (i.e.
2.5V > 2.048V + 50mV). The LTC6655-3.3, LTC6655-2.5,
available from Linear Technology, may be suitable for
many applications requiring a high performance external
reference for either 3.3V or 2.5V input spans respectively.
Transfer Function
Figure 11 depicts the transfer function of the LTC2312-12.
The code transitions occur midway between successive
integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB… FS0.5LSB). The output code is straight binary with 1LSB =
VREF/4096.
DC Performance
The noise of an ADC can be evaluated in two ways: signalto-noise ratio (SNR) in the frequency domain and histogram in the time domain. The LTC2312-12 excels in both.
The noise in the time domain histogram is the transition
noise associated with a 12-bit resolution ADC which can
be measured with a fixed DC signal applied to the input of
the ADC. The resulting output codes are collected over a
large number of conversions. The shape of the distribution
of codes will give an indication of the magnitude of the
transition noise. In Figure 12, the distribution of output
codes is shown for a DC input that has been digitized
16000
111...111
σ = 0.33
111...110
COUNTS
OUTPUT CODE
12000
8000
4000
000...001
0
000...000
0 1LSB
INPUT VOLTAGE (V)
FS – 1LSB
Figure 11. LTC2312-12 Transfer Function
14
2046
2047
2048
CODE
231212 F11
2049
231212 F12
Figure 12. Histogram for 16384 Conversions
231212fa
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LTC2312-12
Applications Information
16,384 times. The distribution is Gaussian and the RMS
code transition noise is 0.33LSB. This corresponds to a
noise level of 73dB relative to a full scale voltage of 4.096V.
At the maximum sampling rate of 500kHz, the LTC2312-12
maintains an ENOB above 11.7 bits up to two times the
Nyquist input frequency. (Figure 14)
Dynamic Performance
Signal-to-Noise Ratio (SNR)
The LTC2312-12 has excellent high speed sampling
capability. Fast Fourier Transform (FFT) techniques are
used to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the applied fundamental. The
LTC2312-12 provides guaranteed tested limits for both
AC distortion and noise measurements.
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 13 shows
that the LTC2312-12 achieves a typical SNR of 73dB at
a 500kHz sampling rate with a 259kHz input frequency.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 14 shows the LTC2312-12 maintains a
SINAD above 72dB up to an input frequency of 1MHz.
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is a measurement of
the resolution of an ADC and is directly related to SINAD
by the equation where ENOB is the effective number of
bits of resolution and SINAD is expressed in dB:
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
V22 + V32 + V42 + VN2
THD=20log
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics. THD versus Input Frequency is
shown in the Typical Performance Characteristics section.
The LTC2312-12 has excellent distortion performance up
to two times the Nyquist frequency.
ENOB = (SINAD – 1.76)/6.02
0
–20
73
SINAD (dBFS)
–60
–80
–100
–120
72
11.67
71
11.50
–140
–160
11.83
VDD = 5V
ENOB
AMPLITUDE (dBFS)
–40
12.00
74
VDD = 5V
SNR = 73dBFS
SINAD = 72.7dBFS
THD = –84dB
SFDR = 88dB
VDD = 3V
0
50
100
200
150
INPUT FREQUENCY (kHz)
250
70
0
500
750
INPUT FREQUENCY (kHz)
231212 F13
Figure 13. 16k Point FFT of the LTC2312-12 at fIN = 259kHz
250
11.34
1000
231212 F14
Figure 14. LTC2312-12 ENOB/SINAD vs fIN
For more information www.linear.com/LTC2312-12
231212fa
15
LTC2312-12
Applications Information
Intermodulation Distortion (IMD)
Full-Power and –3dB Input Linear Bandwidth
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
The full-power bandwidth is the input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full-scale input signal.
If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies m • fa ± n • fb, where m and n = 0,
1, 2, 3, etc. For example, the 2nd order IMD terms include
(fa ± fb). If the two input sine waves are equal in magnitude,
the value (in decibels) of the 2nd order IMD products can
be expressed by the following formula:
IMD(fa ± fb) = 20 • log[VA (fa ± fb)/VA (fa)]
The LTC2312-12 has excellent IMD, as shown in Figure 15.
0
fa
fb
–20
MAGNITUDE (dB)
–40
–60
f –f
–80 b a
2fa – fb
–100
2fb – fa
VDD = 5V
fs = 500ksps
fa = 53.14kHz
fb = 58.142kHz
IMD2 (fb – fa) = –80dBc
IMD3 (2fb – fa) = –92dBc
fb + fa
–120
–140
–160
0
50
100
150
200
INPUT FREQUENCY (kHz)
250
231212 F15
Figure 15. LTC2312-12 IMD Plot
Spurious Free Dynamic Range (SFDR)
The spurious free dynamic range is the largest spectral
component excluding DC and the input signal. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.
16
The –3dB linear bandwidth is the input frequency at which
the SINAD has dropped to 68dB (11 effective bits). The
LTC2312-12 has been designed to optimize the input
bandwidth, allowing the ADC to under-sample input signals
with frequencies above the converter’s Nyquist frequency.
The noise floor stays very low at high frequencies and
SINAD becomes dominated by distortion at frequencies
beyond Nyquist.
Recommended Layout
To obtain the best performance from the LTC2312-12 a
printed circuit board is required. Layout for the printed
circuit board (PCB) should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Figure 16 through Figure 20 are an example of a recommended PCB layout. A single solid ground plane is used.
Bypass capacitors to the supplies are placed as close as
possible to the supply pins. Low impedance common
returns for these bypass capacitors are essential to the
low noise operation of the ADC. The analog input traces
are screened by ground. For more details and information
refer to DC1563, the evaluation kit for the LTC2312-12.
Bypassing Considerations
High quality tantalum and ceramic bypass capacitors
should be used at the VDD, OVDD and REF pins. For optimum
performance, a 2.2µF ceramic chip capacitor should be
used for the VDD and OVDD pins. The recommended bypassing for the REF pin is also a low ESR, 2.2µF ceramic chip
capacitor. The traces connecting the pins and the bypass
capacitors must be kept as short as possible and should
be made as wide as possible avoiding the use of vias.
All analog circuitry grounds should be terminated at the
LTC2312-12. The ground return from the LTC2312-12 to
the power supply should be low impedance for noise free
operation. Digital circuitry grounds must be connected to
the digital supply common.
231212fa
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LTC2312-12
Applications Information
In applications where the ADC data outputs and control
signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion
results. These errors are due to feed-through from the
microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the
microprocessor into a “Wait” state during conversion or
by using three-state buffers to isolate the ADC data bus.
Figure 16. Top Silkscreen
Figure 17. Layer 1 Top Layer
Figure 18. Layer 2 GND Plane
231212fa
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17
LTC2312-12
Applications Information
Figure 19. Layer 3 PWR Plane
Figure 20. Layer 4 Bottom Layer
18
231212fa
For more information www.linear.com/LTC2312-12
LTC2312-12
Applications Information
REF
U5
LT1790ACS6-2.048
9V TO 10V
4
VI
GND
GND
1
2
JP1
HD1X3-100
J4
AIN
0V TO 4.096V
C6
4.7µF
R14
0k
VO
AC
C8
10µF
R9
1k
VCCIO
C9
4.7µF
C10
OPT
C11
OPT
C12
4.7µF
DC
COUPLING
1 2 3
C18
OPT
C7
OPT
VDD
VCM
6
+
R15
49.9Ω
C17
1µF
3
2
1
U1
*
4
C19
47pF
NP0
JP2
VCM
1.024V
1
2
5
VDD REF OVDD
AIN
CSL
SCK
GND
3
2.048V
SDO
231212 F21
8
CSL*
7
SCK
SDO
6
R16
33Ω
*NOTE: CSL = CONV
HD1X3-100
R18
1k
Figure 21. Partial 1563 Demo Board Schematic
231212fa
For more information www.linear.com/LTC2312-12
19
LTC2312-12
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
0.40
MAX
2.90 BSC
(NOTE 4)
0.65
REF
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.95 BSC
TS8 TSOT-23 0710 REV A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
20
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LTC2312-12
Revision History
REV
DATE
DESCRIPTION
A
1/15
Updated Timing Diagrams (Figures 8 and 9)
PAGE NUMBER
12
231212fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
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21
LTC2312-12
Typical Application
Low Jitter Clock Timing with RF Sine Generator Using Clock
Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop
VCC
1k NC7SVU04P5X
0.1µF
50Ω
MASTER CLOCK
VCC
1k
PRE
D
>
Q
CONV
CLR
NL17SZ74
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
SDO ENABLE
CONV
SCK
LTC2312-12
NC7SVUO4P5X
SDO
33Ω
231212 TA02
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC2313-12
12-Bit, 2.5Msps Serial ADC
3V/5V, 14mW/25mW, 20ppm/°C Max Internal Reference,
Single-Ended Input, 8-Lead TSOT-23 Package
LTC2315-12
12-Bit, 5Msps Serial ADC
3V/5V, 19mW/32mW, 20ppm/°C Max Internal Reference,
Single-Ended, 8-Lead TSOT-23 Package
LTC1403/LTC1403-1
12-Bit, 2.8Msps Serial ADC
3V, 14mW, Unipolar/Bipolar Inputs, MSOP Package
LTC1407/LTC1407-1
12-Bit, 3Msps Simultaneous Sampling ADC
3V, 2-Channel Differential, Unipolar/Bipolar Inputs, 14mW,
MSOP Package
LTC2355/LTC2356
12-/14-Bit, 3.5Msps Serial ADC
3.3V Supply, Differential Inputs, 18mW, MSOP Package
LTC2365/LTC2366
12-Bit, 1Msps/3Msps Serial Sampling ADC
3.3V Supply, Single-Ended, 8mW, TSOT-23 Package
LT6200/LT6201
Single/Dual Operational Amplifiers
165MHz, 0.95nV/√Hz
LT6230/LT6231
Single/Dual Operational Amplifiers
215MHz, 3.5mA/Amplifier, 1.1nV/√Hz
LT6236/LT6237
Single/Dual Operational Amplifier with
Low Wideband Noise
215MHz, 3.5mA/Amplifier, 1.1nV/√Hz
LT1818/LT1819
Single/Dual Operational Amplifiers
400MHz, 9mA/Amplifier, 6nV/√Hz
LTC6655-2.5/LTC6655-3.3
Precision Low Drift Low Noise Buffered Reference
2.5V/3.3V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise,
MSOP-8 Package
LT1461-3/LT1461-3.3V
Precision Series Voltage Family
0.05% Initial Accuracy, 3ppm Drift
ADCs
Amplifiers
References
22 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2312-12
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2312-12
231212fa
LT 0115 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2013