Cypress CY62138CVLL-70BVI 2m (256k x 8) static ram Datasheet

CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
2M (256K x 8) Static RAM
Features
bits. This device features advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Life™ (MoBL®) in portable applications. The device also has
an automatic power-down feature that significantly reduces
power consumption by 80% when addresses are not toggling.
The device can be put into standby mode reducing power
consumption by more than 99% when deselected (CE1 HIGH
or CE2 LOW).
• Very high speed: 55 ns and 70 ns
• Voltage range:
— CY62138CV25: 2.2V–2.7V
— CY62138CV30: 2.7V–3.3V
— CY62138CV33: 3.0V–3.6V
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is
then written into the location specified on the address pins (A0
through A17).
— CY62138CV: 2.7V–3.6V
• Pin-compatible with CY62138V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
•
•
•
•
•
— Typical active current: 5.5 mA @ f = fmax (70-ns
speed)
Low standby power
Easy memory expansion with CE1, CE2, and OE
features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 36-ball FBGA
Functional Description[1]
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable 2 (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH and WE LOW).
See the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62138CV25/30/33 and CY62138CV are high-performance CMOS static RAMs organized as 256K words by eight
Logic Block Diagram
I/O0
Data in Drivers
I/O1
256K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A
A109
A11
I/O3
I/O4
I/O5
CE1
CE2
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A12
A13
A14
A15
A16
A17
WE
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05200 Rev. *D
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 20, 2002
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
[2, 3]
Pin Configuration
FBGA (Top View)
3
4
5
6
A1
CE2
A3
A6
A8
A
A2
WE
A4
A7
I/O0
B
DNU
A5
I/O1
C
VSS
VCC
D
VCC
VSS
E
I/O2
F
1
2
A0
I/O4
I/O5
I/O6
NC
A17
I/O7
OE
CE1
A16
A15
I/O3
G
A9
A10
A11
A12
A13
A14
H
Maximum Ratings
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current ................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied .............................................. 55°C to +125°C
Supply Voltage to Ground Potential ... –0.5V VCCMAX + 0.5V
DC Voltage Applied to Outputs
in High-Z State[4] .....................................0.5V to VCC + 0.3V
DC Input Voltage[4].................................–0.5V to VCC + 0.3V
Product
CY62138CV25
CY62138CV30
CY62138CV33
CY62138CV
Ambient
Range Temperature TA
VCC
Industrial –40°C to +85°C 2.2V to 2.7V
2.7V to 3.3V
3.0V to 3.6V
2.7V to 3.6V
Output Current into Outputs (LOW) ............................20 mA
Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
Product
CY62138CV25LL
CY62138CV30LL
CY62138CV33LL
CY62138CVLL
Min.
Typ.[5]
2.2
2.5
2.7
3.0
2.7
3.0
3.3
3.3
f = 1 MHz
Max.
Speed
(ns)
Typ.[5]
Max.
2.7
55
1.5
70
1.5
55
3.3
3.6
3.6
Standby, ISB2 (µA)
f = fmax
Typ.[5]
Max.
Typ.[5]
Max.
3
7
15
2
10
3
5.5
12
1.5
3
7
15
2
10
70
1.5
3
5.5
12
55
1.5
3
7
15
5
15
70
1.5
3
5.5
12
70
1.5
3
5.5
12
5
15
Notes:
2. NC pins are not connected to the die.
3. C3 (DNU) can be left as NC or VSS to ensure proper application.
4. VIL(min.) = –2.0V for pulse durations less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05200 Rev. *D
Page 2 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Electrical Characteristics Over the Operating Range
CY62138CV25-55
Parameter
Description
Test Conditions
Min.
Typ.[5]
Max.
VOH
Output HIGH Voltage
IOH = –0.1 mA
VCC = 2.2V
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 2.2V
VIH
Input HIGH Voltage
1.8
VCC +
0.3V
VIL
Input LOW Voltage
–0.3
IIX
Input Leakage Current GND < VI < VCC
–1
IOZ
Output Leakage
Current
–1
ICC
VCC Operating Supply f = fMAX = 1/tRC
Current
f = 1 MHz
GND < VO < VCC, Output Disabled
2.0
Automatic CE
Power-down Current
— CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V, f =
fmax (Address and Data Only), f = 0
(OE, WE)
ISB2
Automatic CE
Power-down Current
— CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC
= 2.7V
Description
Test Conditions
V
V
1.8
VCC +
0.3V
V
0.6
–0.3
0.6
V
+1
–1
+1
µA
+1
–1
+1
µA
mA
7
15
5.5
12
1.5
3
1.5
3
2
10
2
10
Min.
Typ.[5]
Unit
0.4
CY62138CV30-55
Parameter
Max.
2.0
0.4
VCC = 2.7V
IOUT = 0 mA
CMOS Levels
ISB1
CY62138CV25-70
Min. Typ.[5]
Max.
CY62138CV30-70
Min. Typ.[5]
Max.
Output HIGH Voltage
IOH = –1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
0.4
V
VIH
Input HIGH Voltage
2.2
VCC +
0.3V
2.2
VCC +
0.3V
V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
–1
+1
–1
+1
µA
ICC
VCC Operating Supply f = fMAX = 1/tRC
Current
f = 1 MHz
mA
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
ISB1
Automatic CE
Power-down Current
— CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V, f =
fmax (Address and Data Only), f = 0
(OE, WE)
ISB2
Automatic CE
Power-down Current
— CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V, VIN
> VCC − 0.2V or VIN < 0.2V, f = 0,
VCC=3.3V
Document #: 38-05200 Rev. *D
2.4
Unit
VOH
GND < VO < VCC, Output Disabled
2.4
µA
V
0.4
7
15
5.5
12
1.5
3
1.5
3
2
10
2
10
µA
Page 3 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Electrical Characteristics Over the Operating Range
CY62138CV33-70
CY62138CV-70
CY62138CV33-55
Parameter
VOH
Description
Min. Typ.[5]
Test Conditions
Output HIGH Voltage
IOH = –1.0 mA
VCC = 3.0V
Max.
Min. Typ.[5]
2.4
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 3.0V
Max.
Unit
2.4
V
2.4
V
0.4
VCC = 2.7V
0.4
V
0.4
V
V
VIH
Input HIGH Voltage
2.2
VCC +
0.3V
2.2
VCC +
0.3V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
–1
+1
–1
+1
µA
ICC
VCC Operating Supply f = fMAX = 1/tRC
Current
f = 1 MHz
mA
GND < VO < VCC, Output Disabled
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
ISB1
Automatic CE
CE1 > VCC – 0.2V or CE2 < 0.2V
Power-down Current— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
CE1 > VCC – 0.2V or CE2 < 0.2V
Power-down Current— VIN > VCC − 0.2V or VIN < 0.2V,
CMOS Inputs
f = 0, VCC = 3.6V
7
15
5.5
12
1.5
3
1.5
3
5
15
5
15
µA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
6
pF
8
pF
Thermal Resistance
Parameter
Description
ΘJA
Thermal
(Junction to Ambient)
ΘJC
Thermal Resistance[6]
(Junction to Case)
Resistance[6]
Test Conditions
BGA
Unit
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
55
°C/W
16
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
VCC Typ
30 pF
INCLUDING
JIG AND
SCOPE
10%
R2
90%
GND
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
90%
10%
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05200 Rev. *D
Page 4 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Parameters
2.5V
3.0V
3.3V
Unit
R1
16600
1105
1216
Ω
R2
15400
1550
1374
Ω
RTH
8000
645
645
Ω
VTH
1.20
1.75
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[6]
Chip Deselect to Data
Retention Time
tR[7]
Operation Recovery Time
Min.
Typ.[5]
1.5
VCC = 1.5V
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC − 0.2V or VIN < 0.2V
Max.
Unit
VCC(max.)
V
6
µA
1
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC(min.)
VDR > 1.5 V
VCC(min.)
VCC
tR
tCDR
CE1
or
CE2
Switching Characteristics Over the Operating Range[8]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
55
Low-Z[9]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[9, 10]
Low-Z[9]
CE1 LOW and CE2 HIGH to
CE1 HIGH or CE2 LOW to High-Z[9, 10]
tPU
CE1 LOW and CE2 HIGH to Power-up
tPD
CE1 HIGH or CE2 LOW to Power-down
ns
70
10
10
ns
25
10
20
0
ns
ns
25
0
55
ns
ns
5
20
tHZCE
tWC
10
5
tLZCE
Write
70
ns
ns
70
ns
Cycle[11]
Write Cycle Time
55
70
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
45
60
ns
Notes:
7. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05200 Rev. *D
Page 5 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Switching Characteristics Over the Operating Range[8] (continued)
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[9, 10]
tLZWE
WE HIGH to
0
ns
20
Low-Z[9]
10
25
10
ns
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [13, 14]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
12. Device is continuously selected. OE, CE1 = VIL, CE2=VIH.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05200 Rev. *D
Page 6 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Switching Waveforms (continued)
[11, 15, 17]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 16
tHZOE
[11, 15, 17]
Write Cycle No. 2 (CE1 or CE2 Controlled)
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tAW
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
Notes:
15. Data I/O is high impedance if OE = VIH.
16. During this period, the I/Os are in output state and input signals should not be applied.
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.
Document #: 38-05200 Rev. *D
Page 7 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[17]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tSD
DATAI/O
NOTE 16
DATAIN VALID
tHZWE
Document #: 38-05200 Rev. *D
tHD
tLZWE
Page 8 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)
Operating Current vs. Supply Voltage
14.0
14.0
12.0
12.0
12.0
12.0
MoBL
ICC (mA)
ICC (mA)
10.0
(f = fmax,
55 ns)
8.0
6.0
(f = fmax,
70 ns)
4.0
2.0
10.0
MoBL
8.0
(f = fmax,
55 ns)
6.0
(f = fmax,
70 ns)
4.0
(f = 1MHz)
MoBL
8.0
(f = fmax,
55 ns)
6.0
4.0
(f = 1MHz)
10.0
8.0
MoBL
(f = fmax,
55 ns)
(f = fmax,
70 ns)
6.0
(f = fmax,
70 ns)
2.0
2.0
0.0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
0.0
2.2
2.5 2.7
SUPPLY VOLTAGE (V)
10.0
ICC (mA)
14.0
ICC (mA)
14.0
4.0
(f = 1MHz)
0.0
3.6
3.3
3.0
SUPPLY VOLTAGE (V)
2.0
(f = 1MHz)
0.0
3.6
3.3
2.7
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
MoBL
12.0
10.0
10.0
8.0
MoBL
6.0
6.0
2.0
2.0
2.2 2.5 2.7
SUPPLY VOLTAGE (V)
3.0
2.7
10.0
8.0
6.0
6.0
4.0
4.0
2.0
2.0
0
0
MoBL
8.0
4.0
4.0
12.0
MoBL
ISB (µA)
8.0
12.0
ISB (µA)
10.0
ISB (µA)
ISB (µA)
12.0
0
3.3
3.0
SUPPLY VOLTAGE (V)
3.3
0
3.6
3.3
2.7
SUPPLY VOLTAGE (V)
3.6
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
MoBL
60
MoBL
60
MoBL
50
50
40
40
40
40
30
30
30
30
20
20
20
10
10
10
0
0
0
2.2
2.5
2.7
2.7
SUPPLY VOLTAGE (V)
3.0
3.3
SUPPLY VOLTAGE (V)
TAA (ns)
50
TAA (ns)
50
TAA (ns)
TAA (ns)
60
20
10
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
Truth Table
Mode
0
2.7
3.3
3.6
SUPPLY VOLTAGE (V)
CE1
CE2
WE
OE
H
X
X
X
High-Z
Deselect/Power-down
Standby (ISB)
X
L
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
Data Out (I/O0-I/O7)
Read
Active (ICC)
L
H
H
H
High-Z
Output Disabled
Active (Icc)
L
H
L
X
Data in (I/O0-I/O7)
Write
Active (Icc)
Document #: 38-05200 Rev. *D
Inputs/Outputs
MoBL
Power
Page 9 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Ordering Information
Speed
(ns)
Ordering Code
Voltage
Range (V)
70
CY62138CV25LL-70BAI
2.2–2.7
CY62138CV25LL-70BVI
2.2–2.7
CY62138CV30LL-70BAI
2.7–3.3
BA36A
36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62138CV30LL-70BVI
2.7–3.3
BV36A
36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62138CV33LL-70BAI
3.0–3.6
BA36A
36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62138CV33LL-70BVI
3.0–3.6
BV36A
36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
55
Package
Name
Package Type
Operating
Range
BA36A
36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
Industrial
BV36A
36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62138CVLL-70BAI
2.7–3.6
BA36A
36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62138CVLL-70BVI
2.7–3.6
BV36A
36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62138CV25LL-55BAI
2.2–2.7
BA36A
36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62138CV25LL-55BVI
2.2–2.7
BV36A
36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62138CV30LL-55BAI
2.7–3.3
BA36A
36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62138CV30LL-55BVI
2.7–3.3
BV36A
36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62138CV33LL-55BAI
3.0–3.6
BA36A
36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62138CV33LL-55BVI
3.0–3.6
BV36A
36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Package Diagrams
36-ball FBGA (7 x 7 x 1.2 mm) BA36A
51-85099-*C
Document #: 38-05200 Rev. *D
Page 10 of 12
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Package Diagrams (continued)
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
51-85149-*A
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05200 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Document History Page
Document Title: CY62138CV25/30/33 MoBL®/CY62138CV MoBL® 2M (256K x 8) Static RAM
Document Number: 38-05200
REV.
ECN NO.
Issue Date
Orig. of
Change
**
112381
02/19/02
GAV
New Data Sheet (advance information)
*A
114024
04/25/02
JUI
Added BV package diagram
Changed from Advance Information to Preliminary
*B
117062
07/12/02
MGN
Added Second Chip Enable
Changed from Preliminary to Final
*C
118123
09/09/02
MGN
Added new part number: CY62138CV with wider voltage (2.7V – 3.6V)
For TAA = 55 ns, improved tPWE min. from 45 ns to 40 ns
For TAA = 70 ns, improved tPWE min. from 60 ns to 45 ns
For TAA = 70 ns, improved tLZWE min. from 5 ns to 10 ns
*D
118760
09/23/02
MGN
Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns).
Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns).
For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns.
Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX +
0.5V.
Changed upper spec for DC Voltage Applied to Ouputs in High-Z State and
DC Input Voltage to VCC + 0.3V.
Document #: 38-05200 Rev. *D
Description of Change
Page 12 of 12
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