ATMEL AT25320B Spi serial eeproms 32k (4096 x 8) 64k (8192 x 8) Datasheet

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
– 1.8 (VCC = 1.8V to 5.5V)
20 MHz Clock Rate (5V)
32-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead
TSSOP and 8-lead Ultra Lead Frame Land Grid Array (ULA) Packages
Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
SPI Serial
EEPROMs
32K (4096 x 8)
64K (8192 x 8)
AT25320B
AT25640B
Description
The AT25320B/640B provides 32768/65536 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The AT25320B/640B is
available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin MiniMAP (MLP 2x3), 8-lead Ultra Lead Frame Land Grid Array (ULA) and 8-lead TSSOP
packages.
Advance
Information
The AT25320B/640B is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write.
Table 0-1.
Pin Configuration
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-lead PDIP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead TSSOP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8535B–SEEPR–7/08
8-lead Ultra Thin Mini-MAP (MLP 2x3)
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
VCC
HOLD
SCK
SI
8
7
6
5
CS
SO
WP
GND
1
2
3
4
Bottom View
8-ball dBGA2
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
Bottom View
8-lead Ultra Lead Frame
Land Grid Array (ULA)
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
Bottom View
Block write protection is enabled by programming the status register with one of four blocks of
write protection. Separate program enable and program disable instructions are provided for
additional data protection. Hardware data protection is provided via the WP pin to protect
against inadvertent write attempts to the status register. The HOLD pin may be used to suspend
any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA
2
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
Figure 0-1.
Table 0-2.
Block Diagram
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
Max
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT = 0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
Note:
1. This parameter is characterized and is not 100% tested.
3
8535B–SEEPR–7/08
Table 0-3.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Min
Max
Units
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 20 MHz, SO = Open, Read
7.5
10.0
mA
ICC2
Supply Current
VCC = 5.0V at 20 MHz, SO = Open, Read,
Write
4.0
10.0
mA
ICC3
Supply Current
VCC = 5.0V at 5 MHz, SO = Open,
Read, Write
4.0
6.0
mA
ISB1
Standby Current
VCC = 1.8V, CS = VCC
< 0.1
6.0(2)
µA
ISB2
Standby Current
VCC = 2.7V, CS = VCC
0.3
7.0(2)
µA
ISB3
Standby Current
VCC = 5.0V, CS = VCC
IIL
Input Leakage
VIN = 0V to VCC
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
VIL(1)
Typ
10.0
µA
–3.0
3.0
µA
–3.0
3.0
µA
Input Low-voltage
–0.6
VCC x 0.3
V
VIH(1)
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
0.4
V
VOH1
Output High-voltage
VOL2
Output Low-voltage
VOH2
Output High-voltage
Notes:
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
2.0
(2)
IOL = 3.0 mA
IOH = −1.6 mA
VCC - 0.8
IOL = 0.15 mA
IOH = −100 µA
V
0.2
VCC - 0.2
V
V
1. VIL min and VIH max are reference only and are not tested.
2. Worst case measured at 85°C
4
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
Table 0-4.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
20
10
5
MHz
tRI
Input Rise Time
4.5–5.5
2.7–5.5
1.8–5.5
2
2
2
µs
tFI
Input Fall Time
4.5–5.5
2.7–5.5
1.8–5.5
2
2
2
µs
tWH
SCK High Time
4.5–5.5
2.7–5.5
1.8–5.5
20
40
80
ns
tWL
SCK Low Time
4.5–5.5
2.7–5.5
1.8–5.5
20
40
80
ns
tCS
CS High Time
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
ns
tCSS
CS Setup Time
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
ns
tCSH
CS Hold Time
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
ns
tSU
Data In Setup Time
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
ns
tH
Data In Hold Time
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
ns
tHD
HOLD Setup Time
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
tCD
HOLD Hold Time
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
tV
Output Valid
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
tHO
Output Hold Time
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
ns
20
40
80
ns
ns
5
8535B–SEEPR–7/08
Table 0-4.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
tLZ
HOLD to Output Low Z
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
25
50
100
ns
tHZ
HOLD to Output High Z
4.5–5.5
2.7–5.5
1.8–5.5
40
80
200
ns
tDIS
Output Disable Time
4.5–5.5
2.7–5.5
1.8–5.5
40
80
200
ns
tWC
Write Cycle Time
4.5–5.5
2.7–5.5
1.8–5.5
5
5
5
ms
Endurance(1)
3.3V, 25°C, Page Mode
Note:
1M
Write Cycles
1. This parameter is characterized and is not 100% tested.
1. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25320B/640B always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25320B/640B has separate pins designated for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25320B/640B, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25320B/640B is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25320B/640B.
When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
6
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is “0”. This will allow the user to install the AT25320B/640B in a system with the WP pin
tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
Figure 1-1.
SPI Serial Interface
AT25320B/640B
2. Functional Description
The AT25320B/640B is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25320B/640B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 2-1. All instructions, addresses, and data are transferred with
the MSB first and start with a high-to-low CS transition.
Table 2-1.
Instruction Set for the AT25320B/640B
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
7
8535B–SEEPR–7/08
Table 2-1.
Instruction Set for the AT25320B/640B
Instruction Name
Instruction Format
Operation
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR instruction.
Table 2-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 2-3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
Bit 2 (BP0)
See Table 2-4 on page 9.
Bit 3 (BP1)
See Table 2-4 on page 9.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 2-5 on page 9.
Bits 0–7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25320B/640B is divided into four array segments. One-quarter,
one-half, or all of the memory segments can be protected. Any of the data within any selected
segment will therefore be read only. The block write protection levels and corresponding status
register control bits are shown in Table 2-4 on page 9.
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, tWC, RDSR).
8
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
Table 2-4.
Block Write Protect Bits
Status Register Bits
Level
Array Addresses Protected
BP1
BP0
AT25320B
AT25640B
0
0
0
None
None
1(1/4)
0
1
0C00−0FFF
1800−1FFF
2(1/2)
1
0
0800−0FFF
1000−1FFF
3(All)
1
1
0000−0FFF
0000−1FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the status register, including the block protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as
long as the WP pin is held low.
Table 2-5.
WPEN Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writeable
Writeable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writeable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writeable
Writeable
READ SEQUENCE (READ): Reading the AT25320B/640B via the Serial Output (SO) pin
requires the following sequence. After the CS line is pulled low to select a device, the read opcode is transmitted via the SI line followed by the byte address to be read (A15–A0, see Table 26). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the specified
address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The read sequence can be continued since the byte
address is automatically incremented and data will continue to be shifted out. When the highest
address is reached, the address counter will roll over to the lowest address allowing the entire
memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25320B/640B, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction.
Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s)
to be programmed must be outside the protected address field location selected by the block
write protection level. During an internal write cycle, all commands will be ignored except the
RDSR instruction.
9
8535B–SEEPR–7/08
A write instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15–A0)
and the data (D7–D0) to be programmed (see Table 2-6). Programming will start after the CS pin
is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time
immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle
has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25320B/640B is capable of a 32-byte page write operation. After each byte of data is
received, the five low-order address bits are internally incremented by one; the high-order bits of
the address will remain constant. If more than 32 bytes of data are transmitted, the address
counter will roll over and the previously written data will be overwritten. The AT25320B/640B is
automatically returned to the write disable state at the completion of a write cycle.
NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to
reinitiate the serial communication.
Table 2-6.
Address Key
Address
AT25320B
AT25640B
AN
A11–A0
A12–A0
Don’t Care Bits
A15–A12
A15–A13
3. Timing Diagrams
Figure 3-1.
Synchronous Data Timing (for Mode 0)
t CS
VIH
CS
VIL
t CSH
t CSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
VIH
SI
VALID IN
VIL
tV
VOH
SO
HI-Z
t HO
t DIS
HI-Z
VOL
10
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
Figure 3-2.
WREN Timing
Figure 3-3.
WRDI Timing
Figure 3-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
SI
SO
INSTRUCTION
HIGH IMPEDANCE
DATA OUT
7
6
5
4
3
MSB
11
8535B–SEEPR–7/08
Figure 3-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA IN
4
3
2
1
0
SCK
INSTRUCTION
SI
SO
Figure 3-6.
7
6
5
HIGH IMPEDANCE
READ Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
SO
Figure 3-7.
INSTRUCTION
HIGH IMPEDANCE
BYTE ADDRESS
15 14 13 ... 3 2 1 0
DATA OUT
7 6 5 4 3 2 1 0
MSB
WRITE Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
SO
12
INSTRUCTION
BYTE ADDRESS
DATA IN
...
15 14 13
3 2 1 0 7 6 5 4 3 2 1 0
HIGH IMPEDANCE
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
Figure 3-8.
HOLD Timing
CS
tCD
tCD
SCK
t HD
t HD
HOLD
t HZ
SO
t LZ
13
8535B–SEEPR–7/08
4. AT25320B Ordering Information
Ordering Code
Voltage
Package
1.8
8P3
AT25320B-PU (Bulk form only)
(1)
(NiPdAu Lead Finish)
1.8
8S1
(2)
(NiPdAu Lead Finish)
1.8
8S1
(NiPdAu Lead Finish)
1.8
8A2
AT25320B-TH-T(2) (NiPdAu Lead Finish)
1.8
8A2
(2)
(NiPdAu Lead Finish)
1.8
8Y6
(2)
(NiPdAu Lead Finish)
1.8
8D3
(2)
(NiPdAu Lead Finish)
1.8
8U2-1
1.8
Die Sale
AT25320BN-SH-B
AT25320BN-SH-T
AT25320B-TH-B
(1)
AT25320BY6-YH-T
AT25320BD3-DH-T
AT25320BU2-UU-T
AT25320B-W-11(3)
Notes:
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
Industrial Temperature
(−40 to 85°C)
1. “B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon
request. Please contact Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
8D3
8-lead, 1.8 mm x 2.2 mm Body, Ultra Leadframe Land Grid Array (ULA)
8U2-1
8-lead, 8.35 mm x 3.73 mm Body, 0.75 mm Pitch, VFBGA Package (dBGA2)
Options
−1.8
14
Low Voltage (1.8 to 5.5V)
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
5. AT25640B Ordering Information
Ordering Code
Voltage
Package
1.8
8P3
AT25640B-PU (Bulk form only)
(1)
(NiPdAu Lead Finish)
1.8
8S1
(2)
(NiPdAu Lead Finish)
1.8
8S1
(NiPdAu Lead Finish)
1.8
8A2
AT25640B-TH-T(2) (NiPdAu Lead Finish)
1.8
8A2
(2)
(NiPdAu Lead Finish)
1.8
8Y6
(2)
(NiPdAu Lead Finish)
1.8
8D3
(2)
(NiPdAu Lead Finish)
1.8
8U2-1
1.8
Die Sale
AT25640BN-SH-B
AT25640BN-SH-T
AT25640B-TH-B
(1)
AT25640BY6-YH-T
AT25640BD3-DH-T
AT25640BU2-UU-T
AT25640B-W-11(3)
Notes:
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
Industrial Temperature
(−40 to 85°C)
1. “B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3mm)
8D3
8-lead, 1.8 mm x 2.2 mm Body, Ultra Leadframe Land Grid Array (ULA)
8U2-1
8-lead, 8.35 mm x 3.73 mm Body, 0.75 mm Pitch, VFBGA Package (dBGA2)
Options
−1.8
Low Voltage (1.8 to 5.5V)
15
8535B–SEEPR–7/08
6. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
NOM
MAX
NOTE
–
–
0.210
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
3
D1
0.005
–
–
3
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
e
0.100 BSC
eA
L
Notes:
MIN
0.300 BSC
0.115
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
Side View
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
17
8535B–SEEPR–7/08
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
E
E1
e
A2
D
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
18
4
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
8Y6 – Mini MAP
D2
A
b
(8X)
E
E2
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
A2
e (6X)
A1
1.50 REF.
COMMON DIMENSIONS
(Unit of Measure = mm)
A3
SYMBOL
MIN
D
2.00 BSC
E
3.00 BSC
MAX
D2
1.40
1.50
1.60
E2
-
-
1.40
A
-
-
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
A3
L
b
NOTE
0.20 REF
0.20
e
Notes:
NOM
0.30
0.40
0.50 BSC
0.20
0.25
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
10/16/07
R
2325 Orchard Parkway
San Jose, CA 95131
DRAWING NO.
TITLE
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
8Y6
Dual No Lead Package (DFN) ,(MLP 2x3)
REV.
D
19
8535B–SEEPR–7/08
8D3 - ULA
D
8
7
e1
6
b
5
L
E
PIN #1 ID
0.10
PIN #1 ID
0.15
1
2
3
4
A1
A
TOP VIEW
b
e
BOTTOM VIEW
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
A
–
–
0.40
A1
0.00
–
0.05
D
1.70
1.80
1.90
E
2.10
2.20
2.30
b
0.15
0.20
0.25
SYMBOL
e
0.40 TYP
e1
1.20 REF
L
0.25
0.30
NOTE
0.35
11/15/05
R
20
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe
Land Grid Array (ULA) D3
DRAWING NO.
REV.
8D3
0
AT25320B/640B
8535B–SEEPR–7/08
AT25320B/640B
8U2-1 - dBGA2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
A2
b
D
E
Notes:
1. This drawing is for general information.
2. Dimension 'b' is measured at the maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
e
e1
d
d1
Package Drawing Contact:
[email protected]
MIN
0.81
0.15
0.40
0.25
NOM
MAX
NOTE
0.91 1.00
0.20 0.25
0.45 0.50
0.30 0.35
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
GPC
TITLE
8U2-1, 8 ball, 2.35 x 3.73 mm Body, 0.75 mm pitch
GWW
VFBGA Package (dBGA2)
2/25/08
DRAWING NO. REV.
8U2-1
C
21
8535B–SEEPR–7/08
Revision History
22
Doc. Rev.
Date
Comments
8535B
7/2008
Modified ‘Endurance’ parameter on page 6
8535A
4/2008
Initial document release.
AT25320B/640B
8535B–SEEPR–7/08
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8535B–SEEPR–7/08