Fujitsu MB95D108BSPFM 8-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12617-1E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100B Series
MB95107B/F108BS/F108BW/R107B/D108BS/
MB95D108BW/FV100D-101
■ DESCRIPTION
The MB95100B series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB95100B Series
(Continued)
• Timer
• 8/16-bit compound timer × 2 channels
• 16-bit reload timer
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
• Timebase timer
• Watch prescaler (for dual clock product)
• FRAM
2K bytes FRAM is loaded (MB95R107B/MB95D108BS/MB95D108BW only)
• LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• I2C*
Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
• I/O port
• The number of maximum ports
• Single clock product : 55 ports
• Dual clock product : 53 ports
• Port configuration
• General-purpose I/O ports (N-ch open drain)
Other than MB95D108BS/MB95D108BW/MB95R107B : 6 ports
MB95D108BS/MB95D108BW/MB95R107B
: 4 ports
• General-purpose I/O ports (CMOS)
Single clock product
: 49 ports
Dual clock product
: 47 ports
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
2
MB95100B Series
■ PRODUCT LINEUP
Part number
MB95107B
MB95F108BS/
MB95F108BW
MB95R107B*3
MB95D108BS/
MB95D108BW
MASK ROM
product
Flash memory
product
MASK ROM
product
Flash memory
product
48K bytes
60K bytes
48K bytes
60K bytes
Parameter
Type
ROM capacity
RAM capacity
2K bytes
FRAM capacity
No
2K bytes
Option*4
Reset output
Clock system
Selectable
Single/Dual clock*1
Single/Dual clock*2
Low voltage
detection reset
CPU functions
Peripheral functions
No
Selectable
Single/Dual clock*1
Single/Dual clock*2
No
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 61.5 ns (at machine clock frequency 16.25 MHz)
: 0.6 µs (at machine clock frequency 16.25 MHz)
General purpose
I/O ports
• Single clock product : 55 ports (N-ch open drain *5 : 4/6 ports, CMOS : 49 ports)
• Dual clock product : 53 ports (N-ch open drain *5 : 4/6 ports, CMOS : 47 ports)
Timebase timer
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
I2C
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
Data transfer capable in UART/SIO
Full duplex double buffer, Variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN-UART
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
8/10-bit A/D
converter
(12 channels)
8-bit or 10-bit resolution can be selected.
(Continued)
3
MB95100B Series
(Continued)
Part number
MB95107B
Parameter
MB95F108BS/
MB95F108BW
MB95R107B*3
MB95D108BS/
MB95D108BW
Two clock modes and two counter operating modes can be selected. Square wave form
output
16-bit reload timer
Count clock : 7 internal clocks and external clock can be selected.
Counter operating mode : reload mode or one-shot mode can be selected.
Peripheral functions
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1
channel”.
8/16-bit compound
Built-in timer function, PWC function, PWM function, capture function and square
timer (2 channels)
wave form output
Count clock : 7 internal clocks and external clock can be selected.
16-bit PPG
(2 channels)
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1
channel”.
Counter operating clock : Eight selectable clock sources
Watch counter
(for dual clock
product)
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting
clock source 1 second and setting counter value to 60)
Watch prescaler
(for dual clock
product)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(12 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded AlgorithmTM *6
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Boot block configuration
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch (for dual clock product), and timebase timer
*1 : Specify clock mode when ordering MASK ROM.
*2 : MB95F108BS/MB95D108BS is single clock and MB95F108BW/MB95D108BW is dual clock.
*3 : This device is under development.
*4 : For details of option, refer to “■ MASK OPTION”.
*5 : MB95D108BS/D108BW/R107B contain 4 general-purpose I/O ports for N-ch open drain. Port number other
than MB95D108BS/D108BW/R107B has 6 general-purpose I/O ports for N-ch open drain.
*6 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of the evaluation products in MB95100B series is MB95FV100D-101. When using it, the MCU
board (MB2146-301A) is required.
4
MB95100B Series
■ SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY)
For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value
of main clock oscillation stabilization wait time from among the following four values.
Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabilization wait time at the maximum value.
Select of oscillation stabilization wait time
Remarks
(2 − 2) /FCH
0.5 µs (at main oscillation clock 4 MHz)
(212 − 2) /FCH
Approx. 1.02 ms (at main oscillation clock 4 MHz)
(213 − 2) /FCH
Approx. 2.05 ms (at main oscillation clock 4 MHz)
(2 − 2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
2
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
MB95107B
MB95R107B
MB95F108BS/F108BW
MB95D108BS/D108BW
MB95FV100D-101
FPT-64P-M03
FPT-64P-M09
BGA-224P-M08
: Available
: Unavailable
5
MB95100B Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The evaluation product has not only the functions of the MB95100B series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95100B series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
Flash memory and MASK ROM products, do not use these values in the program.
The evaluation product do not support the functions of some bits in single-byte registers. Read/write access to
these bits does not cause hardware malfunctions. The evaluation, Flash memory, and MASK ROM products are
designed to behave completely the same way in terms of hardware and software.
• Difference of Memory Spaces
If the amount of memory on the evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
The current consumption of Flash memory product is greater than for MASK ROM product.
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage are different among the evaluation, Flash memory, and MASK ROM products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Difference between RST and MOD pins
The input type of RST and MOD pins is CMOS input on the Flash memory product. The RST and MOD pins
are hysteresis inputs on the MASK ROM product. A pull - down resistor is provided for the MOD pin of the MASK
ROM product.
6
MB95100B Series
■ PIN ASSIGNMENT
AVss
P30/AN00
P31/AN01
P32/AN02
P33/AN03
P34/AN04
P35/AN05
P36/AN06
P37/AN07
P40/AN08
P41/AN09
P42/AN10
P43/AN11
P67/SIN
P66/SOT
P65/SCK
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc
AVR
PE3/INT13
PE2/INT12
PE1/INT11
PE0/INT10
P83
P82
P81
P80
P71/TI0
P70/TO0
MOD
X0
X1
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P64/EC1
P63/TO11
P62/TO10
P61/PPG11
P60/PPG10
P53/TRG1
P52/PPG1
P51/SDA0*2
P50/SCL0*2
P24/EC0
P23/TO01
P22/TO00
P21/PPG01
P20/PPG00
P14/PPG0
P13/TRG0/ADTG
Vcc
PG0
PG2/X1A*1
PG1/X0A*1
RST
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(FPT-64P-M03, FPT-64P-M09)
*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
*2 : P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW.
7
MB95100B Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
circuit
type*
1
AVCC
⎯
A/D converter power supply pin
2
AVR
⎯
A/D converter reference input pin
3
PE3/INT13
4
PE2/INT12
5
PE1/INT11
P
General-purpose I/O port
The pins are shared with the external interrupt input.
6
PE0/INT10
7
P83
8
P82
9
P81
O
General-purpose I/O port
10
P80
11
P71/TI0
12
P70/TO0
13
MOD
14
X0
15
X1
16
VSS
⎯
Power supply pin (GND)
17
VCC
⎯
Power supply pin
18
PG0
H
General-purpose I/O port.
19
PG2/X1A
20
PG1/X0A
21
RST
22
P00/INT00
23
P01/INT01
24
P02/INT02
25
P03/INT03
26
P04/INT04
27
P05/INT05
28
P06/INT06
29
P07/INT07
30
P10/UI0
H
B
A
H/A
Function
General-purpose I/O port.
The pin is shared with 16 - bit reload timer ch.0 input.
General-purpose I/O port.
The pin is shared with 16 - bit reload timer ch.0 output.
An operating mode designation pin
Main clock input oscillation pin
Main clock input/output oscillation pin
Single-system product is general-purpose port (PG2).
Dual-system product is sub clock input/output oscillation pin (32 kHz).
Single-system product is general-purpose port (PG1).
Dual-system product is sub clock input oscillation pin (32 kHz).
B’
Reset pin
C
General-purpose I/O port.
The pins are shared with external interrupt input. Large current port.
G
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input.
(Continued)
8
MB95100B Series
I/O
circuit
type*
Pin no.
Pin name
Function
31
P11/UO0
32
P12/UCK0
33
P13/TRG0/
ADTG
34
P14/PPG0
35
P20/PPG00
36
P21/PPG01
37
P22/TO00
38
P23/TO01
39
P24/EC0
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 clock input.
40
P50/SCL0
General-purpose I/O port (Except MB95R107B , MB95D108BS, and
MB95D108BW) .
The pin is shared with I2C ch.0 clock I/O.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D
converter trigger input (ADTG).
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.0 output.
H
I
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.0 output.
41
P51/SDA0
General-purpose I/O port (Except MB95R107B, MB95D108BS, and
MB95D108BW) .
The pin is shared with I2C ch.0 data I/O.
42
P52/PPG1
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 output.
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 trigger input.
43
P53/TRG1
44
P60/PPG10
45
P61/PPG11
46
P62/TO10
47
P63/TO11
48
P64/EC1
49
P65/SCK
General-purpose I/O port.
The pin is shared with LIN-UART clock I/O.
50
P66/SOT
General-purpose I/O port.
The pin is shared with LIN-UART data output.
51
P67/SIN
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.1 output.
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.1 output.
K
L
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.1 clock input.
General-purpose I/O port.
The pin is shared with LIN-UART data input.
(Continued)
9
MB95100B Series
(Continued)
Pin no.
Pin name
52
P43/AN11
53
P42/AN10
54
P41/AN09
55
P40/AN08
56
P37/AN07
57
P36/AN06
58
P35/AN05
59
P34/AN04
60
P33/AN03
61
P32/AN02
62
P31/AN01
63
P30/AN00
64
AVSS
I/O
circuit
type*
Function
J
General-purpose I/O port.
The pins are shared with A/D converter analog input.
J
General-purpose I/O port.
The pins are shared with A/D converter analog input.
⎯
A/D converter power supply pin (GND)
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
10
MB95100B Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1 (X1A)
A
Clock
input
N-ch
X0 (X0A)
Standby control
B
Mode input
R
• Oscillation circuit
• High-speed side
Feedback resistance value : approx. 1 MΩ
• Low-speed side
Feedback resistance : approx. 24 MΩ
(Evaluation product : approx. 10 MΩ)
Dumping resistance : approx. 144 kΩ
(Evaluation product : without dumping
resistance)
• Only for input
Hysteresis input only for MASK ROM product
With pull-down resistor only for MASK ROM
product
• Hysteresis input only for MASK ROM product
Reset input
B’
P-ch
N-ch
C
Digital output
Hysteresis
input
Standby control
External interrupt
enable
R
P-ch
Pull-up control
P-ch
G
N-ch
Digital output
•
•
•
•
CMOS output
CMOS input
Hysteresis input
With pull-up control
Digital output
CMOS input
Hysteresis
input
Standby control
Pull-up control
R
P-ch
P-ch
H
N-ch
Standby control
Digital output
• CMOS output
• Hysteresis input
• CMOS output
• Hysteresis input
• With pull-up control
Digital output
Digital output
Hysteresis
input
(Continued)
11
MB95100B Series
Type
Circuit
P-ch
N-ch
I
Remarks
•
•
•
Digital output •
N-ch open drain output
CMOS input
Hysteresis input
P-ch transistor is existed in MB95D108BS,
MB95D108BW, and MB95R107B.
CMOS input
Hysteresis
input
Standby control
R
P-ch
P-ch
•
•
Pull-up control
•
Digital output •
CMOS output
Hysteresis input
Analog input
With pull-up control
Digital output
J
N-ch
Analog input
Hysteresis
input
A/D control
Standby control
P-ch
K
N-ch
P-ch
N-ch
N-ch
Standby control
• CMOS output
Digital output • CMOS input
• Hysteresis input
Digital output
CMOS input
Hysteresis
input
Standby control
O
Digital output
Hysteresis
input
Standby control
L
• CMOS output
Digital output • Hysteresis input
• N-ch open drain output
Digital output • Hysteresis input
Hysteresis
input
(Continued)
12
MB95100B Series
(Continued)
Type
Circuit
Pull-up control
R
P-ch
P-ch
P
N-ch
Standby control
External
interrupt control
Remarks
• CMOS output
• Hysteresis input
• With pull-up control
Digital output
Digital output
Hysteresis
input
13
MB95100B Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pins.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC , AVR) and analog input voltage from exceeding
the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power-supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
■ PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent
damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is an unused output pin, make it open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
14
MB95100B Series
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as
to minimize the distance from the MOD pin to VCC or VSS pin and to provide a low-impedance connection.
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN11 pins.
• Precautions for Use of FRAM
When the device is connected to I2C external pins (SCL0 and SDA0) , the device with the same slave addresses
(1010000B to 1010111B) as built-in FRAM cannot be used.
When built-in FRAM is used without connecting the device to I2C external pins, external pull-up resistor (1.1kΩ
or more) should be connected to SCL0 and SDA0 pins.
P50 and P51 cannot be used in MB95R107B , MB95D108BS, and MB95D108BW.
15
MB95100B Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-64P-M03
TEF110-108F35AP
FPT-64P-M09
TEF110-108F36AP
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
Flash memory
CPU address
Programmer address*
1000H
71000H
1FFFH
2000H
71FFFH
72000H
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA2 (4K bytes)
Lower bank
SA1 (4K bytes)
SA3 (4K bytes)
SA4 (16K bytes)
SA6 (4K bytes)
SA7 (4K bytes)
Upper bank
SA5 (16K bytes)
SA8 (4K bytes)
SA9 (4K bytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to 17226.
2) Load program data to parallel programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer
16
MB95100B Series
■ BLOCK DIAGRAM
2
F MC-8FX CPU
RST
X0,X1
PG2/X1A*1
PG1/X0A*1
PG0
Reset control
ROM
RAM
Clock control
Interrupt control
Watch prescaler
Wild register
Watch counter
P00/INT00 to P07/INT07
External interrupt ch.0 to ch.7
16-bit PPG ch.1
P10/UI0
P11/UO0
UART/SIO
8/16-bit PPG ch.1
P12/UCK0
P14/PPG0
16-bit PPG ch.0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
8/16-bit PPG ch.0
8/16-bit compound
timer ch.1
LIN-UART
8/16-bit compound
timer ch.0
16-bit reload timer
P30/AN00 to P37/AN07
AVSS
P60/PPG10
P61/PPG11
P63/TO11
P64/EC1
P65/SCK
P24/EC0
P40/AN08 to P43/AN11
AVCC
P53/TRG1
P62/TO10
Internal bus
P13/TRG0/ADTG
P52/PPG1
P66/SOT
P67/SIN
P70/TO0
P71/TI0
P80 to P83
8/10-bit A/D
converter
External interrupt ch.8 to ch.11
PE0/INT10 to PE3/INT13
AVR
P50/SCL0*2
P51/SDA0*2
I 2C
FRAM*3
Port
Port
Other pins
MOD, VCC, VSS
*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
*2 : P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW.
*3 : MB95R107B, MB95D108BS, and MB95D108BW only
17
MB95100B Series
■ CPU CORE
1. Memory space
Memory space of the MB95100B series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95100B series is shown below.
• Memory Map
MB95F108BS
MB95F108BW
MB95D108BS
MB95D108BW
MB95107B
MB95R107B
0000H
0000H
I/O
I/O
0080H
RAM 2 Kbytes
0080H
RAM 2 Kbytes
MB95FV100D-101
0000H
I/O
0080H RAM 3.75 Kbytes
0100H Register
0100H Register
0100H Register
0200H
0200H
0200H
0880H
Access
prohibited
0F80H
0880H
Access
prohibited
0F80H
Extended I/O
Extended I/O
1000H
1000H
0F80H
Extended I/O
1000H
Access
prohibited
Flash
memory
60 Kbytes
4000H
Flash
memory
60 Kbytes
MASK ROM
48 Kbytes
FFFFH
18
FFFFH
FFFFH
MB95100B Series
2. Register
The MB95100B series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
: A 16-bit register for index modification
Extra pointer (EP)
: A 16-bit pointer to point to a memory address
Stack pointer (SP)
: A 16-bit register to indicate a stack area
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16-bit
: Program counter
FFFDH
A
: Accumulator
0000H
T
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
PC
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the program status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
PS
R4
R3
R2
RP
R1
R0
DP2
DP1
DP
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DP0
H
I
IL1
IL0
N
Z
V
C
CCR
19
MB95100B Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
"0"
"0"
"0"
"0"
"0"
"0"
OP code lower
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
Generated address A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
Interrupt level
Priority
High
0
0
0
0
1
1
1
0
2
1
1
3
N flag
Z flag
V flag
C flag
20
IL0
Low = no interruption
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
MB95100B Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8register. Up to a total of 32 banks can be used on the MB95100B series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
R0
Address 100H
R0
R0
R1
R2
R3
R4
R5
R6
107H
R1
R2
R3
R4
R5
R6
R7
R7
Bank 0
Memory area
R1
R2
R3
R4
R5
R6
1FFH
R7
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
21
MB95100B Series
■ FRAM
• Slave address of FRAM
FRAM operates as one of the slave devices connected to the I2C, and the I2C is used to read from or write to FRAM.
When data is transferred by the I2C, the slave address of FRAM is shown below.
Slave address (7 bits)
Slave ID (4 bits)
1
0
1
Page select bit* (3 bits)
0
000B : page 0
001B : page 1
010B : page 2
011B : page 3
100B : page 4
101B : page 5
110B : page 6
111B : page 7
R/W bit
(1 bit)
0 : at write
1 : at read
* : Page select bit : Set the value corresponding to the accessed page
• Memory configuration of FRAM
The capacitance of the built-in FRAM is 2 Kbytes. The memory configuration of FRAM consists of 8 pages as
follows. The capacitance of each page is 256 bytes.
Page
Address
Capacitance
22
0
00H to FFH
256 bytes
1
00H to FFH
256 bytes
2
00H to FFH
256 bytes
3
00H to FFH
256 bytes
4
00H to FFH
256 bytes
5
00H to FFH
256 bytes
6
00H to FFH
256 bytes
7
00H to FFH
256 bytes
MB95100B Series
• Single byte write
Start Condition
Address & Data
Stop Condition
Microcontroller
MSB
LSB
Slave Address 0
S
MSB
LSB
MSB
Address
A
FRAM
LSB
Data Byte
A
A
P
Acknowledge
• Compound byte write
Start Condition
Microcontroller
MSB
LSB
MSB
Slave Address 0
S
Stop Condition
Address & Data
LSB
Address
A
MSB
LSB
Data Byte
A
FRAM
MSB
LSB
Data Byte
A
A P
Acknowledge
• Current address read
Start Condition
No Acknowledge
Address
Microcontroller
MSB
S
Stop Condition
LSB
Slave Address 1
FRAM
MSB
LSB
A
Data Byte
Acknowledge
Data
1
P
• Continuous address read
Microcontroller
Start Condition
Address
Stop Condition
MSB
S
No Acknowledge
Acknowledge
LSB
Slave Address 1
FRAM
MSB
LSB
Data Byte
A
MSB
A
Acknowledge
LSB
Data Byte
1 P
Data
• Select (random) read
Start Condition
Address
Start Condition
Address
Microcontroller
MSB
LSB MSB
S Slave Address 0 A
LSB
Address
MSB
LSB
A S Slave Address 1 A
No Acknowledge
Acknowledge
MSB
LSB MSB
Data Byte
A
Stop
Condition
LSB
Data Byte
1 P
FRAM
Acknowledge
Data
Notes : • When the device is connected to I2C external pins (SCL0 and SDA0) , the device with the same addresses
(1010000B to 1010111B) as built-in FRAM cannot be used.
• When FRAM is used without connecting the device built into the pull-up resistor to I2C external pins,
external pull-up resistor (1.1 kΩ or more) should be connected to SCL0 and SDA0 pins.
• P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW.
23
MB95100B Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
⎯
(Disabled)
⎯
⎯
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H
PDR3
Port 3 data register
R/W
00000000B
0011H
DDR3
Port 3 direction register
R/W
00000000B
0012H
PDR4
Port 4 data register
R/W
00000000B
0013H
DDR4
Port 4 direction register
R/W
00000000B
0014H
PDR5
Port 5 data register
R/W
00000000B
0015H
DDR5
Port 5 direction register
R/W
00000000B
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
PDR7
Port 7 data register
R/W
00000000B
0019H
DDR7
Port 7 direction register
R/W
00000000B
001AH
PDR8
Port 8 data register
R/W
00000000B
001BH
DDR8
Port 8 direction register
R/W
00000000B
001CH
to
0025H
⎯
(Disabled)
⎯
⎯
0026H
PDRE
Port E data register
R/W
00000000B
0027H
DDRE
Port E direction register
R/W
00000000B
0028H,
0029H
⎯
(Disabled)
⎯
⎯
002AH
PDRG
Port G data register
R/W
00000000B
(Continued)
24
MB95100B Series
Address
Register
abbreviation
Register name
R/W
Initial value
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
⎯
(Disabled)
⎯
⎯
002DH
PUL1
Port 1 pull - up register
R/W
00000000B
002EH
PUL2
Port 2 pull - up register
R/W
00000000B
002FH
PUL3
Port 3 pull - up register
R/W
00000000B
0030H
PUL4
Port 4 pull - up register
R/W
00000000B
0031H
PUL5
Port 5 pull - up register
R/W
00000000B
0032H
PUL7
Port 7 pull - up register
R/W
00000000B
0033H
⎯
(Disabled)
⎯
⎯
0034H
PULE
Port E pull - up register
R/W
00000000B
0035H
PULG
Port G pull - up register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch.1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch.1
R/W
00000000B
003EH
TMCSRH0
16-bit reload timer control status register (Upper byte) ch.0
R/W
00000000B
003FH
TMCSRL0
16-bit reload timer control status register (Lower byte) ch.0
R/W
00000000B
0040H,
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG control status register (Upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG control status register (Lower byte) ch.0
R/W
00000000B
0044H
PCNTH1
16-bit PPG control status register (Upper byte) ch.1
R/W
00000000B
0045H
PCNTL1
16-bit PPG control status register (Lower byte) ch.1
R/W
00000000B
0046H,
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0/ch.1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2/ch.3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4/ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/ch.7
R/W
00000000B
004CH
EIC01
External interrupt circuit control register ch.8/ch.9
R/W
00000000B
004DH
EIC11
External interrupt circuit control register ch.10/ch.11
R/W
00000000B
(Continued)
25
MB95100B Series
Address
Register
abbreviation
Register name
R/W
Initial value
004EH,
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch.0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
0060H
IBCR00
I2C bus control register 0 ch.0
R/W
00000000B
0061H
IBCR10
I2C bus control register 1 ch.0
R/W
00000000B
0062H
IBSR0
I2C bus status register ch.0
R
00000000B
I C data register ch.0
R/W
00000000B
0063H
2
IDDR0
2
0064H
IAAR0
I C address register ch.0
R/W
00000000B
0065H
ICCR0
I2C clock control register ch.0
R/W
00000000B
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
(Continued)
26
MB95100B Series
Address
Register
abbreviation
Register name
R/W
Initial value
0078H
⎯
Mirror of register bank pointer (RP) and
direct bank pointer (DP)
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (Upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (Upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (Upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control register
ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control register
ch.1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
(Continued)
27
MB95100B Series
Address
Register
abbreviation
Register name
R/W
Initial value
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch.1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch.1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch.1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch.1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG start register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
TMRH0/
TMRLRH0
16-bit timer register (Upper byte) ch.0/
16-bit reload register (Upper byte) ch.0
R/W
00000000B
0FA7H
TMRL0/
TMRLRL0
16-bit timer register (Lower byte) ch.0/
16-bit reload register (Lower byte) ch.0
R/W
00000000B
0FA8H,
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (Upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (Lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (Upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (Lower byte) ch.0
R/W
11111111B
0FB0H
PDCRH1
16-bit PPG down counter register (Upper byte) ch.1
R
00000000B
0FB1H
PDCRL1
16-bit PPG down counter register (Lower byte) ch.1
R
00000000B
0FB2H
PCSRH1
16-bit PPG cycle setting buffer register (Upper byte) ch.1
R/W
11111111B
0FB3H
PCSRL1
16-bit PPG cycle setting buffer register (Lower byte) ch.1
R/W
11111111B
0FB4H
PDUTH1
16-bit PPG duty setting buffer register (Upper byte) ch.1
R/W
11111111B
0FB5H
PDUTL1
16-bit PPG duty setting buffer register (Lower byte) ch.1
R/W
11111111B
0FB6H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator
prescaler select register ch.0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator baud rate
setting register ch.0
R/W
00000000B
0FC0H,
0FC1H
⎯
(Disabled)
⎯
⎯
0FC2H
AIDRH
A/D input disable register (Upper byte)
R/W
00000000B
0FC3H
AIDRL
A/D input disable register (Lower byte)
R/W
00000000B
(Continued)
28
MB95100B Series
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FC4H
to
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
29
MB95100B Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
request
number
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch.1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch.1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
16-bit reload timer ch.0
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch.1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch.0
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
I2C ch.0
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
16-bit PPG ch.1
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch timer/Watch counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
High
External interrupt ch.8
External interrupt ch.9
External interrupt ch.10
External interrupt ch.11
30
Low
MB95100B Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
1
Power supply voltage*
Input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
AVCC
VSS − 0.3
VSS + 4.0
AVR
VSS − 0.3
VSS + 4.0
VI1
VSS − 0.3
VSS + 4.0
VI2
VSS − 0.3
VSS + 6.0
VO
VSS − 0.3
VSS + 4.0
V
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*4
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*4
IOL1
IOL2
“L” level average
current
⎯
“H” level maximum
output current
V
mA
mA
12
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
⎯
− 15
− 15
mA
−4
⎯
mA
−8
IOHAV2
*2
*2
ΣIOL
“H” level average
current
“H” level total average
output current
15
⎯
IOHAV1
“H” level total maximum
output current
15
V
4
IOLAV2
“L” level total average
output current
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Other than P80 to P83*3
P80 to P83
*3
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
(Continued)
31
MB95100B Series
(Continued)
Parameter
Symbol
Rating
Min
Max
Unit
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
− 55
+ 150
Storage temperature
°C
TSTG
− 40
+ 125
Remarks
MB95107B, MB95F108BS,
MB95F108BW
MB95R107B, MB95D108BS,
MB95D108BW
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVCC and VCC. AVR should not exceed AVCC + 0.3 V.
*3 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI1 rating.
*4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71,
PE0 to PE3, PG0
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The + B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
32
MB95100B Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply
voltage
A/D converter
reference input
voltage
Operating temperature
SymPin name Condition
bol
VCC,
AVCC
Value
Min
Max
Unit
Remarks
⎯
⎯
1.8*
3.3
At normal operating,
Flash memory product,
TA = −10 °C to +85 °C
⎯
⎯
1.8*
3.6
At normal operating,
MASK ROM product,
TA = −10 °C to +85 °C
⎯
⎯
2.0*
3.3
At normal operating,
Flash memory product,
TA = −40 °C to +85 °C
⎯
⎯
2.0*
3.6
At normal operating,
MASK ROM product,
TA = −40 °C to +85 °C
3.3
At normal operating,
Flash memory product,
At FRAM access,
TA = −40 °C to +85 °C
V
⎯
⎯
2.7
⎯
⎯
2.7
3.6
At normal operating,
MASK ROM product,
At FRAM access,
TA = −40 °C to +85 °C
⎯
⎯
2.6
3.6
MB95FV100D-101
TA = + 5 °C to +35 °C
⎯
⎯
1.5
3.3
Retain status in stop mode,
Flash memory product
⎯
⎯
1.5
3.6
Retain status in stop mode,
MASK ROM product
AVR
⎯
⎯
1.8
AVCC
V
TA
⎯
⎯
− 40
+ 85
°C
* : The values vary with the operating frequency.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
33
MB95100B Series
3. DC Characteristics
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
VIH1
Pin name
P10, P67
Conditions
*1
Value
Min
Typ
Max
0.7 VCC
⎯
VCC + 0.3
⎯
VIH2
P50, P51
⎯
Unit
V
VSS + 5.5
0.7 VCC
V
⎯
VCC + 0.3
Remarks
At selecting CMOS
input level
At selecting CMOS
input level
MB95F108BS,
MB95F108BW,
MB95107B,
MB95FV100D-101
At selecting CMOS
input level
MB95D108BS,
MB95D108BW,
MB95R107B
VIHS1
P00 to P07,
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
P52, P53,
P60 to P67,
P70, P71,
PE0 to PE3,
PG0, PG1*2,
PG2*2
*1
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
VIHS2
P80 to P83
*1
0.8 VCC
⎯
VSS + 5.5
V
Hysteresis input
V
Hysteresis input
MB95F108BS,
MB95F108BW,
MB95107B,
MB95FV100D-101
“H” level input
voltage
⎯
VIHS3
VIHM
P50, P51
⎯
VSS + 5.5
0.8 VCC
⎯
VSS + 5.0
Hysteresis input
MB95D108BS,
MB95D108BW,
MB95R107B
⎯
0.7 VCC
⎯
VCC + 0.3
V
CMOS input
(Flash memory
product)
⎯
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
(MASK ROM
product)
RST, MOD
(Continued)
34
MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
VIL
P10, P50, P51,
P67
VILS
P00 to P07,
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
P50 to P53,
P60 to P67,
P70, P71,
P80 to P83,
PE0 to PE3,
PG0, PG1*2,
PG2*2
“L” level input
voltage
VILM
Input leakage
current (Hi-Z
output leakage
current)
“H” level output
voltage
“L” level output
voltage
ILI
VOH1
Open-drain
output
application
voltage
Open-drain
output leakage
current
Max
*1
VSS − 0.3
⎯
0.3 VCC
V
At selecting CMOS
input level
(Hysteresis input)
*1
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
⎯
VSS − 0.3
⎯
0.3 VCC
V
CMOS input
(Flash memory
product)
⎯
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
(MASK ROM
product)
0.0 V < VI < VCC
−5
⎯
+5
µA
When the pull-up is
prohibition setting
Output pin other
IOH = − 4.0 mA
than P00 to P07
2.4
⎯
⎯
V
IOH = − 8.0 mA
2.4
⎯
⎯
V
Output pin other
IOL = 4.0 mA
than P00 to P07
⎯
⎯
0.4
V
IOL = 12 mA
⎯
⎯
0.4
V
VSS − 0.3
⎯
VSS + 5.5
RST, MOD
Port other than
P50, P51,
P80 to P83
P80 to P83
⎯
VSS + 5.5
VD2
P50, P51
⎯
VSS − 0.3
V
⎯
P50, P51,
P80 to P83
0.0 V < VI <
VSS + 5.5 V
⎯
⎯
5
MB95F108BS,
MB95F108BW,
MB95107B
MB95D108BS,
MB95D108BW,
MB95R107B
VCC + 0.3
ILIOD
Remarks
Typ
VOL2 P00 to P07
VD1
Unit
Min
VOH2 P00 to P07
VOL1
Value
µA
(Continued)
35
MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pull-up resistor RPULL
Pull-down
resistor
Input
capacitance
Pin name
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
VI = 0.0 V
P52, P53,
P70, P71,
PE0 to PE3,
PG0, PG1*2, PG2*2
RMOD MOD
CIN
Conditions
VI = VCC
Other than AVCC,
f = 1 MHz
AVSS, AVR, VCC, VSS
Value
ICC
FCH = 32 MHz
VCC (External clock FMP = 16 MHz
operation)
Main clock mode
(divided by 2)
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
When FRAM
read and write
(fSCL = 400 kHz)
100
kΩ
When the pull-up is
permission setting
50
100
kΩ
MASK ROM
product
5
15
pF
Max
25
50
25
⎯
11.0
14.0
MB95F108BS,
MB95F108BW
mA (at other than Flash
memory writing and
erasing)
⎯
30.0
35.0
MB95F108BS,
MB95F108BW
mA
(at Flash memory
writing and erasing)
⎯
7.3
10.0
mA MB95107B
22.4
MB95F108BS,
MB95F108BW
mA (at other than Flash
memory writing and
erasing)
⎯
Power supply
current*3
Remarks
Typ
⎯
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
Unit
Min
17.6
⎯
38.1
44.9
MB95F108BS,
MB95F108BW
mA
(at Flash memory
writing and erasing)
⎯
11.7
16.0
mA MB95107B
15.0
MB95D108BS,
MB95D108BW
mA (at other than Flash
memory writing and
erasing)
⎯
11.1
⎯
30
35
⎯
7.4
11.0
MB95D108BS,
MB95D108BW
mA
(at Flash memory
write and erase)
mA MB95R107B
(Continued)
36
MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
When FRAM read
and write
(fSCL = 400 kHz)
ICC
Value
Min
⎯
Typ
17.7
Max
Unit
Remarks
22.5
MB95D108BS,
MB95D108BW
mA (at other than Flash
memory writing and
erasing)
⎯
38.1
44.9
MB95D108BS,
MB95D108BW
mA
(at Flash memory
write and erase)
⎯
11.8
16.1
mA MB95R107B
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯
4.5
6.0
mA
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
⎯
7.2
9.6
mA
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
⎯
25
35
µA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯
7
15
µA
⎯
2
10
µA
ICCT
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯
1
5
µA MASK ROM product
⎯
10
14
mA
⎯
6.7
10.0
mA MASK ROM product
⎯
16.0
22.4
mA
⎯
10.8
16.0
mA MASK ROM product
ICCS
Power supply
current*3
Conditions
ICCL
ICCMPLL
VCC (External
clock operation)
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
Flash memory
product
Flash memory
product
Flash memory
product
(Continued)
37
MB95100B Series
(Continued)
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Value
Unit
Min
Typ
Max
⎯
190
250
µA
ICTS
VCC (External
FCH = 10 MHz
clock operation) Timebase timer
mode
TA = + 25 °C
⎯
0.4
0.5
mA
ICCH
Sub stop mode
TA = + 25 °C
⎯
1
5
µA
FCH = 10 MHz
At operating of A/D
conversion
⎯
1.3
2.2
mA
FCH = 10 MHz
At stopping of A/D
conversion
TA = + 25 °C
⎯
1
5
µA
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
ICCSPLL
Power supply
current*3
Conditions
IA
AVCC
IAH
Remarks
*1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR).
*2 : Single clock product only
*3 : Power supply current is regulated by external clock.
• Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
38
MB95100B Series
4. AC Characteristics
(1) Clock Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
SymPin name Conditions
bol
FCH
X0, X1
Clock frequency
FCL
Value
Unit
Remarks
⎯
16.25 MHz
When using main
oscillation circuit
1.00
⎯
32.50 MHz When using external clock
3.00
⎯
10.00 MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
3.00
⎯
4.06
MHz Main PLL multiplied by 4
⎯
32.768
⎯
kHz
When using sub PLL
Flash memory product :
kHz VCC = 2.3 V to 3.3 V
MASK ROM product :
VCC = 2.3 V to 3.6 V
Min
Typ
1.00
Max
X0A, X1A
⎯
32.768
⎯
61.5
⎯
1000
ns
When using main
oscillation circuit
30.8
⎯
1000
ns
When using external clock
When using sub
oscillation circuit,
When using external clock
⎯
tHCYL
X0, X1
Clock cycle time
Input clock pulse width
Input clock rise time
and fall time
When using sub
oscillation circuit
tLCYL
X0A, X1A
⎯
30.5
⎯
µs
tWH1
tWL1
X0
61.5
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
µs
When using external
clock, duty ratio is about
30% to 70%.
tCR
tCF
X0, X0A
⎯
⎯
10
ns
When using external clock
39
MB95100B Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock Input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
C1
C2
• Input wave form for using external clock (sub clock)
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of sub clock input port external connection
When using a crystal or
ceramic oscillator
Microcontroller
X0A
X1A
When using external clock
Microcontroller
X0A
FCL
X1A
Open
FCL
C1
40
C2
MB95100B Series
(2) Source Clock/Machine Clock
Parameter
Source clock cycle
time*1
(Clock before setting
division)
Source clock
frequency
Machine clock cycle
time*2
(Minimum instruction
execution time)
Machine clock
frequency
Sym- Pin
bol name
tSCLK
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Unit
Remarks
2000
ns
When using main clock
Min : FCH = 8.125 MHz, PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
⎯
61.0
µs
When using sub clock
Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
16.25
Min
Typ
Max
61.5
⎯
7.6
⎯
FSP
⎯
0.5
⎯
FSPL
⎯
16.384
⎯
100
⎯
32000
ns
When using main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6
⎯
976.5
µs
When using sub clock
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
0.031
⎯
16.250
1.024
⎯
131.072 kHz When using sub clock
tMCLK
FMP
FMPL
MHz When using main clock
131.072 kHz When using sub clock
⎯
⎯
MHz When using main clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follow.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follow.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
41
MB95100B Series
• Outline of clock generation block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
SCLK
(source clock)
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
42
Clock mode select bit
(SYCC: SCS1, SCS0)
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
(machine clock)
MB95100B Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95107B, MB95R107B
Sub PLL operation guarantee range
Sub clock mode and
watch mode
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
Operating voltage (V)
Operating voltage (V)
3.6
2.3
1.8
16.384 kHz
32 kHz
2.7
1.8
0.5 MHz 3 MHz
131.072 kHz
5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
2.3
1.8
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Operating voltage (V)
Operating voltage (V)
3.3
2.7
1.8
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
43
MB95100B Series
• Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C)
• MB95107B, MB95R107B
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
Operating voltage (V)
Operating voltage (V)
3.6
2.3
1.8
16.384 kHz
32 kHz
2.7
1.8
0.5 MHz 3 MHz 5 MHz
131.072 kHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
PLL operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
FRAM operating guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
Operating voltage (V)
Operating voltage (V)
3.3
2.3
2.0
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSPL)
44
2.7
2.0
0.5 MHz 3 MHz 5 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
MB95100B Series
• Operating voltage - Operating frequency (TA = + 5 °C to + 35 °C)
• MB95FV100D-101
FRAM, Main clock mode and main PLL
mode operation guarantee range
Sub PLL, Sub clock mode and watch
mode operation guarantee range
3.6
2.6
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSPL)
Operating voltage (V)
Operating voltage (V)
3.6
3.3
2.6
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
45
MB95100B Series
• Main PLL operation frequency
[MHz]
16.25
16
15
×4
12
Source clock frequency (Fsp)
× 2.5
10
×1
×2
7.5
6
5
3
0
3
4 4.062
5
6.4 6.5
Machine clock frequency (FMP)
46
8 8.125
10 [MHz]
MB95100B Series
(3) External Reset
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol
RST “L” level pulse
width
tRSTL
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns
At normal operating
Oscillation time of oscillator*2
+ 2 tMCLK*1
⎯
ns
At stop mode, sub clock mode,
sub sleep mode, and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
tRSTL
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
2 tMCLK
Oscillation time
Oscillation stabilization wait time
of oscillator
Execute instruction
Internal reset
47
MB95100B Series
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Power supply rising time
tR
Power supply cutoff time
tOFF
Value
Unit
Min
Max
⎯
⎯
36
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
Note : The power supply must be turned on within the selected oscillation stabilization time.
tR
tOFF
1.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
Hold Condition in stop mode
VSS
48
MB95100B Series
(5) Peripheral Input Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol
Pin name
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
INT00 to INT07,
INT10 to INT13,
EC0, EC1, TI0, TRG0/ADTG,
TRG1
Unit
Min
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
INT10 to INT13, EC0, EC1,
TI0, TRG0/ADTG, TRG1
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
49
MB95100B Series
(6) UART/SIO, Serial I/O Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Value
Conditions
Max
4 tMCLK*
⎯
ns
− 190
+ 190
ns
2 tMCLK*
⎯
ns
UCK0, UI0
2 tMCLK*
⎯
ns
tSHSL
UCK0
4 tMCLK*
⎯
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 tMCLK*
⎯
ns
UCK ↓ → UO time
tSLOV
UCK0, UO0
0
190
ns
Valid UI → UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
⎯
ns
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
⎯
ns
Internal clock
operation output pin :
CL = 80 pF + 1TTL.
External clock
operation output pin :
CL = 80 pF + 1TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
tSHSL
tSLSH
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
50
Unit
Min
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
MB95100B Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Serial clock cycle time
SCK ↑→ SOT delay time
SymPin name
bol
tSCYC
tSLOVI
Valid SIN→SCK↑
tIVSHI
SCK↑→ valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
Value
Conditions
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
SCK
Internal clock
SCK, SOT
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
SCK
SCK
SCK ↓→SOT delay time
tSLOVE SCK, SOT
Valid SIN→SCK↑
tIVSHE
SCK↑→ valid SIN hold time
tSHIXE
External clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
t
* + 190
MCLK 3
MCLK 3
t
⎯
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
51
MB95100B Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
SCK
0.8 VCC
0.8 VCC
0.2 VCC
tF
SOT
tSHSL
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
52
0.8 VCC
MB95100B Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Internal clock
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
t
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
* + 190
MCLK 3
Valid SIN→SCK↓
tIVSLI
SCK↓→ valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3 − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
⎯
ns
SCK, SOT
⎯
SCK↑ →SOT delay time
tSHOVE
Valid SIN→SCK↓
tIVSLE
SCK↓→ valid SIN hold time
tSLIXE
External clock
SCK, SIN operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
53
MB95100B Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
54
0.2 VCC
MB95100B Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Valid SIN→SCK↓
tIVSLI
SCK, SIN
SCK↓→ valid SIN hold time
tSLIXI
SCK, SIN
SOT→SCK↓ delay time
tSOVLI
SCK, SOT
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
0.8 VCC
0.2 VCC
0.8 V
tSHOVI
tSOVLI
tSLIXI
0.8 VCC
0.2 VCC
55
MB95100B Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
tSLOVI
Parameter
Value
Conditions
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN→SCK↑
tIVSHI
SCK↑ → valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operating output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT→SCK↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSHI
SIN
56
tSLOVI
0.8 VCC
0.2 VCC
tSHIXI
0.8 VCC
0.2 VCC
MB95100B Series
(8) I2C Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
SCL clock frequency
Pin name
Conditions
Standard-mode
Fast-mode
Min
Max
Min
Max
Unit
fSCL
SCL0
0
100
0
400
kHz
tHD;STA
SCL0
SDA0
4.0
⎯
0.6
⎯
µs
SCL clock “L” width
tLOW
SCL0
4.7
⎯
1.3
⎯
µs
SCL clock “H” width
tHIGH
SCL0
4.0
⎯
0.6
⎯
µs
(Repeat) Start condition setup time SCL ↑ → SDA ↓
tSU;STA
SCL0
SDA0
4.7
⎯
0.6
⎯
µs
Data hold time SCL ↓ → SDA
↓↑
tHD;DAT
SCL0
SDA0
0
3.45*2
0
0.9*3
µs
Data setup time SDA ↓ ↑ →
SCL ↑
tSU;DAT
SCL0
SDA0
0.25
⎯
0.1
⎯
µs
Stop condition setup time SCL
↑ → SDA ↑
tSU;STO
SCL0
SDA0
4
⎯
0.6
⎯
µs
tBUF
SCL0
SDA0
4.7
⎯
1.3
⎯
µs
(Repeat) Start condition hold
time SDA ↓ → SCL ↓
Bus free time between stop
condition and start condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
tWAKEUP
SDA0
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL0
tHD;STA
tSU;DAT
tSU;STA
tSU;STO
57
MB95100B Series
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Sym- Pin
bol name
Conditions
Value*2
Min
Max
Unit
Remarks
SCL clock
“L” width
tLOW
SCL0
(2 + nm / 2) tMCLK − 20
⎯
ns
Master mode
SCL clock
“H” width
tHIGH
SCL0
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
ns
Master mode
Start condition
SCL0
tHD;STA
hold time
SDA0
(−1 + nm / 2) tMCLK − 20
(−1 + nm) tMCLK + 20
ns
Master mode
Maximum value is
applied when m,
n = 1, 8.
Otherwise, the
minimum value is
applied.
Stop condition
SCL0
tSU;STO
setup time
SDA0
(1 + nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition
SCL0
tSU;STA
setup time
SDA0
(1 + nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Master mode
SCL0
SDA0
(2 nm + 4) tMCLK − 20
⎯
ns
SCL0
SDA0
3 tMCLK − 20
⎯
ns
Master mode
ns
Master mode
When assuming
that “L” of SCL is not
extended, the
minimum value is
applied to first bit of
continuous data.
Otherwise,
the maximum value
is applied.
Bus free time
between stop
condition and
start condition
tBUF
Data hold time tHD;DAT
R = 1.7 kΩ,
C = 50 pF*1
Data setup
time
tSU;DAT
SCL0
SDA0
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT
SCL0
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Minimum value is
applied to interrupt
at 9th SCL↓.
Maximum value is
applied to interrupt
at 8th SCL↓.
SCL clock “L”
width
tLOW
SCL0
4 tMCLK − 20
⎯
ns
At reception
SCL clock “H”
width
tHIGH
SCL0
4 tMCLK − 20
⎯
ns
At reception
Start condition
SCL0
tHD;STA
detection
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at
reception
(Continued)
58
MB95100B Series
(Continued)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin
name
Stop condition
detection
tSU;STO
Restart condition
detection condition
Parameter
Conditions
Value*2
Unit
Remarks
Min
Max
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at
reception
tSU;STA
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at
reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK − 20
⎯
ns
At reception
Data hold time
tHD;DAT
SCL0
SDA0 R = 1.7 kΩ,1
2 tMCLK − 20
⎯
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0
tLOW − 3 tMCLK − 20
⎯
ns
At slave transmission
mode
Data hold time
tHD;DAT
SCL0
SDA0
0
⎯
ns
At reception
Data setup time
tSU;DAT
SCL0
SDA0
tMCLK − 20
⎯
ns
At reception
SDA↓→SCL↑
(at wakeup function)
tWAKEUP
SCL0
SDA0
Oscillation stabilization
wait time +
2 tMCLK − 20
⎯
ns
C = 50 pF*
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : •
•
•
•
Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22) , (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
59
MB95100B Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 1.8 V to 3.3 V [Flash memory product], AVCC = VCC = 1.8 V to 3.6 V [MASK ROM product],
AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Unit
Min
Typ
Max
Resolution
⎯
⎯
10
bit
Total error
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Linearity error
⎯
Differential linear
error
Zero transition
voltage
Full-scale transition
voltage
Compare time
Sampling time
VOT
VFST
⎯
Remarks
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
V
Flash memory product :
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V
AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB
V
1.8 V ≤ AVCC < 2.7 V
AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB
V
Flash memory product :
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V
AVR − 2.5 LSB AVR − 0.5 LSB AVR + 1.5 LSB
V
1.8 V ≤ AVCC < 2.7 V
1.3
⎯
140
µs
Flash memory product :
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V
20
⎯
140
µs
1.8 V ≤ AVCC < 2.7 V
0.4
⎯
∞
µs
Flash memory product :
2.7 V ≤ AVCC ≤ 3.3 V
MASK ROM product :
2.7 V ≤ AVCC ≤ 3.6 V external impedance < at
1.8 kΩ
30
⎯
∞
µs
1.8 V ≤ AVCC < 2.7 V
external impedance <
at 14.8 kΩ
⎯
Analog input current
IAIN
−0.3
⎯
+ 0.3
µA
Analog input voltage
VAIN
AVSS
⎯
AVR
V
⎯
AVSS + 1.8
⎯
AVCC
V
AVR pin
IR
⎯
400
600
µA
AVR pin,
During A/D operation
IRH
⎯
⎯
5
µA
AVR pin,
At stop mode
Reference voltage
Reference voltage
supply current
60
Value
MB95100B Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input pin
Comparator
C
During sampling : ON
2.7 V ≤ AVCC ≤ 3.6 V
1.8 V ≤ AVCC < 2.7 V
R
1.7 kΩ (Max)
84 kΩ (Max)
C
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
AVCC ≥ 2.7 V
AVCC ≥ 1.8 V
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
40
External impedance [kΩ]
External impedance [kΩ]
AVCC ≥ 2.7 V
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
Minimum sampling time [µs]
• About errors
As |AVR − AVSS| becomes smaller, values of relative errors grow larger.
61
MB95100B Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
002H
VOT
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001H
001H
0.5 LSB
AVSS
AVR
Analog input
1 LSB =
AVR − AVSS
1024
(V)
AVSS
AVR
Analog input
Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) to N.
(Continued)
62
MB95100B Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
Actual conversion
characteristic
3FFH
Digital output
Digital output
004H
003H
002H
Ideal
characteristics
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
001H
Actual conversion
characteristic
3FCH
VOT (measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
3FEH
Actual conversion
characteristic
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
003H
Digital output
{1 LSB × N + VOT}
3FDH
Digital output
Ideal characteristics
N+1H
NH
N-1H
VNT
Actual conversion
characteristic
Ideal characteristics
002H
N-2H
001H
V (N+1)T
VOT (measurement value)
AVSS
AVR
AVSS
Analog input
Linear error in = VNT − {1 LSB × N + VOT}
1 LSB
digital output N
Analog input
Differential linear error =
in digital output N
V (N + 1) T − VNT
1 LSB
AVR
−1
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) to N.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
63
MB95100B Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
3.0*2
s
Excludes 00H programming prior erasure.
0.5*1
12.0*2
s
Excludes 00H programming prior erasure.
⎯
32
3600
µs
Excludes system-level overhead.
10000
⎯
⎯
cycle
Power supply voltage at
program/erase
2.7
⎯
3.3
V
Flash memory data retention
time
20*3
⎯
⎯
year
Min
Typ
Max
Sector erase time
(4K bytes sector)
⎯
0.2*1
Sector erase time
(16K bytes sector)
⎯
Byte programming time
Program/erase cycle
Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
7. FRAM Program Characteristics
Parameter
Unit
Min
Typ
Max
Read/write cycle*
1010
⎯
⎯
cycle
Power supply voltage at
read/write
2.7
⎯
3.6
V
Data retention time
10
⎯
⎯
year
* : Number of data read/write
64
Value
Remarks
TA = 0 °C to +55 °C
MB95100B Series
■ MASK OPTION
Part number
No.
Specifying procedure
1
Clock mode select*1
• Single-system clock mode
• Dual-system clock mode
2
FRAM*1
• With load of FRAM
• Without load of FRAM
MB95107B
MB95R107B
MB95F108BS
MB95D108BS
Specify when
Setting disabled
ordering MASK
MB95F108BW
MB95D108BW
MB95FV100D-101
Setting disabled
Setting disabled
Selectable
Single-system
clock mode
Dual-system
clock mode
Changing by the
switch on MCU
board
Specify by
part number
Specify by
part number
Specify by
part number
No
3
Low voltage detection reset*2
• With low voltage detection
reset
• Without low voltage
detection reset
No
No
No
No
4
Clock supervisor*2
• With clock supervisor
• Without clock supervisor
No
No
No
No
5
Selection of oscillation
stabilization wait time
• Selectable the initial value
of main clock oscillation
stabilization wait time
Selectable
1 : (22 − 2) /FCH
2 : (212 − 2) /FCH
3 : (213 − 2) /FCH
4 : (214 − 2) /FCH
Fixed to oscillation
stabilization wait
time of
(214 − 2) /FCH
Fixed to oscillation
stabilization wait
time of
(214 − 2) /FCH
Fixed to oscillation
stabilization wait
time of
(214 − 2) /FCH
*1 : Refer to table below about clock mode select and load of FRAM.
*2 : Low voltage detection reset and clock supervisor are options of 5-V products.
Part number
MB95107B/R107B
MB95F108BS
MB95D108BS
MB95F108BW
MB95D108BW
MB95FV100D-101
Clock mode select
Load of FRAM
Single-system
No
Dual-system
No
Single-system
Dual-system
No
Yes
No
Yes
Single-system
No
Dual-system
No
65
MB95100B Series
■ ORDERING INFORMATION
Part number
MB95107BPFV
MB95F108BSPFV
MB95F108BWPFV
MB95R107BPFV
MB95D108BSPFV
MB95D108BWPFV
64-pin plastic LQFP
(FPT-64P-M03)
MB95107BPFM
MB95F108BSPFM
MB95F108BWPFM
MB95R107BPFM
MB95D108BSPFM
MB95D108BWPFM
64-pin plastic LQFP
(FPT-64P-M09)
MB2146-301A
(MB95FV100D-101PBT)
66
Package
(
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
)
MB95100B Series
■ PACKAGE DIMENSIONS
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M03)
64-pin plastic LQFP
(FPT-64P-M03)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
32
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
64
0˚~8˚
17
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.50(.020)
C
0.20±0.05
(.008±.002)
0.08(.003)
M
2003 FUJITSU LIMITED F64009S-c-5-8
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
67
MB95100B Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12 × 12 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP64-12×12-0.65
(FPT-64P-M09)
64-pin plastic LQFP
(FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
64
17
1
0.65(.026)
C
"A"
16
0.32±0.05
(.013±.002)
0.13(.005)
0.10±0.10
(.004±.004)
(Stand off)
M
2003 FUJITSU LIMITED F64018S-c-3-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
68
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB95100B Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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representatives before ordering.
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circuit examples, in this document are presented solely for the
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Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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Please note that Fujitsu will not be liable against you and/or any
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If any products described in this document represent goods or
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Edited
Business Promotion Dept.
F0612