AD ADL5372ACPZ-R71 1500 mhz to 2500 mhz quadrature modulator Datasheet

1500 MHz to 2500 MHz
Quadrature Modulator
ADL5372
FEATURES
Output frequency range: 1500 MHz to 2500 MHz
Modulation bandwidth: >500 MHz (3 dB)
1 dB output compression: 14 dBm @ 1900 MHz
Noise floor: −158 dBm/Hz
Sideband suppression: −45 dBc @ 1900 MHz
Carrier feedthrough: −45 dBm @ 1900 MHz
Single supply: 4.75 V to 5.25 V
24-lead LFCSP_VQ
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
LOIP
LOIN
QUADRATURE
PHASE
SPLITTER
VOUT
APPLICATIONS
Cellular communication systems
CDMA2000/GSM/WCDMA
WiMAX/broadband wireless access systems
Satellite modems
06511-001
QBBN
QBBP
Figure 1.
GENERAL DESCRIPTION
The ADL5372 is a member of the fixed-gain quadrature modulator
(F-MOD) family designed for use from 1500 MHz to 2500 MHz.
Its excellent phase accuracy and amplitude balance enable high
performance intermediate frequency or direct radio frequency
modulation for communication systems.
The ADL5372 provides a >500 MHz, 3 dB baseband bandwidth,
making it ideally suited for use in broadband zero IF or low
IF-to-RF applications and in broadband digital predistortion
transmitters.
The ADL5372 accepts two differential baseband inputs and a
single-ended, local oscillator (LO) and generates a singleended output.
The ADL5372 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available in
a 24-lead, exposed-paddle, Pb-free, LFCSP. Performance is
specified over a −40°C to +85°C temperature range. A Pb-free
evaluation board is available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADL5372
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Modulator Interfacing ..................................................... 14
Applications....................................................................................... 1
Limiting the AC Swing .............................................................. 14
Functional Block Diagram .............................................................. 1
Filtering........................................................................................ 14
General Description ......................................................................... 1
Revision History ............................................................................... 2
Using the AD9779 Auxiliary DAC for Carrier Feedthrough
Nulling ......................................................................................... 15
Specifications..................................................................................... 3
GSM Operation .......................................................................... 15
Absolute Maximum Ratings............................................................ 5
WCDMA Operation .................................................................. 16
ESD Caution.................................................................................. 5
WiMAX Operation .................................................................... 16
Pin Configuration and Function Descriptions............................. 6
LO Generation Using PLLs ....................................................... 16
Typical Performance Characteristics ............................................. 7
Transmit DAC Options ............................................................. 17
Theory of Operation ...................................................................... 11
Modulator/Demodulator Options ........................................... 17
Circuit Description..................................................................... 11
Evaluation Board ............................................................................ 18
Basic Connections .......................................................................... 12
Characterization Setup .................................................................. 19
Optimization ............................................................................... 13
Outline Dimensions ....................................................................... 21
Applications Information .............................................................. 14
Ordering Guide .......................................................................... 21
REVISION HISTORY
12/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5372
SPECIFICATIONS
VS = 5 V; TA = 25°C; LO = 0 dBm 1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted.
Table 1.
Parameter
OPERATING FREQUENCY RANGE
LO = 1900 MHz
Output Power
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
GSM
WCDMA
LO = 2150 MHz
Output Power
OutputP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
WCDMA
LO = 2400 MHz
Output Power
OutputP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
WiMAX
Conditions
Low frequency
High frequency
Min
VIQ = 1.4 V p-p differential
POUT − (fLO + (2 × fBB)), POUT = 6.2 dBm
POUT − (fLO + (3 × fBB)), POUT = 6.2 dBm
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1 dBm per tone
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1 dBm per tone
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset; LO = 1960 MHz
6 MHz carrier offset, POUT = 5 dBm, PLO = 6 dBm; LO = 1960 MHz
Single carrier, 20 MHz carrier offset, POUT = −10 dBm,
PLO = 0 dBm; LO = 1966 MHz
VIQ = 1.4 V p-p differential
POUT − (fLO + (2 × fBB)), POUT = 6.2 dBm
POUT − (fLO + (3 × fBB)), POUT = 6.2 dBm
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1 dBm per tone
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1 dBm per tone
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset
Single carrier, 20 MHz carrier offset, POUT = −10 dBm, PLO = 0 dBm;
LO = 2140 MHz
VIQ = 1.4 V p-p differential
POUT − (fLO + (2 × fBB)), POUT = 6.2 dBm
POUT − (fLO + (3 × fBB)), POUT = 6.2 dBm
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1 dBm per tone
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1 dBm per tone
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset; LO = 2350 MHz
10 MHz carrier bandwidth (256 subcarriers), 64 QAM signal,
70 MHz carrier offset, POUT = −10 dBm, PLO = 0 dBm; LO = 2350 MHz
Rev. 0 | Page 3 of 24
Typ
1500
2500
Max
Unit
MHz
MHz
7.1
14.2
−45
−45
0.21
0.09
−50
−47
54
27
−158
dBm
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
−158
−157.6
dBc/Hz
dBm/Hz
7.2
14
−41
−44
0.27
0.12
−59
−48
65
26.5
−158
dBm
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
−157.5
dBm/Hz
5.6
12.4
−36
−40
0.6
0.13
−54
−48
57
24.5
−158.5
dBm
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
−158
dBm/Hz
ADL5372
Parameter
LO INPUTS
LO Drive Level1
Input Return Loss
BASEBAND INPUTS
I and Q Input Bias Level
Input Bias Current
Input Offset Current
Differential Input Impedance
Bandwidth (0.1 dB)
Bandwidth (1 dB)
POWER SUPPLIES
Voltage
Supply Current
1
2
Conditions
Min
Typ
Max
Unit
Characterization performed at typical level
See Figure 9 for a plot of return loss vs. frequency
Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN
−6
0
−12
+6
dBm
dB
500
45
0.1
2900
70
350
Current sourcing from each baseband input with a bias of 500 mV dc 2
LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc
LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc
Pin VPS1 and Pin VPS2
4.75
5.25
165
High LO drive reduces noise at a 6 MHz carrier offset in GSM applications.
See V-to-I Converter section for architecture information.
Rev. 0 | Page 4 of 24
mV
μA
μA
kΩ
MHz
MHz
V
mA
ADL5372
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPOS
IBBP, IBBN, QBBP, QBBN
LOIP and LOIN
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
0 V to 2 V
13 dBm
1100 mW
54°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL5372
24
23
22
21
20
19
QBBP
QBBN
COM4
COM4
IBBN
IBBP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
F-MOD
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
VPS5
VPS4
VPS3
VPS2
VPS2
VOUT
06511-002
1
2
3
4
5
6
COM2 7
LOIP 8
LOIN 9
COM2 10
COM3 11
COM3 12
COM1
COM1
VPS1
VPS1
VPS1
VPS1
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 2, 7, 10 to 12,
21, 22
3 to 6, 14 to 18
Mnemonic
COM1 to COM4
Description
Input Common Pins. Connect to ground plane via a low impedance path.
VPS1 to VPS5
8, 9
LOIP, LOIN
13
VOUT
19, 20, 23, 24
IBBP, IBBN, QBBN, QBBP
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 25).
50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled.
AC-couple LOIN to ground and drive LO through LOIP.
Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The output
is ground referenced.
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs
must be dc-biased to 500 mV dc and must be driven from a low impedance source.
Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a differential
drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and must be
externally biased.
Connect to ground plane via a low impedance path.
Exposed Paddle
Rev. 0 | Page 6 of 24
ADL5372
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V; TA = 25°C; LO = 0 dBm single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted.
16
9
8
OUTPUT P1dB (dBm)
12
6
TA = +25°C
5
TA = +85°C
4
3
TA = +25°C
10
TA = +85°C
8
6
1
2
0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 6. SSB Output P1dB Compression Point (OP1dB) vs. fLO and Temperature
16
9
VS = 5V
8
VS = 5V
14
7
OUTPUT P1dB (dBm)
12
6
5
VS = 5.25V
VS = 4.75V
4
3
VS = 5.25V
VS = 4.75V
10
8
6
2
0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
LO FREQUENCY (MHz)
06511-004
1
LO FREQUENCY (MHz)
Figure 7. SSB Output P1dB Compression Point (OP1dB) vs. fLO and Supply
Figure 4. Single Sideband (SSB) Output Power (POUT) vs.
LO Frequency (fLO) and Supply
90
5
60
1500MHz
S11 OF LOIP
S22 OF OUTPUT
150
30
0
180
0
2500MHz
1500MHz
2500MHz
330
210
100
1000
240
300
270
Figure 8. Smith Chart of LOIP S11 and VOUT S22
(fLO from 1600 MHz to 2500 MHz)
Figure 5. I and Q Input Bandwidth Normalized to
Gain @ 1 MHz (fLO = 1900 MHz)
Rev. 0 | Page 7 of 24
06511-043
10
BASEBAND FREQUENCY (MHz)
06511-005
OUTPUT POWER VARIANCE (dB)
120
1
06511-007
4
2
–5
06511-006
4
2
06511-003
SSB OUTPUT POWER (dBm)
7
Figure 3. Single Sideband (SSB) Output Power (POUT) vs.
LO Frequency (fLO) and Temperature
SSB OUTPUT POWER (dBm)
TA = –40°C
14
TA = –40°C
ADL5372
0
–10
–15
–20
–10
–20
–30
TA = –40°C
–40
–50
TA = +85°C
TA = +25°C
LO FREQUENCY (MHz)
06511-009
–25
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
–60
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
LO FREQUENCY (MHz)
Figure 12. Sideband Suppression vs. fLO and Temperature
Multiple Devices Shown
0
0
–10
–10
SIDEBAND SUPPRESSION (dBc)
–20
TA = –40°C
–40
–50
–60
TA = +25°C
–70
–60
–70
LO FREQUENCY (MHz)
Figure 13. Sideband Suppression vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
Figure 10. Carrier Feedthrough vs. fLO and Temperature
Multiple Devices Shown
0
SECOND-ORDER DISTORTION, THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
–20
–10
–20
TA = +85°C
TA = –40°C
–40
–50
–60
–70
TA = +25°C
–90
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
LO FREQUENCY (MHz)
–30
15
SSB OUTPUT POWER (dBm)
CARRIER
FEEDTHROUGH (dBm)
10
5
–40
0
–50
SIDEBAND SUPPRESSION (dBc)
–5
–60
SECOND ORDER (dBc)
–10
–70
THIRD ORDER (dBc)
–80
06511-040
CARRIER FEEDTHROUGH (dBm)
–50
TA = –40°C
TA = +25°C
–90
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
06511-010
LO FREQUENCY (MHz)
–80
–40
–80
–80
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
–30
TA = +85°C
–30
06511-041
–30
TA = +85°C
–20
SSB OUTPUT POWER (dBm)
CARRIER FEEDTHROUGH (dBm)
Figure 9. Return Loss (S11) of LOIP
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
–15
3.4
BASEBAND INPUT VOLTAGE (V p–p)
Figure 11. Carrier Feedthrough vs. fLO and Temperature after Nulling at 25°C
Multiple Devices Shown
Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 1900 MHz)
Rev. 0 | Page 8 of 24
06511-014
RETURN LOSS (dB)
–5
06511-012
SIDEBAND SUPPRESSION (dBc)
0
ADL5372
15
30
–40
5
–50
0
SIDEBAND SUPPRESSION (dBc)
THIRD ORDER (dBc)
–60
SECOND ORDER (dBc)
–70
0.6
1.0
1.4
1.8
2.2
2.6
3.0
–15
3.4
BASEBAND INPUT VOLTAGE (V p-p)
15
10
5
0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
LO FREQUENCY (MHz)
Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level
(fLO = 2150 MHz)
Figure 18. OIP3 vs. Frequency and Temperature
THIRD ORDER
TA = +25°C
–30
THIRD ORDER
TA = +85°C
THIRD ORDER
TA = –40°C
–50
–60
–70
SECOND ORDER
TA = +85°C
SECOND ORDER
TA = –40°C
SECOND ORDER
TA = +25°C
–80
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
LO FREQUENCY (MHz)
60
50
40
20
10
LO FREQUENCY (MHz)
6
THIRD ORDER (dBc)
–45
5.5
–50
5
CARRIER FEEDTHROUGH (dBm)
–55
SSB OUTPUT POWER (dBm)
6.5
SIDEBAND SUPPRESSION (dBc)
4.5
SECOND ORDER (dBc)
–60
1M
10M
BASEBAND FREQUENCY (Hz)
4
100M
SECOND-ORDER DISTORTION, THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
–20
Figure 17. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. fBB and Temperature (fLO = 1900 MHz)
8
SSB OUTPUT POWER (dBm)
–30
–40
7
CARRIER
FEEDTHROUGH (dBm)
6
SIDEBAND SUPPRESSION (dBc)
–50
5
THIRD ORDER (dBc)
SECOND ORDER (dBc)
–60
–70
–6
06511-017
SECOND-ORDER DISTORTION, THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
7
SSB OUTPUT POWER (dBm)
–35
–40
Figure 19. OIP2 vs. Frequency and Temperature
7.5
–30
TA = –40°C
0
1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500
8
–25
TA = +85°C
30
Figure 16. Second- and Third-Order Distortion vs. fLO and Temperature
(Baseband I/Q Amplitude = 1.4 V p-p Differential)
–20
TA = +25°C
70
06511-019
OUTPUT SECOND-ORDER INTERCEPT (dBm)
80
06511-016
SECOND-ORDER AND THIRD-ORDER
DISTORTION (dBc)
–20
–40
TA = +85°C
TA = –40°C
4
–4
–2
0
2
4
6
SSB OUTPUT POWER (dBm)
0.2
–10
TA = +25°C
20
3
LO AMPLITUDE (dBm)
Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 1900 MHz)
Rev. 0 | Page 9 of 24
06511-020
–80
–5
25
06511-018
10
CARRIER
FEEDTHROUGH (dBm)
SSB OUTPUT POWER (dBm)
–30
OUTPUT THIRD-ORDER INTERCEPT (dBm)
SSB OUTPUT POWER (dBm)
06511-015
SECOND-ORDER DISTORTION, THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
–20
ADL5372
22
fLO = 1960MHz
20
8
SSB OUTPUT POWER (dBm)
16
CARRIER
FEEDTHROUGH (dBm)
7
14
6
–40
–50
5
SIDEBAND SUPPRESSION (dBc)
–60
THIRD ORDER (dBc)
4
SECOND ORDER (dBc)
QUANTITY
SSB OUTPUT POWER (dBm)
–30
18
10
6
4
2
–4
–2
0
2
4
6
LO AMPLITUDE (dBm)
Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough,
Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 2150 MHz)
0.20
0.19
0.18
VS = 5.25V
0.17
VS = 5V
0.16
VS = 4.75V
0.15
0.14
0.13
0.12
0.10
–40
–15
10
35
60
TEMPERATURE (°C)
85
06511-042
0.11
Figure 22. Power Supply Current vs. Temperature
Rev. 0 | Page 10 of 24
NOISE AT 20MHz OFFSET (dBm/Hz)
–157.1
–157.3
–157.5
–157.7
–157.9
–158.1
–158.3
–158.5
–158.7
–158.9
3
06511-023
–6
–159.1
0
–70
SUPPLY CURRENT (A)
12
8
06511-021
SECOND-ORDER DISTORTION, THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
–20
Figure 23. 20 MHz Offset Noise Floor Distribution at fLO = 1960 MHz
(I/Q Amplitude = 0 mV p-p with 500 mV dc Bias)
ADL5372
THEORY OF OPERATION
CIRCUIT DESCRIPTION
V-to-I Converter
Overview
The differential baseband inputs (QBBP, QBBN, IBBN, and
IBBP) consist of the bases of PNP transistors, which present a
high impedance. The voltages applied to these pins drive the
V-to-I stage that converts baseband voltages into currents. The
differential output currents of the V-to-I stages feed each of their
respective Gilbert-cell mixers. The dc common-mode voltage at
the baseband inputs sets the currents in the two mixer cores.
Varying the baseband common-mode voltage influences the
current in the mixer and affects overall modulator performance.
The recommended dc voltage for the baseband common-mode
voltage is 500 mV dc.
The ADL5372 can be divided into five circuit blocks: the LO
interface, the baseband voltage-to-current (V-to-I) converter,
the mixers, the differential-to-single-ended (D-to-S) stage, and
the bias circuit. A detailed block diagram of the device is shown
in Figure 24.
LOIP
LOIN
PHASE
SPLITTER
Mixers
IBBP
IBBN
Σ
06511-024
QBBP
OUT
QBBN
Figure 24. Block Diagram
The LO interface generates two LO signals in quadrature. These
signals are used to drive the mixers. The I and Q baseband input
signals are converted to currents by the V-to-I stages, which
then drive the two mixers. The outputs of these mixers combine
to feed the output balun, which provides a single-ended output.
The bias cell generates reference currents for the V-to-I stage.
LO Interface
The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase. The LO can be driven either single-ended or
differentially. When driven single-ended, the LOIN pin should
be ac grounded via a capacitor. Each quadrature LO signal then
passes through a limiting amplifier that provides the mixer with
a limited drive signal.
The ADL5372 has two double-balanced mixers: one for the
in-phase channel (I-channel) and one for the quadrature
channel (Q-channel). Both mixers are based on the Gilbert-cell
design of four cross-connected transistors. The output currents
from the two mixers sum together into a load. The signal
developed across this load is used to drive the D-to-S stage.
D-to-S Stage
The output D-to-S stage consists of an on-chip balun that
converts the differential signal to a single-ended signal. The
balun presents high impedance to the output (VOUT). Hence, a
matching network may be needed at the output for optimal
power transfer.
Bias Circuit
An on-chip band gap reference circuit is used to generate a
proportional-to-absolute temperature (PTAT) reference current
for the V-to-I stage.
Rev. 0 | Page 11 of 24
ADL5372
BASIC CONNECTIONS
Baseband Inputs
Figure 25 shows the basic connections for the ADL5372.
IBBP
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs may
range from 400 mV to 600 mV. This results in a reduction in
the usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5372 input range and on the top end by the output compliance
range on most DACs from Analog Devices.
C16
0.1µF
19 IBBP
20 IBBN
IBBN
21 COM4
QBBN
22 COM4
24
QBBP
QBBN
23
QBBP
VPOS
C15
0.1µF
COM1
1
COM1
2
VPS1
3
VPS1
4
VPS1
VPS1
18
Z1
F-MOD
17
16
5
EXPOSED PADDLE
6
C12
0.1µF
VPS5
VPS2
14
VPS2
VOUT
A single-ended LO signal should be applied to the LOIP pin
through an ac coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.
VPOS
C11
OPEN
VOUT
12
C13
0.1µF
COM3
10
11
COM3
COM2
9
LOIN
8
LOIP
7
COUT
100pF
COM2
C14
0.1µF
VPS3
15
13
LO Input
VPS4
GND
CLON
100pF
LO
06511-025
CLOP
100pF
Figure 25. Basic Connections for the ADL5372
Power Supply and Grounding
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Application Note AN-772 discusses the
thermal and electrical grounding of the LFCSP in detail.
The nominal LO drive of 0 dBm can be increased to up to 6 dBm
to realize an improvement in the noise performance of the
modulator. This improvement is tempered by degradation in
the sideband suppression performance (see Figure 20) and,
therefore, should be used judiciously. If the LO source cannot
provide the 0 dBm level, then operation at a reduced power
below 0 dBm is acceptable. Reduced LO drive results in slightly
increased modulator noise. The effect of LO power on sideband
suppression and carrier feedthrough is shown in Figure 20. The
effect of LO power on GSM noise is shown in Figure 35.
RF Output
The RF output is available at the VOUT pin (Pin 13). The
VOUT pin connects to an internal balun, which is capable of
driving a 50 Ω load. For applications requiring 50 Ω output
impedance, external matching is needed (see Figure 8 for S22
performance). The internal balun provides a low dc path to
ground. In most situations, the VOUT pin should be ac-coupled
to the load.
Rev. 0 | Page 12 of 24
ADL5372
OPTIMIZATION
The carrier feedthrough and sideband suppression performance
of the ADL5372 can be improved by using optimization
techniques.
It is often desirable to perform a one-time carrier null calibration. This is usually performed at a single frequency. Figure 27
shows how carrier feedthrough varies with LO frequency over a
range of ±50 MHz on either side of a null at 1900 MHz.
–30
Carrier Feedthrough Nulling
–60
CARRIER FEEDTHROUGH (dBm)
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
1850 1860 1870 1880 1890 1900 1910 1920 1930 1940 1950
LO FREQUENCY (MHz)
06511-022
Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
modulator, the quantities (VIOPP − VIOPN) and (VQOPP − VQOPN)
are equal to zero, which results in no carrier feedthrough. In a real
modulator, those two quantities are nonzero; and, when mixed
with the LO, they result in a finite amount of carrier feedthrough.
The ADL5372 is designed to provide a minimal amount of carrier
feedthrough. Should even lower carrier feedthrough levels be
required, minor adjustments can be made to the (VIOPP − VIOPN)
and (VQOPP − VQOPN) offsets. The I-channel offset is held constant
while the Q-channel offset is varied until a minimum carrier
feedthrough level is obtained. The Q-channel offset required to
achieve this minimum is held constant, while the offset on the
I-channel is adjusted until a new minimum is reached. Through
two iterations of this process, the carrier feedthrough can be
reduced to as low as the output noise. The ability to null is
sometimes limited by the resolution of the offset adjustment.
Figure 26 shows the relationship of carrier feedthrough vs. dc
offset as null.
Figure 27. Carrier Feedthrough vs. Frequency After Nulling at 1900 MHz
Sideband Suppression Optimization
Sideband suppression results from relative gain and relative
phase offsets between the I-channel and Q-channel and can
be suppressed through adjustments to those two parameters.
Figure 28 illustrates how sideband suppression is affected by
the gain and phase imbalances.
0
–10
–72
–76
–80
–88
–300 –240 –180 –120
06511-045
–84
–60
0
60
120
180
240
300
The same applies to the Q channel.
–70
0dB
0.1
1
10
100
PHASE ERROR (Degrees)
Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied
VIOPP = 500 mV + VIOS/2, and
VIOPN = 500 mV − VIOS/2, such that
VIOPP − VIOPN = VIOS
–50 0.05dB
0.025dB
–60 0.0125dB
–90
0.01
Figure 26. Carrier Feedthrough vs. DC Offset Voltage at 1900 MHz
When an offset of +VIOS is applied to the I-channel inputs
–30 0.5dB
0.25dB
–40 0.125dB
–80
VP – VN OFFSET (µV)
VIOPP = VIOPN = 500 mV, or
VIOPP − VIOPN = VIOS = 0 V
2.5dB
–20 1.25dB
06511-028
–68
SIDEBAND SUPPRESSION (dBc)
CARRIER FEEDTHROUGH (dBm)
–64
Figure 28. Sideband Suppression vs. Quadrature Phase Error for
Various Quadrature Amplitude Offsets
Figure 28 underlines the fact that adjusting only one parameter
improves the sideband suppression only to a point, unless the
other parameter is also adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance better than 1°
does not yield any improvement in the sideband suppression. For
optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.
The sideband suppression nulling can be performed either through
adjusting the gain for each channel or through the modification
of the phase and gain of the digital data coming from the digital
signal processor.
Rev. 0 | Page 13 of 24
ADL5372
APPLICATIONS INFORMATION
AD9779
The ADL5372 is designed to interface with minimal components
to members of the Analog Devices family of DACs. These DACs
feature an output current swing from 0 to 20 mA, and the
interface described in this section can be used with any DAC
that has a similar output.
OUT1_P
AD9779
OUT1_N
19
IBBP
RBIP
50Ω
OUT2_N
OUT2_P
RBIN
50Ω
84
RBQN
50Ω
RBQP
50Ω
83
OUT2_P
92
IBBP
RSLI
100Ω
RBIN
50Ω
20
84
23
RBQN
50Ω
RBQP
50Ω
83
IBBN
QBBN
RSLQ
100Ω
24
QBBP
Figure 30. AC Voltage Swing Reduction Through the Introduction
of a Shunt Resistor Between Differential Pair
The value of this ac voltage swing limiting resistor is chosen
based on the desired ac voltage swing. Figure 31 shows the
relationship between the swing-limiting resistor and the peakto-peak ac swing that it produces when 50 Ω bias-setting
resistors are used.
2.0
20
23
24
1.8
IBBN
QBBN
QBBP
06511-029
OUT1_N
92
OUT2_N
Figure 29. Interface Between the AD9779 and ADL5372 with 50 Ω Resistors to
Ground to Establish the 500 mV DC Bias for the ADL5372 Baseband Inputs
DIFFERENTIAL SWING (V p-p)
OUT1_P
F-MOD
93
19
RBIP
50Ω
Driving the ADL5372 with a TxDAC®
An example of the interface using the AD9779 TxDAC is shown
in Figure 29. The baseband inputs of the ADL5372 require a dc
bias of 500 mV. The average output current on each of the
outputs of the AD9779 is 10 mA. Therefore, a single 50 Ω
resistor to ground from each of the DAC outputs results in an
average current of 10 mA flowing through each of the resistors,
thus producing the desired 500 mV dc bias for the inputs to the
ADL5372.
F-MOD
93
06511-030
DAC MODULATOR INTERFACING
1.6
1.4
1.2
1.0
0.8
0.6
0.4
LIMITING THE AC SWING
There are situations in which it is desirable to reduce the ac
voltage swing for a given DAC output current. This can be
achieved through the addition of another resistor to the interface.
This resistor is placed in the shunt between each side of the
differential pair, as shown in Figure 30. It has the effect of
reducing the ac swing without changing the dc bias already
established by the 50 Ω resistors.
0
10
100
1000
RL (Ω)
10000
06511-031
0.2
The AD9779 output currents have a swing that ranges from 0 to
20 mA. With the 50 Ω resistors in place, the ac voltage swing
going into the ADL5372 baseband inputs ranges from 0 V to 1 V.
A full-scale sine wave out of the AD9779 can be described as a
1 V p-p single-ended (or 2 V p-p differential) sine wave with a
500 mV dc bias.
Figure 31. Relationship Between the AC Swing-Limiting Resistor and the
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
FILTERING
It is necessary to low-pass filter the DAC outputs to remove
images when driving a modulator. The interface for setting up
the biasing and ac swing that was discussed in the Limiting the
AC Swing section lends itself well to the introduction of such a
filter. The filter can be inserted between the dc bias setting
resistors and the ac swing-limiting resistor. Doing so establishes
the input and output impedances for the filter.
Rev. 0 | Page 14 of 24
ADL5372
OUT2_N
92
RBIN
50Ω
RSLI
100Ω
20
IBBN
LNI
2.7nH
LNQ
2.7nH
84
RBQN
50Ω
OUT2_P
1.1nF
C2I
RBQP
83 50Ω
1.1nF
C1Q
1.1nF
C2Q
3.5
–40
3.0
–50
IBBP
23
QBBN
2.5
PEAK EVM
–60
2.0
400kHz
–70
1.5
600kHz
–80
RSLQ
100Ω
0.5
24
QBBP
LPQ
2.7nH
0
–6
OUT1_P
OUT1_N
90
250Ω
93
RBIP
50Ω
RBIN
92 50Ω
1.1nF
C1I
1.1nF
C2I
19
IBBP
RSLI
100Ω
20
250Ω
AUX1_N
F-MOD
LPI
2.7nH
LNI
2.7nH
2
4
6
4.0
–80
3.5
–85
PEAK EVM
3.0
–90
2.5
–95
2.0
–100
6MHz NOISE FLOOR
1.5
–105
RMS EVM
1.0
–110
0.5
–115
0
–120
–6
–4
–2
0
2
4
6
LO DRIVE (dBm)
Figure 35. GSM EVM and 6 MHz Noise Floor vs. LO Power at 1960 MHz;
Output Power = 5 dBm
87
250Ω
84
RBQN
50Ω
RBQP
83 50Ω
86
1.1nF
C1Q
LNQ
2.7nH
1.1nF
C2Q
23
RSLQ
100Ω
24
250Ω
LPQ
2.7nH
Figure 35 illustrates that an LO amplitude of 3 dBm provides
the ideal operating point for noise and EVM for a GSM signal
at 1960 MHz.
QBBN
QBBP
500Ω
06511-033
500Ω
AUX2_P
0
Figure 35 shows the GSM EVM and noise performance vs. the
LO amplitude at 1960 MHz with an output power of 5 dBm.
Increasing the LO drive level improves the noise performance
but degrades EVM performance.
89
AUX2_N
OUT2_P
–2
IBBN
500Ω
OUT2_N
–110
–4
OUTPUT POWER (dBm)
PEAK AND RMS EVM (%)
The AD9779 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each main
DAC channel. This feature can be used to produce the small
offset voltages necessary to null out the carrier feedthrough
from the modulator. Figure 33 shows the interface required
to use the auxiliary DACs. This adds four resistors to the
interface.
500Ω
–100
6 MHz NOISE FLOOR
Figure 34. GSM EVM and Spectral Performance vs. Channel Power at
1960 MHz vs. Output Power; LO Power = 0 dBm
USING THE AD9779 AUXILIARY DAC FOR CARRIER
FEEDTHROUGH NULLING
AUX1_P
–90
RMS EVM
Figure 32. DAC Modulator Interface with
3 MHz Third-Order, Elliptical Low-Pass Filter
AD9779
1.2MHz
1.0
06511-026
OUT1_N
1.1nF
C1I
19
6MHz OFFSET NOISE FLOOR (dBc/100kHz)
RBIP
50Ω
250kHz
Figure 33. DAC Modulator Interface with Auxiliary DAC Resistors
Rev. 0 | Page 15 of 24
06511-027
93
–30
4.0
F-MOD
LPI
2.7nH
PEAK AND RMS EVM (%)
OUT1_P
Figure 34 shows the GSM EVM, spectral mask, and noise vs. the
output power for the ADL5372 at 1960 MHz. For a given LO
amplitude, the performance is independent of output power.
06511-032
AD9779
GSM OPERATION
250kHz, 400kHz, 600kHz AND 1200kHz
SPECTRAL MASK (dBc/30kHz)
6MHz OFFSET NOISE FLOOR (dBc/100kHz)
An example is shown in Figure 32 with a third-order, elliptical,
low-pass filter with a 3 dB frequency of 3 MHz. Matching input
and output impedances makes the filter design easier, so the
shunt resistor chosen is 100 Ω, producing an ac swing of
1 V p-p differential.
–153
The ADL5372 is suitable for operation in a WCDMA
environment, providing better than 72.5 dB of adjacent channel
power ratio (ACPR) at an output power of −10 dBm, with a
20 MHz noise floor of −157 dBm/Hz. Figure 36 and Figure 37
show the ACPR and 20 MHz offset noise floor of the ADL5372
vs. the output power at LO frequencies of 1966 MHz and
2140 MHz, respectively.
–60
–154
–62
–155
–64
–156
–156.0
–74
–76
–156.5
20MHz NOISE FLOOR
ALTERNATE CPR
–157.0
–78
–157.5
–80
–158.0
–82
–14
–13
–12
–11
–10
–9
–8
20MHz OFFSET NOISE FLOOR (dBm/Hz)
ADJACENT CPR
–72
–158.5
–7
POUT (dBm)
Figure 36. WCDMA Adjacent and Alternate Channel Power ratios and
20 MHz Offset Noise Floor vs. Output Power at 1966 MHz; LO Power = 0 dBm
–72
–156.0
ADJACENT CPR
–156.5
–74
–76
–157.0
20MHz NOISE FLOOR
–157.5
–78
ALTERNATE CPR
–158.0
–80
–82
–14
–13
–12
–11
–10
–9
–8
20MHz OFFSET NOISE FLOOR (dBm/Hz)
–155.5
–158.5
–7
POUT (dBm)
Figure 37. WCDMA Adjacent and Alternate Channel Power and 20 MHz
Offset Noise Floor vs. Output Power at 2140 MHz; LO Power = 0 dBm
WiMAX OPERATION
Figure 38 demonstrates the ACPR vs. the output power for the
ADL5372 at 2350 MHz. The following test conditions were
applied: a 10 MHz wide 64-QAM OFDM signal with 256
subcarriers, and a raised cosine filter with an α = 0.2.
06511-035
ADJACENT AND ALTERNATE CHANNEL
POWER RATIOS (dB)
–70
–157
ACPR
–68
–155.5
06511-034
ADJACENT AND ALTERNATE CHANNEL
POWER RATIOS (dB)
–70
–66
–158
–70
–159
70MHz OFFSET NOISE FLOOR
–72
–16
–14
–12
–10
–8
–6
–4
–160
–2
OUTPUT POWER (dBm)
06511-046
–58
ACPR (dB)
WCDMA OPERATION
70MHz OFFSET NOISE FLOOR (dBm/Hz)
ADL5372
Figure 38. WiMAX ACPR and Noise Floor vs. Output Power at 2350 MHz;
LO Power = 0 dBm
LO GENERATION USING PLLS
Analog Devices has a line of PLLs that can be used for generating
the LO signal. Table 4 lists the PLLs together with their maximum
frequency and phase noise performance.
Table 4. Analog Devices PLL Selection Table
Part
ADF4110
ADF4111
ADF4112
ADF4113
ADF4116
ADF4117
ADF4118
Frequency FIN (MHz)
550
1200
3000
4000
550
1200
3000
Phase Noise @ 1 kHz Offset
and 200 kHz PFD (dBc/Hz)
−91 @ 540 MHz
−87 @ 900 MHz
−90 @ 900 MHz
−91 @ 900 MHz
−89 @ 540 MHz
−87 @ 900 MHz
−90 @ 900 MHz
The ADF4360 comes as a family of chips, with nine operating
frequency ranges. One is chosen, depending on the local
oscillator frequency required. While the use of the integrated
synthesizer may come at the expense of slightly degraded noise
performance from the ADL5372, it can be a cheaper alternative
to a separate PLL and VCO solution. Table 5 shows the options
available.
Table 5. ADF4360 Family Operating Frequencies
Part
ADF4360-0
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
ADF4360-8
Rev. 0 | Page 16 of 24
Output Frequency Range (MHz)
2400 to 2725
2050 to 2450
1850 to 2150
1600 to 1950
1450 to 1750
1200 to 1400
1050 to 1250
350 to 1800
65 to 400
ADL5372
TRANSMIT DAC OPTIONS
The AD9779 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the
ADL5372. There are other appropriate DACs, depending on the
level of performance required. Table 6 lists the dual TxDACs
offered by Analog Devices.
Table 6. Dual TxDAC Selection Table
Part
AD9709
AD9761
AD9763
AD9765
AD9767
AD9773
AD9775
AD9777
AD9776
AD9778
AD9779
Resolution (Bits)
8
10
10
12
14
12
14
16
12
14
16
Update Rate (MSPS Minimum)
125
40
125
125
125
160
160
160
1000
1000
1000
All DACs listed have nominal bias levels of 0.5 V and use the
same simple DAC modulator interface that is shown in Figure 32.
MODULATOR/DEMODULATOR OPTIONS
Table 7 lists other Analog Devices modulators and demodulators.
Table 7. Modulator/Demodulator Options
Part No.
AD8345
AD8346
AD8349
ADL5390
ADL5385
ADL5370
ADL5371
ADL5373
ADL5374
AD8347
AD8348
AD8340
AD8341
Rev. 0 | Page 17 of 24
Modulator/
Demodulator
Modulator
Modulator
Modulator
Modulator
Modulator
Modulator
Modulator
Modulator
Modulator
Demodulator
Demodulator
Vector
modulator
Vector
modulator
Frequency
Range (MHz)
140 to 1000
800 to 2500
700 to 2700
20 to 2400
50 to 2200
300 to 1000
500 to 1500
2300 to 3000
3000 to 4000
800 to 2700
50 to 1000
700 to 1000
1500 to 2400
Comments
External quadrature
ADL5372
EVALUATION BOARD
Populated RoHS-compliant evaluation boards are available for
evaluation of the ADL5372. The ADL5372 package has an
exposed paddle on the underside. This exposed paddle must
be soldered to the board (see the Power Supply and Grounding
section). The evaluation board is designed without any
components on the underside so heat can be applied to the
underside for easy removal and replacement of the ADL5372.
IBBN
RFPQ RFNQ CFNQ CFNI
0Ω
0Ω OPEN OPEN
VPOS
RFNI
0Ω
RFPI
0Ω
CFPI
OPEN
C16
0.1µF
L12
0Ω
19 IBBP
20 IBBN
21 COM4
22 COM4
23
QBBN
RTI
OPEN
24
QBBP
RTQ
CFPQ OPEN
OPEN
IBBP
COM1
1
COM1
2
VPS1
3
VPS1
4
15
VPS2
VPS1
5
14
VPS2
VPS1
18
Z1
F-MOD
17
16
EXPOSED PADDLE
6
C12
0.1µF
13
VPS4
VOUT
C11
OPEN
VOUT
12
C13
0.1µF
COM3
11
COM3
9
8
10
COM2
LOIN
7
LOIP
COM2
CLOP
100pF
Figure 40. Evaluation Board Layout, Top Layer
C14
0.1µF
VPS3
COUT
100pF
GND
C15
0.1µF
L11
0Ω
VPS5
06511-037
QBBN
VPOS
QBBP
CLON
100pF
06511-036
LO
Figure 39. ADL5372 Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options
Component
VPOS, GND
RFPI, RFNI, RFPQ, RFNQ, CFPI,
CFNI, CFPQ, CFNQ, RTQ, RTI
Description
Power Supply and Ground Clip Leads.
Baseband Input Filters. These components can be used to
implement a low-pass filter for the baseband signals. See
the Filtering section.
Rev. 0 | Page 18 of 24
Default Condition
Not applicable
RFNQ, RFPQ, RFNI, RFPI = 0 Ω (0402)
CFNQ, CFPQ, CFNI, CFPI = Open (0402)
RTQ, RTI = Open (0402)
ADL5372
CHARACTERIZATION SETUP
AEROFLEX IFR 3416
250kHz TO 6GHz SIGNAL GENERATOR
R AND S SPECTRUM ANALYZER
FSU 20Hz TO 8GHz
RF
OUT
FREQ 4MHz LEVEL 0dBm
BIAS 0.5V GAIN 0.7V
BIAS 0.5V GAIN 0.7V
LO
CONNECT TO BACK OF UNIT
I OUT I/AM Q OUT Q/FM
90°
I
+6dBm
RF
IN
0°
Q
AGILENT 34401A
MULTIMETER
FMOD TEST SETUP
0.175 ADC
IP
VPOS +5V
IN
QP
AGILENT E3631A
POWER SUPPLY
–
OUT
OUTPUT
QN
VPOS GND
0.175A
6V
LO
±25V
+ COM –
06511-038
5.000
+
FMOD
Figure 41. Characterization Bench Setup
The primary setup used to characterize the ADL5372 is shown
in Figure 41. This setup was used to evaluate the product as a
single-sideband modulator. The Aeroflex signal generator supplied
the LO and differential I and Q baseband signals to the device
under test, DUT. The typical LO drive was 0 dBm. The I-channel is
driven by a sine wave, and the Q-channel is driven by a cosine
wave. The lower sideband is the single sideband (SSB) output.
The majority of characterization for the ADL5372 was performed
using a 1 MHz sine wave signal with a 500 mV common-mode
voltage applied to the baseband signals of the DUT. The baseband
signal path was calibrated to ensure that the VIOS and VQOS
offsets on the baseband inputs were minimized, as close as
possible, to 0 V before connecting to the DUT. See the Carrier
Feedthrough Nulling section for the definitions of VIOS and VQOS.
Rev. 0 | Page 19 of 24
ADL5372
CH1 1MHz
AMPL 700mV p-p
PHASE 0°
CH2 1MHz
AMPL 700mV p-p
PHASE 90°
0°
R AND S SMT 06
SIGNAL GENERATOR
CH2 OUTPUT
CH1 OUTPUT
TEKTRONIX AFG3252
DUAL FUNCTION
ARBITRARY FUNCTION GENERATOR
I Q
RF
OUT
FREQ 4MHz TO 4GHz
LEVEL 0dBm
LO
90°
SINGLE TO DIFFERENTIAL
CIRCUIT BOARD
AGILENT E3631A
POWER SUPPLY
FMOD TEST RACK
5.000
0.350A
Q IN AC
±25V
6V
VPOS ++5V–
+5V
VPOS +5V
FMOD
CHAR BD
Q IN DCCM
+ COM –
IP
IP
VPOSB VPOSA IN
IN
TSEN
–5V
GND
AGND IN1
IN1
VN1
VP1
I IN DCCM
I IN AC
QP
OUTPUT
OUT
QN
GND
VPOS
QP
QN
AGILENT E3631A
POWER SUPPLY
0.500
LO
R AND S FSEA 30
SPECTRUM ANALYZER
0.010A
+
6V
RF
IN
±25V
–
+ COM –
100MHz TO 4GHz
+6dBm
VCM = 0.5V
AGILENT 34401A
MULTIMETER
06511-039
0.200 ADC
Figure 42. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling
The setup used to evaluate baseband frequency sweep and
undesired sideband nulling of the ADL5372 is shown in Figure 42.
The interface board has circuitry that converts the single-ended
I input and Q input from the arbitrary function generator to
differential I and Q baseband signals with a dc bias of 500 mV.
Undesired sideband nulling was achieved through an iterative
process of adjusting amplitude and phase on the Q-channel. See
Sideband Suppression Optimization section for a detailed
discussion on sideband nulling.
Rev. 0 | Page 20 of 24
ADL5372
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
TOP
VIEW
0.50
BSC
3.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
12° MAX
SEATING
PLANE
0.80 MAX
0.65 TYP
0.30
0.23
0.18
PIN 1
INDICATOR
19
18
24 1
*2.45
EXPOSED
PAD
2.30 SQ
2.15
(BOTTOMVIEW)
13
12
7
6
0.23 MIN
2.50 REF
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5372ACPZ-R2 1
ADL5372ACPZ-R71
ADL5372ACPZ-WP1
ADL5372-EVALZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
24-Lead LFCSP_VQ, 7” Tape and Reel
24-Lead LFCSP_VQ, 7” Tape and Reel
24-Lead LFCSP_VQ, Waffle Pack
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 21 of 24
Package Option
CP-24-2
CP-24-2
CP-24-2
Ordering Quantity
250
1,500
64
ADL5372
NOTES
Rev. 0 | Page 22 of 24
ADL5372
NOTES
Rev. 0 | Page 23 of 24
ADL5372
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06511-0-12/06(0)
T
T
Rev. 0 | Page 24 of 24