Cypress CY62168DV30LL-55BVXI 16-mbit (2048k x 8) static ram Datasheet

CY62168DV30
MoBL
16-Mbit (2048K x 8) Static RAM
Features
addresses are not toggling. The device can be put into standby
mode reducing power consumption by more than 99% when
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)
LOW. The input/output pins (I/O0 through I/O7) are placed in
a high-impedance state when: deselected Chip Enable 1
(CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled
(OE HIGH), or during a write operation (Chip Enable 1 (CE1)
LOW and Chip Enable 2 (CE2) HIGH and WE LOW).
• Very high speed: 55 ns and 70 ns
— Wide voltage range: 2.20V – 3.60V
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = fmax
• Ultra-low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Functional Description[1]
The CY62168DV30 is a high-performance CMOS static RAMs
organized as 2048Kbit words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 90% when
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address
pins(A0 through A20).
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip
Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
Logic Block Diagram
I/O0
Data in Drivers
I/O1
2048K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O3
I/O4
I/O5
COLUMN
DECODER
CE1
CE2
I/O6
POWER
DOWN
I/O7
OE
A17
A18
A19
A20
A16
A13
A14
A15
WE
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05329 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised September 14, 2004
CY62168DV30
MoBL
Pin Configuration[2]
FBGA
Top View
1
2
3
4
5
6
DNU
OE
A0
A1
A2
CE2
A
DNU DNU
A3
A4
CE1 DNU
B
I/O0
DNU
A5
A6
DNU
I/O4
C
VSS
I/O1
A17
A7
I/O5
VCC
D
VCC
I/O2
DNU
A16
I/O6
VSS
E
I/O3
DNU
A14
A15
DNU
I/O7
F
A12
A13
WE
DNU
G
A9
A10
A11
A19
H
DNU
A18
A
A
Product Portfolio
A8
Power Dissipation
Operating ICC (mA)
VCC Range (V)
Max.
Speed
(ns)
Typ.[3]
3.0
3.6
55
3.0
3.6
55
Min.
Typ.[3]
CY62168DV30L
2.2
CY62168DV30LL
2.2
Product
f = 1 MHz
Max.
Max.
Typ.[3]
Max.
2
4
15
30
2.5
30
12
25
2
4
15
30
2.5
22
12
25
70
70
Standby ISB2(µA)
f = fmax
Typ.[3]
Notes:
2. DNU pins have to be left floating or tied to VSS to ensure proper application.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05329 Rev. *D
Page 2 of 9
CY62168DV30
MoBL
DC Input Voltage[4, 5] ......................–0.3V to VCC(max) + 0.3V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Supply Voltage to Ground
Potential ........................................ –0.3V to VCC(max) + 0.3V
DC Voltage Applied to Outputs
in High-Z State[4, 5] ......................... –0.3V to VCC(max) + 0.3V
Range
Ambient
Temperature (TA) [6]
VCC[7]
Industrial
–40°C to +85°C
2.2V – 3.6V
DC Electrical Characteristics (Over the Operating Range)
CY62168DV30-55
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min.
2.2 < VCC < 2.7
IOH = −0.1 mA
2.0
2.4
Typ.
[3]
Max.
CY62168DV30-70
Min.
Typ.[3]
Max.
Unit
2.0
V
2.7 < VCC < 3.6
IOH = −1.0 mA
2.2 < VCC < 2.7
IOL = 0.1 mA
0.4
0.4
2.7 < VCC < 3.6
IOH = 2.1 mA
0.4
0.4
2.4
V
2.2 < VCC < 2.7
1.8
VCC +
0.3
1.8
VCC +
0.3
2.7 < VCC < 3.6
2.2
VCC +
0.3
2.2
VCC +
0.3
2.2 < VCC < 2.7
–0.3
0.6
–0.3
0.6
2.7 < VCC < 3.6
–0.3
0.8
–0.3
0.8
GND < VI < VCC
–1
+1
–1
+1
+1
–1
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
IOZ
Output Leakage Current GND < VO < VCC, Output disabled
+1
µA
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
Vcc = 3.6V,
IOUT = 0mA,
CMOS level
15
30
12
25
mA
2
4
2
4
CE1 > VCC − 0.2V, CE2 < L
0.2V, VIN > VCC − 0.2V, VIN
< 0.2V, f = fMAX (Address
and Data Only), f = 0 (OE, LL
WE, )
2.5
30
2.5
30
ISB1
Automatic CE
Power-down Current −
CMOS Inputs
2.5
22
2.5
22
Automatic CE
Power-down Current −
CMOS Inputs
CE1 > VCC − 0.2V, CE2 < L
0.2V, VIN > VCC − 0.2V or LL
VIN < 0.2V, f = 0, VCC=3.6V
2.5
30
2.5
30
2.5
22
2.5
22
ISB2
f = 1 MHz
–1
V
V
µA
µA
µA
Thermal Resistance
Parameter
Description
Test Conditions
BGA
Unit
Resistance[8]
Still Air, soldered on a 3 x 4.5 inch, four-layer printed
circuit board
55
°C/W
16
°C/W
ΘJA
Thermal
(Junction to Ambient)
ΘJC
Thermal Resistance[8]
(Junction to Case)
Notes:
4.VIL(min) = –0.2V for pulse durations less than 20 ns.
5.VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
6.TA is the “Instant-On” case temperature.
7.Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 100 µs wait time after Vcc stabilization..
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05329 Rev. *D
Page 3 of 9
CY62168DV30
MoBL
Capacitance[8]
e
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Unit
8
pF
10
pF
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
VCC
50 pF
R2
GND
10%
90%
10%
90%
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50V
3.0V
Unit
R1
16600
1103
Ω
R2
15400
1554
Ω
RTH
8000
645
Ω
VTH
1.2
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[8]
Chip Deselect to Data
Retention Time
tR[9]
Operation Recovery
Time
Min.
Typ.[3]
1.5
L
VCC = 1.5V
CE1 > VCC − 0.2V or CE2 <0.2V
LL
VIN > VCC − 0.2V or VIN < 0.2V
Max.
Unit
3.6
V
15
µA
10
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
VDR > 1.5 V
tCDR
VCC(min)
tR
CE1
or
CE2
Note:
9. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
Document #: 38-05329 Rev. *D
Page 4 of 9
CY62168DV30
MoBL
Switching Characteristics Over the Operating Range [10]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[11]
tHZOE
OE HIGH to High Z[11, 12]
tLZCE
CE1 LOW and CE2 HIGH to Low Z[11]
tHZCE
CE1 HIGH or CE2 LOW to High Z[11, 12]
tPU
CE1 LOW and CE2 HIGH to Power-Up
tPD
CE1 HIGH or CE2 LOW to Power-Down
55
70
55
10
ns
70
ns
70
ns
10
55
25
5
ns
35
5
20
10
25
10
20
0
ns
ns
25
0
55
ns
ns
ns
ns
70
ns
Write Cycle[13]
tWC
Write Cycle Time
55
70
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
40
60
ns
tAW
Address Set-Up to Write End
40
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
tSD
Data Set-Up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High Z[11, 12]
tLZWE
WE HIGH to Low Z[11]
20
10
25
10
ns
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of VCC(typ.)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
12. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05329 Rev. *D
Page 5 of 9
CY62168DV30
MoBL
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
tPD
tPU
50%
50%
SUPPLY
CURRENT
Write Cycle No. 1(WE Controlled)
HIGH
IMPEDANCE
ICC
ISB
[13, 17, 18]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
See Note [19]
tHD
VALID DATA
tHZOE
Notes:
14. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
17. Data I/O is high impedance if OE = VIH.
18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05329 Rev. *D
Page 6 of 9
CY62168DV30
MoBL
Switching Waveforms (continued)
Write Cycle No. 2(CE1 or CE2 Controlled)
[13, 17, 18]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tHA
tAW
tPWE
WE
OE
tSD
DATA I/O
tHD
VALID DATA
Write Cycle No. 3 (WE Controlled, OE LOW)
[19]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tSD
See Note [19]
DATAI/O
tHD
VALID DATA
tLZWE
tHZWE
Truth Table
CE1
CE2
WE
OE
H
X
X
X
Inputs/Outputs
High Z
Mode
Power
Deselect/Power-down
Standby (ISB)
X
L
X
X
High Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
Data Out (I/O0-I/O7)
Read
Active (ICC)
L
H
H
H
High Z
Output Disabled
Active (Icc)
L
H
L
X
Data in (I/O0-I/O7)
Write
Active (Icc)
Document #: 38-05329 Rev. *D
Page 7 of 9
CY62168DV30
MoBL
Ordering Information
Speed
(ns)
55
70
55
70
Package
Name
Package Type
Operating
Range
CY62168DV30L-55BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
Industrial
CY62168DV30LL-55BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
CY62168DV30L-70BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
Ordering Code
CY62168DV30LL-70BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
CY62168DV30L-55BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
CY62168DV30LL-55BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
CY62168DV30L-70BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
CY62168DV30LL-70BVXI
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
Industrial
Industrial
Industrial
Package Diagrams
48-Lead VFBGA (8 x 9.5 x 1 mm) BV48B
51-85150-*B
51-85178-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are trademarks of their respective holders.
Document #: 38-05329 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62168DV30
MoBL
Document History Page
Document Title: CY62168DV30 MoBL® 16-Mbit (2048K x 8) Static RAM
Document Number: 38-05329
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
118409
09/30/02
GUG
New Data Sheet
*A
123693
02/05/03
DPM
Changed Advance Information to Preliminary
Added package diagram
*B
126556
04/24/03
DPM
Minor change: Change sunset owner from DPM to HRT
*C
132869
01/15/04
XRJ
Changed Preliminary to Final
*D
272589
See ECN
PCI
Updated Final data sheet and added Pb-free package.
Document #: 38-05329 Rev. *D
Page 9 of 9
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