Fintek Feature Integration Technology Inc. F75375S/F75375SG F75375S/F75375SG Fintek Hardware Monitor IC Datasheet Release Date: July 2007 Revision: Version 0.26P July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG F75375 Datasheet Revision History Version Date Page Revision History 0.20P 2002 May. Original version 0.21P 2003 Dec 1. Add external clock input function. 2. Add Linear mode for fan speed control 0.22P 2004 Jan 3 Revise pin13 description 0.23P 2004 Feb 15 1.Revise register description of Index01 45 - 46 2.Revise AC/DC characteristics 0.24P 2004 Sep 2 Add key spec.(supply voltage and operating supply current) 0.25P 2005 Apr 23 Support Green package F75375SG and delete version ID register 0.26P 2007 July Company readdress LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Table of Contents 1 GENERAL DESCRIPTION............................................................................................................................................ 1 2 FEATURE ...................................................................................................................................................................... 1 3 PIN CONFIGURATION.................................................................................................................................................. 2 4 PIN DESCRIPTION ....................................................................................................................................................... 2 5 FUNCTIONAL DESCRIPTION...................................................................................................................................... 4 5.1 ANALOG INPUT ..........................................................................................................................................................4 5.2 ACCESS INTERFACE ...................................................................................................................................................5 5.3 TEMPERATURE MEASUREMENT MACHINE ....................................................................................................................6 5.3.1 Monitor Temperature from thermistor ..................................................................................................................6 5.3.2 Monitor Temperature from thermo diode .............................................................................................................7 5.3.3 Over Temperature Signal (OVT#) ........................................................................................................................7 5.4 5.4.1 Fan speed count ..................................................................................................................................................7 5.4.2 Fan speed control ................................................................................................................................................8 5.4.3 Fan speed control mechanism.............................................................................................................................9 5.4.4 FAN_Fault# ........................................................................................................................................................ 11 5.5 SMI# ......................................................................................................................................................................12 5.5.1 Temperature.......................................................................................................................................................12 5.5.2 Voltage ...............................................................................................................................................................13 5.5.3 Fan .....................................................................................................................................................................13 5.6 6 FAN ..........................................................................................................................................................................7 VOLT_FAULT# (VOLTAGE FAULT SIGNAL) ...............................................................................................................13 REGISTER DESCRIPTION.........................................................................................................................................14 6.1 CONFIGURATION REGISTER INDEX 00H ................................................................................................................14 6.2 CONFIGURATION REGISTER INDEX 01H ................................................................................................................14 6.3 CONFIGURATION REGISTER INDEX 02H ................................................................................................................15 6.4 CONFIGURATION REGISTER INDEX 03H ................................................................................................................16 6.5 SERIAL BUS ADDRESS REGISTER INDEX 04H ........................................................................................................17 6.6 VALUE RAM INDEX 10H- 2FH ..............................................................................................................................17 6.7 IRQ/SMI# ENABLE REGISTER 1 INDEX 30H .......................................................................................................18 6.8 INTERRUPT STATUS REGISTER 1 INDEX 31H .........................................................................................................19 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 6.9 REAL TIME STATUS REGISTER 1 INDEX 32H ..........................................................................................................19 6.10 IRQ/SMI# ENABLE REGISTER 2 INDEX 33H ....................................................................................................20 6.11 INTERRUPT STATUS REGISTER 2 INDEX 34H ......................................................................................................20 6.12 FAN_FAULT/VOLT_FAULT/OVT ENABLE REGISTER INDEX 35H ...................................................................21 6.13 REAL TIME FAULT STATUS REGISTER 1 INDEX 36H ..........................................................................................22 6.14 NON-ZERO-PWM FAN FAULT ENABLE REGISTER INDEX 37H ......................................................................22 6.15 NON-ZERO-PWM REAL TIME FAULT STATUS REGISTER 2 INDEX 38H ............................................................22 6.16 CHIPID(1) REGISTER – INDEX 5AH ......................................................................................................................23 6.17 CHIPID(2) REGISTER – INDEX 5BH ......................................................................................................................23 6.18 VENDOR ID(1) REGISTER – INDEX 5DH ..............................................................................................................23 6.19 VENDOR ID(2) REGISTER – INDEX 5EH ...............................................................................................................23 6.20 RESET TIMER CONTROL REGISTER -- INDEX 60H ...................................................................................................23 6.21 FAN FAULT TIME REGISTER -- INDEX 61H ...............................................................................................................24 6.22 RESET-TIMER TIME REGISTER -- INDEX 62H ........................................................................................................25 6.23 FAN STEP TIME DEFINED REGISTER -- INDEX 63H ................................................................................................25 6.24 VT1 OFFSET REGISTER -- INDEX 64H .................................................................................................................25 6.25 VT2 OFFSET REGISTER -- INDEX 65H .................................................................................................................26 6.26 PWMOUT1 RAISE DUTY-CYCLE INDEX 69H ................................................................................................26 6.27 PWMOUT2 RAISE DUTY-CYCLE INDEX 6AH ................................................................................................26 6.28 PWMOUT1 DROP DUTY-CYCLE INDEX 6BH ................................................................................................27 6.29 PWMOUT2 DROP DUTY-CYCLE INDEX 6CH ................................................................................................27 6.30 FAN1 FULL SPEED COUNT REGISTER 1 INDEX71H..............................................................................................27 6.31 FAN1 EXPECT TIMEOUT SPEED REGISTER INDEX 72H ........................................................................................27 6.32 FAN1 EXPECT TIMEOUT SPEED REGISTER INDEX 73H ........................................................................................28 6.33 FAN1 EXPECT COUNT REGISTER-- INDEX 74H .......................................................................................................28 6.34 FAN1 EXPECT COUNT REGISTER-- INDEX 75H .......................................................................................................28 6.35 FAN1 PWM_DUTY -- INDEX 76H ........................................................................................................................28 6.36 FAN1 NON-ZERO-PWM WAITING TIME -- INDEX 77H ...........................................................................................28 6.37 FAN1 EXPECT COUNT TOLERANCE -- INDEX 78H .................................................................................................29 6.38 FAN1 EXPECT COUNT HIGH BOUNDARY(MSB) -- INDEX 79H ...............................................................................29 6.39 FAN1 EXPECT COUNT HIGH BOUNDARY(LSB) -- INDEX 7AH ................................................................................29 6.40 FAN1 EXPECT COUNT LOW BOUNDARY(MSB) -- INDEX 7BH ...............................................................................30 6.41 FAN1 EXPECT COUNT LOW BOUNDARY(LSB) -- INDEX 7CH ................................................................................30 6.42 FAN1 PWMOUT CLOCK FREQUENCY SELECT -- INDEX 7DH.......................................................................30 6.43 FAN2 FULL SPEED REGISTER 0 INDEX 80H .......................................................................................................30 6.44 FAN2 FULL SPEED REGISTER 1 INDEX 81H ........................................................................................................31 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 6.45 FAN2 EXPECT TIMEOUT SPEED REGISTER INDEX 82H ........................................................................................31 6.46 FAN2 EXPECT TIMEOUT SPEED REGISTER INDEX 83H ........................................................................................31 6.47 FAN2 EXPECT COUNT REGISTER-- INDEX 84H .......................................................................................................31 6.48 FAN2 EXPECT COUNT REGISTER-- INDEX 85H .......................................................................................................32 6.49 PWM_DUTY -- INDEX 86H ..................................................................................................................................32 6.50 FAN2 NON-ZERO-PWM WAITING TIME -- INDEX 87H ...........................................................................................32 6.51 FAN2 EXPECT COUNT TOLERANCE -- INDEX 88H .................................................................................................32 6.52 FAN2 EXPECT COUNT HIGH BOUNDARY(MSB) -- INDEX 89H ...............................................................................33 6.53 FAN2 EXPECT COUNT HIGH BOUNDARY(LSB) -- INDEX 8AH ................................................................................33 6.54 FAN2 EXPECT COUNT LOW BOUNDARY(MSB) -- INDEX 8BH ...............................................................................33 6.55 FAN2 EXPECT COUNT LOW BOUNDARY(LSB) -- INDEX 8CH ................................................................................33 6.56 FAN2 PWMOUT CLOCK FREQUENCY SELECT -- INDEX 8DH.......................................................................33 6.57 GPIOX OUTPUT CONTROL REGISTER – INDEX 90H ................................................................................................34 6.58 GPIOX OUTPUT DATA REGISTER – INDEX 91H .......................................................................................................34 6.59 GPIO1X INPUT STATUS REGISTER – INDEX 92H ....................................................................................................35 6.60 VT1 BOUNDARY 1 TEMPERATURE – INDEX A0H .............................................................................................35 6.61 VT1 BOUNDARY 2 TEMPERATURE – INDEX A1H .............................................................................................35 6.62 VT1 BOUNDARY 3 TEMPERATURE – INDEX A2H .............................................................................................36 6.63 VT1 BOUNDARY 4 TEMPERATURE – INDEX A3H .............................................................................................36 6.64 FAN1 SEGMENT 1 SPEED COUNT (MSB) – INDEX A4H .................................................................................36 6.65 FAN1 SEGMENT 1 SPEED COUNT (LSB) – INDEX A5H ..................................................................................37 6.66 FAN1 SEGMENT 2 SPEED COUNT (MSB) – INDEX A6H .................................................................................37 6.67 FAN1 SEGMENT 2 SPEED COUNT (LSB) – INDEX A7H ..................................................................................37 6.68 FAN1 SEGMENT 3 SPEED COUNT (MSB) – INDEX A8H .................................................................................37 6.69 FAN1 SEGMENT 3 SPEED COUNT (LSB) – INDEX A9H ..................................................................................37 6.70 FAN1 SEGMENT 4 SPEED COUNT (MSB) – INDEX AAH.................................................................................38 6.71 FAN1 SEGMENT 4 SPEED COUNT (LSB) – INDEX ABH..................................................................................38 6.72 FAN1 SEGMENT 5 SPEED COUNT (MSB) – INDEX ACH ................................................................................38 6.73 FAN1 SEGMENT 5 SPEED COUNT (LSB) – INDEX ADH .................................................................................38 6.74 VT2 BOUNDARY 1 TEMPERATURE – INDEX B0H .............................................................................................39 6.75 VT2 BOUNDARY 2 TEMPERATURE – INDEX B1H .............................................................................................39 6.76 VT2 BOUNDARY 3 TEMPERATURE – INDEX B2H .............................................................................................39 6.77 VT2 BOUNDARY 4 TEMPERATURE – INDEX B3H .............................................................................................40 6.78 FAN2 SEGMENT 1 SPEED COUNT (MSB) – INDEX B4H .................................................................................40 6.79 FAN2 SEGMENT 1 SPEED COUNT (LSB) – INDEX B5H ..................................................................................40 6.80 FAN2 SEGMENT 2 SPEED COUNT (MSB) – INDEX B6H .................................................................................40 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7 6.81 FAN2 SEGMENT 2 SPEED COUNT (LSB) – INDEX B7H ..................................................................................41 6.82 FAN2 SEGMENT 3 SPEED COUNT (MSB) – INDEX B8H .................................................................................41 6.83 FAN2 SEGMENT 3 SPEED COUNT (LSB) – INDEX B9H ..................................................................................41 6.84 FAN2 SEGMENT 4 SPEED COUNT (MSB) – INDEX BAH ................................................................................42 6.85 FAN2 SEGMENT 4 SPEED COUNT (LSB) – INDEX BBH .................................................................................42 6.86 FAN2 SEGMENT 5 SPEED COUNT (MSB) – INDEX BCH ................................................................................42 6.87 FAN2 SEGMENT 5 SPEED COUNT (LSB) – INDEX BDH .................................................................................42 6.88 BJTOFFSET1 (FOR VT1) 6.89 BJTGAIN1 (FOR VT1) 6.90 BJTOFFSET2 (FOR VT2) 6.91 BJTGAIN2 (FOR VT1) – INDEX C0H...........................................................................................................43 – INDEX C1H ................................................................................................................43 – INDEX C2H...........................................................................................................43 – INDEX C3H ................................................................................................................43 ELECTRON CHARACTERISTIC................................................................................................................................44 7.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................................44 7.2 DC CHARACTERISTICS.............................................................................................................................................44 7.3 AC CHARACTERISTICS .............................................................................................................................................46 8 ORDERING INFORMATION .......................................................................................................................................47 9 PACKAGE DIMENSIONS (16SOP 150MIL)...............................................................................................................47 10 APPLICATION CIRCUIT ............................................................................................................................................... 1 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 1 General Description F75375S is a system hardware monitoring and automatic fan speed controlling IC specific designed for graphic cards and mini PC etc. The F75375S can monitor several critical hardware parameters of the system, including voltages, temperatures and fan speeds which are very important for the system to work stably and properly. An 8-bit analog-to-digital converter (ADC) was built inside F75375S. The chip can monitor up to 4 analog voltage inputs, 2 fan tachometer inputs and 2 remote temperature sensors. The remote temperature sensor is suggested to be performed by thermistor, transistor 2N3906 and CPU thermal diode. The F75375S can provide automatic fan speed control so that the system can operate at the minimum acoustic noise. This chip support not only PWM duty mode but also linear mode for fan speed control. Internal oscillator was built in this chip and user can use external clock input if users need accurate fan speed count. Also the users can set up the upper and lower limits (alarm thresholds) of all monitored parameters and this chip can also issue warning messages for system protection when there is something wrong with monitored items. Through the BIOS or application software, the users can read all the monitored parameters of system all the time. And a pop-up warning can be also activated when the monitored item was out of the proper/pre-setting range. The application software could be Fintek's application software MyGuardTM or other management application software. The F75375S is in the package of 150mil 16-pin SOP and powered by 3.3V. 2 Feature z 4 voltage inputs z Monitor up to 2 remote temperature sensor -- from remote thermistor / transistor / thermal diode (BJT diode-connected) z Up to 2 fan speed monitoring input and 2 automatic fan speed control -- Support both linear and PWM fan speed control (PWMOUT 25KHz support 4 pin fan) -- 3 flexible fan speed controlled modes : Manual mode, Speed mode and Temperature mode. z Programmable limited and setting points(alert threshold) for all monitored items z Issue FAN_FAULT# or VOLT_FAULT# or OVT# or SMI# signal to activate system protection z Can use external clock for accurate fan speed count z Up to 4 general purpose I/O support z 2-wire I2C interface z VCC3V operation and 16SOP package(150mil) Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 1 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 3 Key Specifications z Supply voltage 3.0~3.6V z Operating supply current 3 mA typ. 4 Pin Configuration FANIN1 FANIN2/GPIO0 1 2 16 15 VCC VT1 PWMOUT1/DACOUT1/ADDR_TRAP 3 VT2 PWMOUT2/DACOUT2/GPIO1 FAN_FAULT#/SMI#/GPIO2 4 5 14 13 VOLT_FAULT#/OVT#GPIO3/EXT_CLKIN SCLK 6 7 11 10 VIN2 VIN3 8 9 GND SDATA 12 VREF VIN1 5 Pin Description O8 - TTL level output pin with 8 mA source-sink capability INts/OD12 - TTL level bi-directional pin, can select to O.D or OUT by register, with 12mA source-sink capability I/OD8 - TTL level bi-directional pin, Open-drain outpu with 8 mA sink capability I/OD16 - TTL level bi-directional pin, Open-drain outpu with 16 mA sink capability AOUT - Output pin(Analog) OD16 - Open-drain output pin with 16 mA sink capability INt - TTL level input pin INts - TTL level input pin and schmitt trigger INtsd100k - TTL level input pin and schmitt trigger with internal pull down 100K ohm AIN P - Input pin(Analog) - Power 2 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Power Pin Pin No. Pin Name Type Description 16 VCC P 3.3V power supply voltage input 9 GND P GND Monitoring Items and Fan Speed Control Pin No. Pin Name Type Description 1 FANIN1 INt 0V to +3.3V amplitude fan tachometer input. 2 GPIO0 INts/OD8 (Default) General purpose I/O pin. Default Open drain FANIN2 INt 0V to +3.3V amplitude fan tachometer input. PWMOUT1 O12 Fan speed control pin. DACOUT1 AOUT This pin is either PWM-duty mode or Linear mode. ADDR_TRAP INtsd100k Address power on trapping pin. Internal pull down100k ohm. The 3 internal pull-down resistor will be turn-off after power-on trapping. 4 GPIO1 INts/OD12 (Default) General purpose I/O pin. Default Open drain PWMOUT2 O12 Fan speed control pin. DACOUT2 AOUT This pin is either PWM-duty mode or Linear mode. 10 VIN3 AIN 0V to 2.048V FSR Analog Inputs 11 VIN2 AIN 0V to 2.048V FSR Analog Inputs 12 VIN1 AIN 0V to 2.048V FSR Analog Inputs 14 VT2 AIN Thermistor / transistor / thermal diode terminal input 15 VT1 AIN Thermistor / transistor / thermal diode terminal input Alert Signals and Others Pin No. Pin Name Type Description 5 GPIO2 INts/OD14 (Default) General purpose I/O function. Default pure open drain SMI# OD14 System management interrupt (Pure Open Drain) FAN_FAULT# OD14 This pin will be a logic LOW when the fan speed is abnormal. GPIO3 INts/OD8 (Default) General purpose I/O function. Default Open drain OVT# OD8 Active-Low output. This pin will be a logic LOW when the temperature 6 exceeds its limit. VOLT_FAULT# OD8 Active-Low output. This pin will be a logic LOW when the voltage exceeds its limit. EXT_CLKIN INt 48MHz External clock input for chip operation source. 3 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 13 VREF AOUT Reference Voltage. Serial Bus Control Pin Pin No. Pin Name Type Description 8 SDATA INts/OD12 Serial Bus data. 7 SCLK INt s Serial Bus clock. 6 Functional Description F75375S is a system hardware monitoring and automatic fan speed controlling IC specific designed for graphic cards. The chip can monitor up to 4 analog voltage inputs, 2 fan tachometer inputs and 2 remote temperature sensors. The remote temperature sensor can be performed by thermistor, transistor and thermal diode. The F75375S can provide automatic fan speed control so that the system can operate at the minimum acoustic noise. Also the users can set up the upper and lower limits (alarm thresholds) of all monitored parameters and this chip can also issue warning messages for system protection when there is something wrong with monitored items. 6.1 Analog Input For the 8-bit ADC has the 7.8125mv LSB, the maximum input voltage of the analog pin is 2V. Therefore the voltage under 2V (ex:1.5V) can directly connected to these analog inputs. The voltage higher than 2V should be reduced by a factor with external resistors so as to obtain the input range. Only 3VCC is an exception for it is main power of the F75375S. Therefore 3VCC can directly connect to this chip and need no external resistors. There are two functions in this pin with 3.3V. The first function is to supply internal analog power of the F75375S and the second function is that this voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The internal serial resistors are two 50K ohm, so that the internal reduced voltage is half +3.3V. There are four voltage inputs in the F75375S and the voltage divided formula is shown as follows: VIN = V+12V × R2 R1 + R2 where V+12V is the analog input voltage, for example. If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within the tolerance. As for application circuit, it can be refer to the figure shown as follows. 4 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 3VCC Voltage Inputs 50K (directly connect to the chip) VIN3.3 VIN (Lower than 2.0V) 50K (directly connect to the chip) VIN1(Max2.0V) VIN(Higher than R1 R2 8-bit ADC with 7.8125 mV LSB VREF Pin 13 20K, 1% R 10K, 1% Pin 14 or 15 Typical BJT Connection Typical Thermister Connection RTHM 2N3906 10K, 25 C Figure 5-3 6.2 Access Interface The F75375S provides one serial access interface, Serial Bus, to read/write internal registers. The address of Serial Bus is configurable by using power-on trapping. The pin 3 (PWMOUT1/ADDR_TRAP) is multi-function pin. During power-on, this pin serves as input detection of logic high or logic low. This pin is default pull-down resistor with 100K ohms mapping the Serial Bus address 0x5A (0101_1010). Another Serial Bus address 0x5C (0101_1100) is set when external pull-up resistor with 10K ohms is connected in this pin. (a) Serial bus write to internal address register followed by the data byte 7 0 8 0 7 8 SCL SDA 0 Start By Master 1 0 1 1 0 1 R/W D7 Ack by 375S Frame 1 Serial Bus Address Byte D6 D5 D4 D3 D2 D1 D0 Ack by 375S Frame 2 Internal Index Register Byte 0 7 8 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 Frame 3 Data Byte D0 Stop by Master Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte (b) Serial bus read form internal address register followed by the data byte 5 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 0 SCL SDA 0 Start by Master 7 1 0 1 1 0 1 8 0 R/W D7 7 D6 ack by 375S Frame 1 Serial Bus Address Byte 0 1 2 3 4 5 6 0 1 0 1 1 0 1 D5 D4 D3 D2 D1 D0 ack by 375S Frame 2 Internal Index Register Byte 7 8 8 0 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 8 SCL(Continued) SDA(Continued) R/W ack by 375S Frame 3 Serial Bus Byte Frame 4 Data Byte ack Stop by by Master 375S Figure 2. Serial Bus read from Internal Address Register followed by the Data Byte 6.3 Temperature Measurement Machine The temperature data format is 8-bit two-complement for thermal sensor. The 8-bit temperature data can be obtained by reading through register. The format of the temperature data is show in Table 4-1. Temperature 8-Bit Digital Output 8-Bit Binary 8-Bit Hex +125°C 0111,1101 7Dh +25°C 0001,1001 19h +2°C 0000,0010 02h +1°C 0000,0001 01h +0°C 0000,0000 00h -1°C 1111,1111 FFh -2°C 1111,1110 FEh -25°C 1110,0111 E7h -50°C 1100,1110 CEh Table 4-1. Monitor Temperature from thermistor The F75375S can connect two thermistors to measure environment temperature or remote temperature. The specification of thermistor should be considered to (1) β value is 3435K (2) resistor value is 10K ohm at 25°C. In the Figure 5-3, the thermistor is connected by a serial resistor with 10K Ohm, then connected to VREF (pin13). 6 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Monitor Temperature from thermo diode Also, if the CPU, GPU or external circuits provide thermal diode for temperature monitor, F75375S is capable to these situations. The build-in reference table is for PNP 2N3906, and each different kind of thermal diode should be matched with specific offset and BJT gain. In the Figure 5-3, the 2N3906 PNP is connected by a serial resistor with 20K ohm, then connect to VREF (pin13). Over Temperature Signal (OVT#) The F75375S can provide two external thermal sensors to detect temperature. When monitored temperature exceeds the over-temperature threshold value, OVT# will be asserted until the temperature goes below the hysteresis temperature. To T HYST OVT# Figure 5-4 Fan Fan speed count Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage cannot be over VCC. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as follows: 7 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG +12V +12V Pull-up resister 4.7K Ohms Pull-up resister < 1K or totem-pole output +12V 22K~30K FAN Out Fan Input +12V FANIN 1 GND 10K > 1K FAN Out Fan Input FANIN 1 GND 3.3V Zener F75375S FAN Connector Figure 5-5 Fan with Tach Pull-Up to +12V, or Totern-Pole Output and Register Attenuator F75375S Figure 5-6 Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp +5V +5V Pull-up resister 4.7K Ohms Pull-up resister < 1K or totem-pole output +5V 1K~2.7K FAN Out Fan Input +5V FANIN1 GND 10K > 1K FAN Out Fan Input FANIN1 GND 3.3V Zener F75375S FAN Connector F75375S .Figure 5-8 Fan with Tach Pull-Up to +5V, or Totem-Pole Putput and Zener Clamp Figure 5-7. Fan with Tach Pull-Up to +5V, or Totern-Pole Output and Register Attenuator Determine the fan counter according to: Count = 1.5 × 10 6 RPM In other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. As for fan, it would be best to use 2 pulses tachmeter output per round. RPM = 6.3.1 1.5 × 10 6 Count Fan speed control The F75375S provides 2 fan speed control methods: 1. LINEAR FAN CONTROL 2. PWM DUTY CYCLE 6.3.1.1 Linear Fan Control The range of DC output is 0~3.3V, controlled by 8-bit register (CR76 for FAN1 and CR86 for FAN2). 1 LSB is about 0.013V. The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION VOLTAGE, 12V. The output voltage will be given as followed: 8 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Output_voltage (V) = 3.3 × Programmed 8 - bit Register Value × 100% 255 And the suggested application circuit for linear fac control would be: 8 12V 3 DC OUTPUT VOLTAGE - PMOS 1 D1 1N4148 LM358 4 2 + R 4.7K JP1 R 10K C 47u 3 2 1 R 27K FANIN MONITOR C 0.1u R 10K CON3 R 3.9K DC FAN Control with OP 6.3.1.2 PWM duty Fan Control The duty cycle of PWM can be programmed by a 8-bit register which are defined in the CR76h and CR86h. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty_cycle(%) = Programmed 8 - bit Register Value × 100% 255 +5V +12V R1 R1 R2 R2 PNP Transistor D G PWM Clock Input G NMOS S PWM Clock Input NMOS + S + C C FAN FAN - - Figure 5-9 6.3.2 PNP Transistor D Figure 5-10 Fan speed control mechanism There are 3 modes to control fan speed and they are manual, fan speed mode and temperature mode. For manual 9 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG mode, it generally acts as PWM fan speed control. As for speed mode and temperature mode, they are more intelligent fan speed control and described as below: 6.3.2.1 Fan Speed mode Fan speed mode is an intelligent method according to expected fan speed pre-setting by BIOS. In the beginning, fan speed will operate at full speed and the F75375S will get the full speed count value. Then fan speed slows down to rotate at about 72.5% (8/11) of full speed. After that, the fan speed will automatically rotate according to the expected fan speed setting by BIOS. The register CR74h and CR75h are used for this mode. 6.3.2.2 Temperature mode At this mode, F75375S provides the clever system to automatically control fan speed related to temperature of GPU or the system. The F75375S can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. All these values should be set by BIOS first. Take figure 5-11 as example. When temperature setting value is 45,55,65, and 75°C. There are five intervals and each interval is 10°C. The related desired fan speed counts for each interval are 0500h, 0400h, 0300h, 0200h, 0100h. When the temperature is within 55~65°C, the fan speed count 300h will be load into FAN EXPECT COUNTregisters(CR74h~CR75h, CR84h~CR85h). Then, F75375S will adjust PWMOUT duty-cycle to make fan speed match the expected value. It can be said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the temperature varying. The F75375S will take charge of all the fan speed control and need no software support. Desired Counts 0100h 75 Degree C 0200h 65 Degree C 0300h 55 Degree C 0400h 45 Degree C 0500h Figure 5-11 6.3.2.3 PWMOUT Duty-cycle operating process In both “FAN SPEED” and “TEMPERATURE” modes, F75375S adjust PWMOUT duty-cycle according to current fan count and expected fan count. It will operate as follows: 10 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG (1). When expected count is FFFFh, PWMOUT duty-cycle will be set to 00h to turn off fan. (2). When expected count is 0000h, PWMOUT duty-cycle will be set to FFh to turn on fan with full speed. (3). If both (1) and (2) are not true and KEEP_DROP_DUTY(see INDEX 60h) is set to 0, (a). When PWMOUT duty-cycle decrease to DROP_DUTY(≠ 00h), obviously the duty-cycle will decrease to 00h next, F75375S will keep duty-cycle at 00h 3 seconds1. After that, F75375S starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. This ensures that if there is any glitch during the 3 seconds1 period, F75375S will ignore it. (b). When PWMOUT duty-cycle increase from 00h to RAISE_DUTY(≠ 00h), F75375S also will keep duty-cycle at RAISE-DUTY 3 seconds1. After that, F75375S starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. This ensures that if there is any glitch during the 3 seconds1 period, F75375S will ignore it. Note 1: The period can be programmed at INDEX 6Eh. 6.3.3 FAN_Fault# Fan_Fault will be asserted when the fan speed doesn’t meet the expected fan speed within a programmable period (default is 3 11 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG seconds) or when fan stops with respect to PWM duty-cycle which should be able to turn on the fan. There are two conditions may cause the FAN_FAULT# event. (1). When PWM_Duty reaches FFh, the fan speed count can’t reach the fan expected count in time. (Figure 5-12) 3 min(default) Current Fan Count Expected Fan Count 100% Duty-cycle Fan_Fault# Figure 5-12 (2). After the period of detecting fan full speed, when PWM_Duty > (RAISE_Duty + 5), and current fan count is monitored FFFFh. 6.4 SMI# 6.4.1 Temperature SMI# interrupt for temperature is shown as figure 5-13. Temperature exceeding high limit or going below hystersis will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. To THYST SMI# (pulse mode) * * * (level mode active low) * *Interrupt Reset when Interrupt Status Registers are written 1 Figure 5-13 12 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 6.4.2 Voltage SMI# interrupt for voltage is shown as figure 5-14. Voltage exceeding or going below high limit will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. Voltage exceeding or going below low limit will result in the same condition as voltage exceeding or going below high limit. 6.4.3 Fan SMI# interrupt for fan is shown as figure 5-15 . SMI# will be asserted when the fan speed count exceeds or goes below the fan limit (Value RAM 2Ch~2Dh, 2Eh~2Fh). Voltage High limit Fan Count limit Voltage Low limit Fan Count limit SMI# SMI# (pulse mode) (level mode) * * * * (pulse mode) * * * (level mode) * * * * * *Interrupt Reset when Interrupt Status Registers are written 1 Voltage SMI# Mode FAN SMI# Mode Figure 5-14 Figure 5-15 6.5 VOLT_FAULT# (Voltage Fault Signal) When voltage leaps from the security range setting by BIOS, the warning signal VOLT_FAULT# will be activated. Shown in figure 5-16 13 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG High limit Low limit VOLT_FAULT# Figure 5-16 7 Register Description 7.1 Configuration Register Index 00h Power on default <7:0> = 01h Bit Name 7 INIT Attribute R/W Description Set one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. 6 5-1 0 SOFT_PWDN R/W Set this bit to 1 will power down A/D converter circuit. Default is 0 Reserved RO Read back will be 0 START R/W A one enables startup of monitoring operations; a zero puts the part in standby mode. 7.2 Configuration Register Index 01h Power on default <7:0> = 0000_00xx b Bit Name Attribute Description 7-6 Reserved RO Read back will be 0. 5 FAN2_LINEAR_MODE R/W Set to 0, FAN2 control mode is PWM Duty-cycle output. Set to 1, FAN2 control mode is LINEAR voltage output. 4 FAN1_LINEAR_MODE R/W Set to 0, FAN1 control mode is PWM Duty-cycle output. Set to 1, FAN1 control mode is LINEAR voltage output. 14 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 3 T2_MODE R/W Set to 1, select VT2 as connected to a BJT. Set to 0, select VT2 as connected to a thermistor. (Default is 0) 2 T1_MODE R/W Set to 1, select VT1 as connected to a BJT. Set to 0, select VT1 as connected to a thermistor. (Default is 0) 1 PIN4_MODE R/W Pin 4 mode select, set this bit to 1 will enable PWMOUT2 output, else if set this bit to 0, pin 4 will be enable the GPIO1 function.(default) This mode is trappable: When PIN3 trapped to high at power-on, PIN4 is set to PWMOUT2. When PIN3 trapped to low at power-on, PIN4 is set to GPIO1. 0 PIN2_MODE R/W Pin 2 mode select, set this bit to 1 will enable FANIN2 input, if set this bit to 0 pin 2 will be enable the GPIO0 function.(default). This mode is trappable: When PIN3 trapped to high at power-on, PIN2 is set to FANIN2. When PIN3 trapped to low at power-on, PIN2 is set to GPIO0. 7.3 Configuration Register Index 02h Power on default <7:0> = xx00_00x0 b Bit 7-6 Name PIN5_MODE Attribute R/W Description 00: pin5 function is GPIO2 01: pin5 is used as SMI 10: pin5 is used as Fan fault function 11: LED out(1Hz/0.5Hz select by bit2) This mode is trappable: When PIN3 trapped to high at power-on, PIN5 is set to Fan fault function. When PIN3 trapped to low at power-on, PIN5 is set to GPIO2. 5 SMI_MODE R/W If set to 0, SMI will be level mode else if this bit set to 1, SMI will be pulse mode. 4 SMI_LEVEL R/W When set this bit to 0 SMI is low active (default). if set to 1 SMI is high active 3 Reserved R/W 2 LED_FREQ R/W When set this bit to 1 fan fault LED output frequency will be 0.5HZ, else is 1Hz(default) 15 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 1 F_FAULT_MODE R/W When set this bit to 0 the fan fault will be level mode, else if set to 1 the fan fault will indicate by LED function(1Hz or 0.5Hz) the LED frequency can set by REG02H bit2. This mode is trappable: When PIN3 trapped to high at power-on, this mode is set to LED function. When PIN3 trapped to low at power-on, this mode is set to level mode. 0 F_FAULT_LEVEL R/W When set this bit to 0 fan fault is low active (default). if set to 1 fan fault is high active 7.4 Configuration Register Index 03h Power on default <7:0> = xx00_0000 b Bit 7 Name PIN6_MODE Attribute R/W Description 00: pin6 function is GPIO3. 01: pin6 is used as OVT 10: pin6 is used as Voltage fault function 11: pin6 is as operating clock input function. The External clock should be 48MHz. This input clock will be the clock source of the whole chip. This mode is trappable: When PIN3 trapped to high at power-on, PIN6 is set to OVT. When PIN3 trapped to low at power-on, PIN6 is set to GPIO3. 5 OVT_LEVEL R/W When set this bit to 0 OVT is low active (default), else if set to 1 OVT is high active 3-4 OVT_QUEUE R/W OVT queue is use to filter the temperature noise, it define the times of the event when OVT is asserted. 00: 1 times 01: 3 times 10: 5 times 11: 7 times 2 V_FAULT_LEVE R/W L 1-0 V_FAULT_QUE UE Voltage fault level. When set this bit to 0 voltage fault is low active (default). if set to 1 fan fault is high active R/W Voltage fault queue. It is used to filter the voltage noise, the follow define the times of the event when VOLT_FAULT is asserted. 00: 1 times 01: 3 times 16 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 10: 5 times 11: 7 times 7.5 Serial Bus Address Register Index 04h Power on default: 5Ah or 5Ch. Bit 7-0 Name Attribute SERIAL_ADDR RO Description Serial Bus address. Power on default value depends on the status of pin3(PWMOUT1/ADDR_TRAP) at the moment of power on. If the pin status is 1, the value is 5Ch, otherwise is 5Ah. To read or write registers of this chip, the serial address must match this value. This register can be written by a sequence value to this register : A9h, C3h, XXh, in which XXh will be the value being written to this register; this is to protect the register from being written by accident. 7.6 Value RAM Index 10h- 2Fh Address 10-3F Attribute Default Description Value 10h RO VCC reading. The unit of reading is 8mV. 11h RO V1 reading. The unit of reading is 8mV. 12h RO V2 reading. The unit of reading is 8mV. 13h RO V3 reading. The unit of reading is 8mV. 14h RO Temperature 1 reading. The unit of reading is 1ºC. 15h RO Temperature 2 reading. The unit of reading is 1ºC. 16h RO FAN1 count reading (MSB) 17h RO FAN1 count reading (LSB) 18h RO FAN2 count reading (MSB) 19h RO FAN2 count reading (LSB) 1Ah~1Eh Reserved 20h R/W FFh VCC High Limit. The unit is 8mV. 21h R/W 00h VCC Low Limit. The unit is 8mV. 22h R/W FFh V1 High Limit. The unit is 8mV. 23h R/W 00h V1 Low Limit. The unit is 8mV. 24h R/W FFh V2 High Limit. The unit is 8mV. 17 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 25h R/W 00h V2 Low Limit. The unit is 8mV. 26h R/W FFh V3 High Limit. The unit is 8mV. 27h R/W 00h V3 Low Limit. The unit is 8mV. 28h R/W 3Ch Temperature sensor 1 High Limit. The unit is 1ºC. 29h R/W 37h Temperature sensor 1 Hysteresis Limit. The unit is 1ºC. 2A h R/W 3Ch Temperature sensor 2 High Limit. The unit is 1ºC. 2Bh R/W 37h Temperature sensor 2 Hysteresis Limit. The unit is 1ºC. 2Ch R/W FFh FAN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 2Dh R/W FFh FAN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 2Eh R/W FFh FAN2 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 2Fh R/W FFh FAN2 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. 7.7 IRQ/SMI# ENABLE Register 1 Index 30h Power on default: 00h Bit 7 Name EN_FAN2_SMI Attribute R/W Description A one enables the corresponding interrupt status bit for SMI# interrupt 6 EN_FAN1_SMI R/W A one enables the corresponding interrupt status bit for SMI# interrupt. 5 EN_VT2_SMI R/W A one enables the corresponding interrupt status bit for SMI# interrupt. 4 EN_VT1_SMI R/W A one enables the corresponding interrupt status bit for SMI# interrupt. 18 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 3 EN_V3_SMI R/W A one enables the corresponding interrupt status bit for SMI# interrupt. 2 EN_V2_SMI R/W A one enables the corresponding interrupt status bit for SMI# interrupt. 1 EN_V1_SMI R/W A one enables the corresponding interrupt status bit for SMI# interrupt. 0 EN_VCC_SMI R/W A one enables the corresponding interrupt status bit for SMI# interrupt. 7.8 Interrupt Status Register 1 Index 31h Power on default: 00h Bit 7 Name FAN2_STS Attribute R/W Description A one indicates fan2 count limit has been exceeded. Write 1 to clear this bit, write 0 will be ignored. 6 FAN1_STS R/W A one indicates fan1 count limit has been exceeded. Write 1 to clear this bit, write 0 will be ignored. 5 VT2_STS R/W A one indicates a high limit of VT2 has been exceeded from temperature sensor. Write 1 to clear this bit, write 0 will be ignored. 4 VT1_STS R/W A one indicates a high limit of VT1 has been exceeded from temperature sensor. Write 1 to clear this bit, write 0 will be ignored. 3 V3_STS R/W A one indicates a high or low limit of VIN3 has been exceeded. Write 1 to clear this bit, write 0 will be ignored. 2 V2_STS R/W A one indicates a high or low limit of VIN2 has been exceeded. Write 1 to clear this bit, write 0 will be ignored. 1 V1_STS R/W A one indicates a high or low limit of VIN1 has been exceeded. Write 1 to clear this bit, write 0 will be ignored. 0 VCC_STS R/W A one indicates a high or low limit of VCC has been exceeded. Write 1 to clear this bit, write 0 will be ignored. 7.9 Real Time Status Register 1 Index 32h Power on default: 00h Bit Name Attribute Description 19 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7 FAN2EXC R/W A one indicates fan2 count limit has been exceeded. A zero indicates fan2 count is in the safe region. 6 FAN1EXC R/W A one indicates fan1 count limit has been exceeded. A zero indicates fan1 count is in the safe region. 5 VT2EXC R/W A one indicates a high limit of VT2 has been exceeded. A zero indicates VT2 is below the hysteresis limit. 4 VT1EXC R/W A one indicates a high limit of VT1 has been exceeded. A zero indicates VT1 is below the hysteresis limit. 3 V3EXC R/W A one indicates a high or low limit of VIN3 has been exceeded. A zero indicates VIN3 is in the safe region. 2 V2EXC R/W A one indicates a high or low limit of VIN2 has been exceeded. . A zero indicates VIN2 is in the safe region. 1 V1EXC R/W A one indicates a high or low limit of VIN1 has been exceeded. . A zero indicates VIN1 is in the safe region. 0 VCCEXC R/W A one indicates a high or low limit of VCC has been exceeded. . A zero indicates VCC is in the safe region. 7.10 IRQ/SMI# ENABLE Register 2 Index 33h Power on default: 00h Bit 7-4 3 Name Reserved EN_NZF2_SMI Attribute Description RO R/W Non-Zero-PWM FAN2 SMI enable bit. A zero disables the corresponding interrupt status for SMI# interrupt. 2 EN_NZF1_SMI R/W Non-Zero-PWM FAN1 SMI enable bit. A zero disables the corresponding interrupt status for SMI# interrupt. 1 EN_TARF2_SMI R/W Target fan2 SMI enable bit. A zero disables the corresponding interrupt status bit for SMI# interrupt 0 EN_TARF1_SMI R/W Target fan1 SMI enable bit. A zero disables the corresponding interrupt status bit for SMI# interrupt 7.11 Interrupt Status Register 2 Index 34h Power on default: 00h Bit Name Attribute Description 20 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7-4 3 Reserved STS_NZ_FAN2 R/W A one indicates fan2’s PWMOUT duty-cycle is above (RAISE_DUTY + 5) and the current FAN speed is 0 ( ie. Fan Count = FFFFh). 2 STS_NZ_FAN1 R/W A one indicates fan1’s PWMOUT duty-cycle is above (RAISE_DUTY + 5) and the current FAN speed is 0 ( ie. Fan Count = FFFFh). 1 STS_TAR_FAN2 R/W A one indicates fan2 reading count is over then fan2 expect count, and the PWMOUT2 duty cycle is full more then the FAN FAULT TIME. Write 1 to clear this bit, write 0 will be ignored. 0 STS_TAR_FAN1 R/W A one indicates fan1 reading count is over then fan1 expect count, and the PWMOUT1 duty cycle is full more then the FAN FAULT TIME. Write 1 to clear this bit, write 0 will be ignored. 7.12 FAN_FAULT/VOLT_FAULT/OVT ENABLE Register Index 35h Power on default: 00h Bit 7 Name EN_F2_FAULT Attribute R/W Description A one enables the fan2 fault status to be indicated in pin FAN_FUALT. This bit is trappable. When PIN3 trapped to high at power-on, this bit is set to 1. When PIN3 trapped to low at power-on, this bit is set to 0. 6 EN_ F1_FAULT R/W A one enables the fan1 fault status to be indicated in pin FAN_FUALT. This bit is trappable. When PIN3 trapped to high at power-on, this bit is set to 1. When PIN3 trapped to low at power-on, this bit is set to 0. 5 EN_T2_OVT R/W A one enables the VT2 fault status to be indicated in pin OVT. This bit is trappable. When PIN3 trapped to high at power-on, this bit is set to 1. When PIN3 trapped to low at power-on, this bit is set to 0. 4 EN_T1_OVT R/W A one enables the VT1 fault status to be indicated in pin OVT. This bit is trappable. When PIN3 trapped to high at power-on, this bit is set to 1. When PIN3 trapped to low at power-on, this bit is set to 0. 3 EN_V3_FAULT R/W A one enables the V3 fault status to be indicated in pin VOLT_FUALT pin. 2 EN_V2_FAULT R/W A one enables the V2 fault status to be indicated in pin VOLT _FUALT. 1 EN_V1_FAULT R/W A one enables the V1 fault status to be indicated in pin VOLT _FUALT. 21 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 0 EN_VCC_FAULT R/W A one enables the VCC fault status to be indicated in pin VOLT _FUALT. 7.13 REAL TIME Fault Status Register 1 Index 36h Power on default: 00h Bit Name Attribute Description 7 FAN2_FAULT RO A one indicates fan2 count limit exceeding. 6 FAN1_FAULT RO A one indicates fan1 count limit exceeding. 5 VT2_OVT RO This bit will set to 1 from high limit of VT2 is exceeded until the temperature2 is under the VT2 hysteresis Limit 4 VT1_OVT RO This bit will set to 1 from high limit of VT1 is exceeded until the temperature1 is under the VT1 hysteresis Limit 3 V3_FAULT RO A one indicates a high or low limit of V3 exceeding. 2 V2_FAULT RO A one indicates a high or low limit of V2 exceeding. 1 V1_FAULT RO A one indicates a high or low limit of V1 exceeding. 0 VCC_FAULT RO A one indicates a high or low limit of VCC exceeding. 7.14 NON-ZERO-PWM FAN FAULT ENABLE Register Index 37h Power on default: 00h Bit 7-3 1 Name Attribute Reserved RO EN_NZF2_FAUL R/W T Description A one enables the FAN2 Non-zero-PWM fault status to be indicated in pin FAN_FUALT. This bit is trappable. When PIN3 trapped to high at power-on, this bit is set to 1. When PIN3 trapped to low at power-on, this bit is set to 0. 0 EN_NZF1_FAUL R/W T A one enables the FAN1 Non-zero-PWM fault status to be indicated in pin FAN_FUALT. This bit is trappable. When PIN3 trapped to high at power-on, this bit is set to 1. When PIN3 trapped to low at power-on, this bit is set to 0. 7.15 NON-ZERO-PWM REAL TIME Fault Status Register 2 Index 38h Power on default: 00h Bit Name Attribute Description 22 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7 Reserved RO 1 FAN2NZEXC2 RO A one indicates FAN2 Non-zero-PWM fault. 0 FAN1NZEXC2 RO A one indicates Fan1 Non-zero-PWM fault. 7.16 CHIPID(1) Register – Index 5Ah Power-on default [7:0] =0000_0011b Bit 7-0 Name Attribute CHIPID RO Description Chip ID, High byte (8’h03). 7.17 CHIPID(2) Register – Index 5Bh Power-on default [7:0] =0000_0110b Bit 7-0 Name Attribute CHIPID RO Description Chip ID, Low byte (8’h06). 7.18 VENDOR ID(1) Register – Index 5Dh Power-on default [7:0] =0001_1001b Bit 7-0 Name Attribute VENDOR1 RO Description Vendor ID, 8’h19 7.19 VENDOR ID(2) Register – Index 5Eh Power-on default [7:0] =0011_0100b Bit 7-0 Name VENDOR2 Attribute RO Description Vendor ID, 8h34 7.20 Reset Timer Control Register -- Index 60h Power on default: 00h Bit 7-6 Name FAN2_MODE Attribute R/W Description 00: FAN2 operates in SPEED mode. PWMOUT2 duty-cycle is automatically adjusted according to FAN2 EXPECT register. 01: FAN2 operates in TEMPERATURE mode. PWMOUT2 duty-cycle 23 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG is automatically adjusted according to FAN2 EXPECT register, which will be automatically loaded into preset values according to the current temperature. (When PIN3 power-on trapped to 1, this mode is selected after power-on.) 1X: FAN2 operates in MANUAL mode. Software set the PWMOUT2 duty-cycle directly. 5-4 FAN1_MODE R/W 00: FAN1 operates in SPEED mode. PWMOUT1 duty-cycle is automatically adjusted according to FAN1 EXPECT register. 01: FAN1 operates in TEMPERATURE mode. PWMOUT1 duty-cycle is automatically adjusted according to FAN1 EXPECT register, which will be automatically loaded into preset values according to the current temperature. (When PIN3 power-on trapped to 1, this mode is selected after power-on.) 1X: FAN1 operates in MANUAL mode. Software set the PWMOUT1 duty-cycle directly. 3 Reserved 2 KEEP_DROP_DU R/W TY2 1 hold. KEEP_DROP_DU R/W TY1 0 Set to 1, keep PWMOUT2 duty-cycle decrease to DROP duty and Set to 1, keep PWMOUT1 duty-cycle decrease to DROP duty and hold. EN_RESET_TIME R/W R Set to 1, enable interface_idle timer. Set to 0, disable the timer. When the timer is enabled, if software doesn’t access the this chip through GP_CLK and GP_DATA, the reset timer starts to count down according to the value set in INDEX 62H. When it counts down to zero, INDEX[72H, 73H] will be loaded into INDEX[74H,75H]. 7.21 Fan Fault Time Register -- Index 61h Power on default: 02h Bit 7-0 Name F_FAULT_TIME Attribute R/W Description This register determines the time of fan fault. Two conditions cause fan fault event: (1). When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan expect count in the time. (2). When PWM_Duty reaches 00h, if the fan speed count can’t reach the fan expect count in the time. 24 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG The unit of this register is 1 second. The default value is 3 seconds. (Set to 0 , means 1 seconds. Set to 1, means 2 seconds. Set to 2, means 3 seconds. …. ) 7.22 RESET-Timer Time Register -- Index 62h Power on default: 09h Bit 7-0 Name F_RESET_TIME Attribute R/W Description Interface idle time. The unit of this register is 1 minute. The default value is 10 minute. More details in INDEX 60H. 7.23 FAN STEP Time defined Register -- Index 63h Power on default: 00h Bit 7-4 Name FAN_STEP2 Attribute R/W Description This value determines the increasing or decreasing speed of PWM_Duty. The unit is 0.1 second. (Set to 0, means 0.1 second per step. Set to 1, means 0.2 second per step…. ) 3:0 FAN_STEP1 R/W This value determines the increasing or decreasing speed of PWM_Duty The unit is 0.1 second. 7.24 VT1 OFFSET Register -- Index 64h Power on default: 00h Bit Name 7-0 T1OFFSET Attribute R/W Description VT1 temperature offset register. The offset value is representative in 2’s complement. The real temperature value will be added by this offset and then will be put into temperature reading ( Value RAM 14h). The offset ranges from -128ºC to +127ºC. 7Fh : +127ºC. 01h : +5ºC. 00h : +0ºC. 25 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG FFh : -1ºC. FEh : -2ºC. 80h : -128ºC. 7.25 VT2 OFFSET Register -- Index 65h Power on default: 00h Bit 7-0 Name T2OFFSET Attribute R/W Description VT2 temperature offset register. The offset value is representative in 2’s complement. The real temperature value will be added by this offset and then will be put into temperature reading ( Value RAM 15h). The offset ranges from -128ºC to +127ºC. 7Fh : +127ºC. 01h : +5ºC. 00h : +0ºC. FFh : -1ºC. FEh : -2ºC. 80h : -128ºC. 7.26 PWMOUT1 RAISE DUTY-CYCLE Index 69h Power on default: 30h Bit 7-0 Name FAN1_RAISE_DUT Attribute R/W Description PWMOUT1 will increase duty-cycle from 0 to this value directly. Y 7.27 PWMOUT2 RAISE DUTY-CYCLE Index 6Ah Power on default: 30h Bit 7-0 Name FAN2_RAISE_DUT Attribute R/W Description PWMOUT2 will increase duty-cycle from 0 to this value directly Y 26 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.28 PWMOUT1 DROP DUTY-CYCLE Index 6Bh Power on default: 10h Bit 7-0 Name FAN1_DROP_DUT Attribute Description R/W PWMOUT1 will decrease duty-cycle to 0 from this value directly or Y keep duty-cycle in this value when CR60 bit1 set to 1. 7.29 PWMOUT2 DROP DUTY-CYCLE Index 6Ch Power on default: 10h Bit 7-0 Name FAN2_DROP_DUT Attribute Description R/W PWMOUT2 will decrease duty-cycle to 0 from this value directly or Y keep duty-cycle in this value when CR60 bit2 set to 1. 7.30 FAN1 full speed Count Register 1 Index71h Power on default: 1111_1111b Bit 7-0 Name FAN1_FULL Attribute RO (LSB) Description When power on, the PWMOUT1 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN1 signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN1 after power on, the PWMOUT1 will keep outputting FFh duty cycle. 7.31 FAN1 expect timeout speed Register Index 72h Power on default: 0000_0001b Bit 7-0 Name FAN1_TSPEED (MSB) Attribute R/W Description The fan1 timeout count, when software idle timeout is happen, this count will be load to FAN1 expect register. The default count is 11/8 of FAN1_FULL reg. ( 73% of full speed). This register is only valid at HALF-AUTOMATIC(SPEED) mode. 27 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.32 FAN1 expect timeout speed Register Index 73h Power on default: 0101_1101b Bit Name 7-0 FAN1_TSPEED Attribute R/W (LSB) Description The fan1 timeout count, when software idle timeout is happen, this count will be load to FAN1 expect register. The default count is 11/8 of FAN1_FULL reg. ( 73% of full speed). This register is only valid at HALF-AUTOMATIC(SPEED) mode. 7.33 FAN1 expect count Register-- Index 74h Power on default [7:0] = 0000_0001b Bit 7-0 Name Attribute FAN1_EXPECT R/W (MSB) Description User expect fan1 count value, program this register to control the expect fan1 speed 7.34 FAN1 expect count Register-- Index 75h Power on default [7:0] = 0101_1101b Bit 7-0 Name FAN1_EXPECT Attribute R/W (LSB) Description User expect fan1 count value, program this register to control the expect fan1 speed. 7.35 FAN1 PWM_duty -- Index 76h Power on default: 1111_1111b Bit 7-0 Name PWM_DUTY1 Attribute R/W Description PWMOUT1 duty cycle. This register is programmable at Manual mode. At SPEED or TEMPERATURE mode, this register reflects current PWMOUT duty-cycle. 7.36 FAN1 Non-zero-PWM Waiting Time -- Index 77h Power on default: 05h Bit Name Attribute Description 28 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7-0 F1_NZ_WAIT R/W This value determines the gap of current PWMOUT1 duty-cycle and FAN1_RAISE_DUTY. After current PWMOUT1 duty-cycle is larger than (FAN1_RAISE_DUTY + F1_NZ_WAIT), it starts to compare if the current fan count equals to FFFFh, which is one of the condition of FAN1 Non-zero-PWM fault. 7.37 FAN1 Expect Count Tolerance -- Index 78h Power on default: 0Ah Bit Name 7-4 Reserved 3-0 FAN1_EXPTOL Attribute R/W Description This value determines the tolerance of fan expect count. When (1). FAN1 current count > (FAN1_EXPECT + FAN1_EXPTOL), Increasing PWM duty. (2). FAN1 current count < (FAN1_EXPECT – FAN1_EXPTOL), Decreasing PWM duty. 7.38 FAN1 Expect Count High Boundary(MSB) -- Index 79h Power on default: 0Ah Bit Name Attribute 7-0 FAN1_EXPEC RO Description The MSB of FAN1_EXPECT + FAN1_EXPTOL T_H[15:8] 7.39 FAN1 Expect Count High Boundary(LSB) -- Index 7Ah Power on default: 0Ah Bit Name Attribute 7-0 FAN1_EXPEC RO Description The LSB of FAN1_EXPECT + FAN1_EXPTOL T_H[7:0] 29 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.40 FAN1 Expect Count Low Boundary(MSB) -- Index 7Bh Power on default: 01h Bit Name Attribute 7-0 FAN1_EXPEC RO Description The MSB of FAN1_EXPECT - FAN1_EXPTOL T_L[15:8] 7.41 FAN1 Expect Count Low Boundary(LSB) -- Index 7Ch Power on default: 53h Bit Name Attribute 7-0 FAN1_EXPEC RO Description The LSB of FAN1_EXPECT - FAN1_EXPTOL T_L[7:0] 7.42 FAN1 PWMOUT CLOCK FREQUENCY SELECT -- Index 7Dh Power on default: 53h Bit Name Attribute Description 7-3 Reserved 2 FAN1_INV R/W Set to 1, invert the signal of PWMOUT1. 1-0 FAN1_PWMCL R/W Select PWMOUT1 output frequency. K_SEL 00 : 5.85K Hz 01 : 26.56K Hz 10 : 187.5K Hz 11 : 5.85K Hz 7.43 FAN2 Full speed Register 0 Index 80h Power on default: 0000_0000b Bit 7-0 Name FAN2_FULL(MSB) Attribute R/W Description While PIN4 is set to PWMOUT mode, the PWMOUT2 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN1 signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN2 after power on, the PWMOUT2 will 30 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG keep outputting FFh duty cycle. 7.44 FAN2 full speed Register 1 Index 81h Power on default: 1111_1111b Bit 7-0 Name Attribute FAN2_FULL R/W (LSB) Description While PIN4 is set to PWMOUT mode, the PWMOUT2 will output full duty cycle (FFh) to enable system FAN. After 15 seconds, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. 7.45 FAN2 expect timeout speed Register Index 82h Power on default: 0000_0001b Bit 7-0 Name Attribute FAN2_TSPEED R/W Description The fan2 timeout count, when software idle timeout is happen, this count will be load to FAN1 expect register. The default count is 11/8 of FAN2_FULL reg. ( 73% of full speed). This register is only valid at HALF-AUTOMATIC(SPEED) mode. 7.46 FAN2 expect timeout speed Register Index 83h Power on default: 0101_1101b Bit 7-0 Name Attribute FAN2_TSPEED R/W (LSB) Description The fan2 timeout count, when software idle timeout is happen, this count will be load to FAN2 expect register. The default count is 11/8 of FAN2_FULL reg. ( 73% of full speed). This register is only valid at HALF-AUTOMATIC(SPEED) mode. 7.47 FAN2 expect count Register-- Index 84h Power on default [7:0] = 0000_0001b Bit 7-0 Name FAN2_EXPECT (MSB) Attribute R/W Description User expect fan2 count value, program this register to control the expect fan2 speed 31 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.48 FAN2 expect count Register-- Index 85h Power on default [7:0] = 0101_1101b Bit 7-0 Name FAN2_EXPECT Attribute R/W (LSB) Description User expect fan2 count value, program this register to control the expect fan2 speed 7.49 PWM_duty -- Index 86h Power on default: 1111_1111b Bit 7-0 Name PWM_DUTY2 Attribute R/W Description PWMOUT2 duty cycle. This register is programmable at MANUAL mode. At SPEED or TEMPERATURE mode, this register reflects current PWMOUT duty-cycle. 7.50 FAN2 Non-zero-PWM Waiting Time -- Index 87h Power on default: 05h Bit 7-0 Name F2_NZ_WAIT Attribute R/W Description This value determines the gap of current PWMOUT2 duty-cycle and FAN2_RAISE_DUTY. After current PWMOUT2 duty-cycle is larger than (FAN2_RAISE_DUTY + F2_NZ_WAIT), it starts to compare if the current fan count equals to FFFFh, which is one of the condition of FAN2 Non-zero-PWM fault. 7.51 FAN2 Expect Count Tolerance -- Index 88h Power on default: 0Ah Bit Name 7-4 Reserved 3-0 FAN2_EXPTOL Attribute R/W Description This value determines the tolerance of fan expect count. When (1). FAN2 current count > (FAN2_EXPECT + FAN2_EXPTOL), Increasing PWM duty. 32 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG (2). FAN2 current count < (FAN2_EXPECT – FAN2_EXPTOL), Decreasing PWM duty. 7.52 FAN2 Expect Count High Boundary(MSB) -- Index 89h Power on default: 0Ah Bit Name Attribute 7-0 FAN2_EXPEC RO Description The MSB of FAN2_EXPECT + FAN2_EXPTOL T_H[15:8] 7.53 FAN2 Expect Count High Boundary(LSB) -- Index 8Ah Power on default: 0Ah Bit Name Attribute 7-0 FAN2_EXPEC RO Description The LSB of FAN2_EXPECT + FAN2_EXPTOL T_H[7:0] 7.54 FAN2 Expect Count Low Boundary(MSB) -- Index 8Bh Power on default: 01h Bit Name Attribute 7-0 FAN2_EXPEC RO Description The MSB of FAN2_EXPECT - FAN2_EXPTOL T_L[15:8] 7.55 FAN2 Expect Count Low Boundary(LSB) -- Index 8Ch Power on default: 53h Bit Name Attribute 7-0 FAN2_EXPEC RO Description The LSB of FAN2_EXPECT - FAN2_EXPTOL T_L[7:0] 7.56 FAN2 PWMOUT CLOCK FREQUENCY SELECT -- Index 8Dh Power on default: 53h 33 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Bit Name Attribute Description 7-3 Reserved 2 FAN2_INV R/W Set to 1, invert the signal of PWMOUT2. 1-0 FAN2_PWMCL R/W Select PWMOUT2 output frequency. K_SEL 00 : 5.85K Hz 01 : 26.56K Hz 10 : 187.5K Hz 11 : 5.85K Hz 7.57 GPIOx Output Control Register – Index 90h Power-on default [7:0] =0000_0000b Bit Name Attribute Description 7-4 Reserved RO Read back will be 0; 3 GPIO3_OCTRL R/W GPIO3 output control. Set to 1 for output function. Set to 0 for input function(default). 2 GPIO2_OCTRL R/W GPIO2 output control. If this pin serves as IRQ/SMI#, this bit has no effect. Set to 1 for output function. Set to 0 for input function(default). 1 GPIO1_OCTRL R/W GPIO1 output control. Set to 1 for output function. Set to 0 for input function(default). 0 GPIO0_OCTRL R/W GPIO0 output control. Set to 1 for output function. Set to 0 for input function(default). 7.58 GPIOx Output Data Register – Index 91h Power-on default [7:0] =0000_0000b Bit Name Attribute Description 7-4 Reserved RO Read back will be 0; 3 GPIO3_ODATA R/W GPIO3 output data. 2 GPIO2_ODATA R/W GPIO2 output data. 1 GPIO1_ODATA R/W GPIO1 output data. 0 GPIO0_ODATA R/W GPIO0 output data. 34 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.59 GPIO1x Input Status Register – Index 92h Power-on default [7:0] = N.A. Bit Name Attribute Description 7-4 Reserved RO Read back will be 0 3 GPIO3_PSTS RO Read the GPIO3 data on the pin. 2 GPIO2_PSTS RO Read the GPIO2 data on the pin. If this pin serves as IRQ/SMI#, this bit always indicates 0, that is, read will return 0. 1 GPIO1_PSTS RO Read the GPIO1 data on the pin. 0 GPIO0_PSTS RO Read the GPIO0 data on the pin. INDEX A0 -- AD registers – FAN1 CONTROL v.s. TEMPERATURE 1 7.60 VT1 BOUNDARY 1 TEMPERATURE – Index A0h Power-on default [7:0] =0011_1100b Bit 7-0 Name BOUND1TMP Attribute R/W Description st The 1 BOUNDARY temperature for VT1 in temperature mode. When VT1 temperature is exceed this boundary, FAN1 segment 1 speed count registers(INDEX A4h, A5h) will be loaded into FAN1 expect count registers(INDEX 74h,75h). When VT1 temperature is below this boundary, FAN1 segment 2 speed count registers(INDEX A6h, A7h) will be loaded into FAN1 expect count registers(INDEX 74h,75h). 7.61 VT1 BOUNDARY 2 TEMPERATURE – Index A1h Power-on default [7:0] =0011_0010b Bit 7-0 Name BOUND2TMP Attribute R/W Description The 2nd BOUNDARY temperature for VT1 in temperature mode. When VT1 temperature is exceed this boundary, FAN1 segment 2 speed count registers(INDEX A6h, A7h) will be loaded into FAN1 expect count registers(INDEX 74h,75h). When VT1 temperature is below this boundary, FAN1 segment 3 speed count registers(INDEX A8h, A9h) will be loaded into FAN1 35 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG expect count registers(INDEX 74h,75h). 7.62 VT1 BOUNDARY 3 TEMPERATURE – Index A2h Power-on default [7:0] =0010_1000b Bit 7-0 Name BOUND3TMP Attribute R/W Description rd The 3 BOUNDARY temperature for VT1 in temperature mode. When VT1 temperature is exceed this boundary, FAN1 segment 3 speed count registers(INDEX A8h, A9h) will be loaded into FAN1 expect count registers(INDEX 74h,75h). When VT1 temperature is below this boundary, FAN1 segment 4 speed count registers(INDEX AAh, ABh) will be loaded into FAN1 expect count registers(INDEX 74h,75h). 7.63 VT1 BOUNDARY 4 TEMPERATURE – Index A3h Power-on default [7:0] =0001_1110b Bit Name 7-0 BOUND4TMP Attribute R/W Description The 4th BOUNDARY temperature for VT1 in temperature mode. When VT1 temperature is exceed this boundary, FAN1 segment 4 speed count registers(INDEX AAh, ABh) will be loaded into FAN1 expect count registers(INDEX 74h,75h). When VT1 temperature is below this boundary, FAN1 segment 5 speed count registers(INDEX ACh, ADh) will be loaded into FAN1 expect count registers(INDEX 74h,75h). 7.64 FAN1 SEGMENT 1 SPEED COUNT (MSB) – Index A4h Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC1SPEED (MSB) Attribute R/W Description st The MSB of 1 expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed, 00h will be loaded into this register. 36 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.65 FAN1 SEGMENT 1 SPEED COUNT (LSB) – Index A5h Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC1SPEED Attribute R/W (LSB) Description st The LSB of 1 expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed, 00h will be loaded into this register. 7.66 FAN1 SEGMENT 2 SPEED COUNT (MSB) – Index A6h Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC2SPEED Attribute R/W (MSB) Description The MSB of 2nd expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, the high byte of 112.5% FAN1 FULL SPEED COUND will be loaded into this register. (ie. 88% of FULL SPEED RPM) 7.67 FAN1 SEGMENT 2 SPEED COUNT (LSB) – Index A7h Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC2SPEED Attribute R/W (LSB) Description The LSB of 2nd expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, the low byte of 112.5% FAN1 FULL SPEED COUND will be loaded into this register. 7.68 FAN1 SEGMENT 3 SPEED COUNT (MSB) – Index A8h Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC3SPEED Attribute R/W (MSB) Description The MSB of 3rd expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, the high byte of 131.25% FAN1 FULL SPEED COUND will be loaded into this register. (ie. 76% of FULL SPEED RPM) 7.69 FAN1 SEGMENT 3 SPEED COUNT (LSB) – Index A9h Power-on default [7:0] =0000_0000b 37 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Bit 7-0 Name SEC3SPEED Attribute R/W (LSB) Description rd The LSB of 3 expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, the low byte of 131.25% FAN1 FULL SPEED COUND will be loaded into this register. (ie. 76% of FULL SPEED RPM) 7.70 FAN1 SEGMENT 4 SPEED COUNT (MSB) – Index AAh Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC4SPEED Attribute R/W (MSB) Description th The MSB of 4 expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, the high byte of 156.25% FAN1 FULL SPEED COUND will be loaded into this register. (ie. 64% of FULL SPEED RPM) 7.71 FAN1 SEGMENT 4 SPEED COUNT (LSB) – Index ABh Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC4SPEED Attribute R/W (LSB) Description The LSB of 4th expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, the low byte of 156.25% FAN1 FULL SPEED COUND will be loaded into this register. (ie. 64% of FULL SPEED RPM) 7.72 FAN1 SEGMENT 5 SPEED COUNT (MSB) – Index ACh Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC5SPEED R/W R/W (MSB) Description The MSB of 5th expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, FFh will be loaded into this register. 7.73 FAN1 SEGMENT 5 SPEED COUNT (LSB) – Index ADh Power-on default [7:0] =0000_0000b 38 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Bit 7-0 Name SEC5SPEED Attribute R/W (LSB) Description th The LSB of 5 expected fan speed for FAN1 in temperature mode. After detecting FAN1 full speed count, FFh will be loaded into this register. INDEX B0 -- BD registers – FAN2 CONTROL v.s. TEMPERATURE 2 7.74 VT2 BOUNDARY 1 TEMPERATURE – Index B0h Power-on default [7:0] =0000_0000b Bit 7-0 Name BOUND1TMP Attribute R/W Description st The 1 BOUNDARY temperature for VT2 in temperature mode. When VT2 temperature is exceed this boundary, FAN2 segment 1 speed count registers(INDEX B4h, B5h) will be loaded into FAN1 expect count registers(INDEX 84h,85h). When VT2 temperature is below this boundary, FAN2 segment 2 speed count registers(INDEX B6h, B7h) will be loaded into FAN2 expect count registers(INDEX 84h,85h). 7.75 VT2 BOUNDARY 2 TEMPERATURE – Index B1h Power-on default [7:0] =0000_0000b Bit 7-0 Name BOUND2TMP Attribute R/W Description nd The 2 BOUNDARY temperature for VT2 in temperature mode. When VT2 temperature is exceed this boundary, FAN2 segment 2 speed count registers(INDEX B6h, B7h) will be loaded into FAN2 expect count registers(INDEX 84h,85h). When VT2 temperature is below this boundary, FAN2 segment 3 speed count registers(INDEX B8h, B9h) will be loaded into FAN2 expect count registers(INDEX 84h,85h). 7.76 VT2 BOUNDARY 3 TEMPERATURE – Index B2h Power-on default [7:0] =0000_0000b Bit Name 7-0 BOUND3TMP Attribute R/W Description The 3rd BOUNDARY temperature for VT2 in temperature mode. 39 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG When VT2 temperature is exceed this boundary, FAN2 segment 3 speed count registers(INDEX B8h, B9h) will be loaded into FAN2 expect count registers(INDEX 84h,85h). When VT2 temperature is below this boundary, FAN2 segment 4 speed count registers(INDEX BAh, BBh) will be loaded into FAN2 expect count registers(INDEX 84h,85h). 7.77 VT2 BOUNDARY 4 TEMPERATURE – Index B3h Power-on default [7:0] =0000_0000b Bit Name 7-0 BOUND4TMP Attribute R/W Description The 4th BOUNDARY temperature for VT2 in temperature mode. When VT2 temperature is exceed this boundary, FAN2 segment 4 speed count registers(INDEX BAh, BBh) will be loaded into FAN2 expect count registers(INDEX 84h,85h). When VT2 temperature is below this boundary, FAN2 segment 5 speed count registers(INDEX BCh, BDh) will be loaded into FAN2 expect count registers(INDEX 84h,85h). 7.78 FAN2 SEGMENT 1 SPEED COUNT (MSB) – Index B4h Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC1SPEED Attribute R/W (MSB) Description st The MSB of 1 expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed, 00h will be loaded into this register. 7.79 FAN2 SEGMENT 1 SPEED COUNT (LSB) – Index B5h Power-on default [7:0] =0000_0000b Bit Name 7-0 SEC1SPEED Attribute R/W (LSB) Description The LSB of 1st expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed, 00h will be loaded into this register. 7.80 FAN2 SEGMENT 2 SPEED COUNT (MSB) – Index B6h Power-on default [7:0] =0000_0000b 40 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Bit 7-0 Name SEC2SPEED Attribute R/W (MSB) Description nd The MSB of 2 expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, the high byte of 112.5% FAN2 FULL SPEED COUND will be loaded into this register. (ie. 88% of FULL SPEED RPM) 7.81 FAN2 SEGMENT 2 SPEED COUNT (LSB) – Index B7h Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC2SPEED Attribute R/W (LSB) Description nd The LSB of 2 expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, the low byte of 112.5% FAN2 FULL SPEED COUND will be loaded into this register. (ie. 88% of FULL SPEED RPM) 7.82 FAN2 SEGMENT 3 SPEED COUNT (MSB) – Index B8h Power-on default [7:0] =0000_0000b Bit Name 7-0 SEC3SPEED Attribute R/W (MSB) Description The MSB of 3rd expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, the high byte of 131.25% FAN2 FULL SPEED COUND will be loaded into this register. (ie. 76% of FULL SPEED RPM) 7.83 FAN2 SEGMENT 3 SPEED COUNT (LSB) – Index B9h Power-on default [7:0] =0000_0000b Bit Name 7-0 SEC3SPEED (LSB) Attribute R/W Description The LSB of 3rd expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, the low byte of 131.25% FAN2 FULL SPEED COUND will be loaded into this register. (ie. 76% of FULL SPEED RPM) 41 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.84 FAN2 SEGMENT 4 SPEED COUNT (MSB) – Index BAh Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC4SPEED Attribute R/W (MSB) Description th The MSB of 4 expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, the high byte of 156.25% FAN2 FULL SPEED COUND will be loaded into this register. (ie. 64% of FULL SPEED RPM) 7.85 FAN2 SEGMENT 4 SPEED COUNT (LSB) – Index BBh Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC4SPEED Attribute R/W (LSB) Description th The LSB of 4 expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, the low byte of 156.25% FAN2 FULL SPEED COUND will be loaded into this register. (ie. 64% of FULL SPEED RPM) 7.86 FAN2 SEGMENT 5 SPEED COUNT (MSB) – Index BCh Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC5SPEED Attribute R/W (MSB) Description th The MSB of 5 expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, FFh will be loaded into this register. 7.87 FAN2 SEGMENT 5 SPEED COUNT (LSB) – Index BDh Power-on default [7:0] =0000_0000b Bit 7-0 Name SEC5SPEED (LSB) Attribute R/W Description th The LSB of 5 expected fan speed for FAN2 in temperature mode. After detecting FAN2 full speed count, FFh will be loaded into this register. 42 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.88 BJTOFFSET1 (for VT1) – Index C0h Power-on default [7:0] = AEh Bit Name 7-0 BJTOFFSET1 7.89 BJTGAIN1 (for VT1) Attribute R/W Description Used to adjust VT1 BJT offset. – Index C1h Power-on default [7:0] = 04h Bit Name 7-5 Reserved 4-0 BJTGAIN_CTRL1 Attribute R/W Description Used to adjust VT1 BJT gain. BJTGAIN is a 23 bits control bus. 0h: BJTGAIN = 000001h 1h: BJTGAIN = 000002h 2h: BJTGAIN = 000004h 3h: BJTGAIN = 000008h 4h: BJTGAIN = 000010h (default value) 5h: BJTGAIN = 000020h 6h: BJTGAIN = 000040h 7h: BJTGAIN = 000080h 8h: BJTGAIN = 000100h : 16h: BJTGAIN = 400000h 7.90 BJTOFFSET2 (for VT2) – Index C2h Power-on default [7:0] = AEh Bit Name 7-0 BJTOFFSET2 7.91 BJTGAIN2 (for VT1) Attribute R/W Description Used to adjust VT2 BJT offset. – Index C3h Power-on default [7:0] = 04h Bit Name 7-3 Reserved 4-0 BJTGAIN_CTRL2 Attribute R/W Description Used to adjust VT2 BJT gain. 0h: BJTGAIN = 000001h 1h: BJTGAIN = 000002h 43 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 2h: BJTGAIN = 000004h 3h: BJTGAIN = 000008h 4h: BJTGAIN = 000010h (default value) 5h: BJTGAIN = 000020h 6h: BJTGAIN = 000040h 7h: BJTGAIN = 000080h 8h: BJTGAIN = 000100h : 16h: BJTGAIN = 400000h 8 Electron Characteristic 8.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage -0.5 to 4.0 V Input Voltage -0.5 to 5.5 V Operating Temperature 0 to +70 °C Storage Temperature -55 to +150 °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8.2 DC Characteristics (Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. 44 UNIT CONDITIONS July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH Input Low Leakage ILIL 0.8 2.0 V V 0.4 V IOL = 12 mA V IOH = - 12 mA +1 µA VIN = VDD -1 µA VIN = 0V 2.4 I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Vt- 0.5 0.8 Input High Threshold Voltage Vt+ 1.6 2.0 Hysteresis VTH 0.5 1.2 Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH Input Low Leakage ILIL 1.1 V VDD = 3.3 V V VDD = 3.3 V V VDD = 3.3 V V IOL = 12 mA V IOH = - 12 mA +1 µA VIN = VDD -1 µA VIN = 0V 2.4 0.4 2.4 45 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 7.2 DC Characteristics, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage VOL Output High Voltage VOH 0.4 V IOL = 12 mA V IOH = -12 mA V IOL = 8 mA V IOL = 12 mA 0.4 V IOL = 16 mA 0.8 V 2.4 OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 OD16 - Open-drain output pin with sink capability of 16 mA Output Low Voltage VOL INt - TTL level input pin Input Low Voltage VIL Input High Voltage VIH Input High Leakage ILIH +1 µA VIN = VDD Input Low Leakage ILIL -1 µA VIN = 0 V 2.0 V INts - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 3.3V Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 3.3V Hysteresis VTH 0.5 1.2 V VDD = 3.3 V Input High Leakage ILIH +1 µA VIN = VDD Input Low Leakage ILIL -1 µA VIN = 0 V 8.3 AC Characteristics t SCL tR tR SCL t HD;SDA t SU;DAT t SU;STO SDA IN VALID DATA t HD;DAT SDA OUT Serial Bus Timing Diagram 46 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Serial Bus Timing PARAMETER SYMBOL MIN. MAX. UNIT SCL clock period t-SCL 10 uS Start condition hold time tHD;SDA 4.7 uS Stop condition setup-up time tSU;STO 4.7 uS DATA to SCL setup time tSU;DAT 120 nS DATA to SCL hold time tHD;DAT 5 nS SCL and SDA rise time tR 1.0 uS SCL and SDA fall time tF 300 nS 9 Ordering Information Part Number Package Type Production Flow F75375S 16 PIN SOP Commercial, 0°C to +70°C F75375SG 16 PIN SOP(Green Package) Commercial, 0°C to +70°C 10 Package Dimensions (16SOP 150mil) 47 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG Feature Integration Technology Inc. Headquarters Taipei Office 3F-7, No 36, Tai Yuan St., Bldg. K4, 7F, No.700, Chung Cheng Rd., Chupei City, Hsinchu, Taiwan 302, R.O.C. Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 886-3-5600168 TEL : 866-2-8227-8027 FAX : 886-3-5600166 FAX : 866-2-8227-8037 www: http://www.fintek.com.tw Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 48 July 2007 V0.26P Fintek Feature Integration Technology Inc. F75375S/F75375SG 11 Application Circuit Y1 ADDRESS SELECT VCC3V PWMOUT1 R1 VCC3V OUT 10K OSC14 R28 R3 100K R4 R5 R6 R7R8 SCLK SDATA VOLTAGE MONITOR EXT_CLK Y1 ON Y1 OFF R9 Ext.Clock=48MHz Internal Clock 100K VIN1 R10 FANIN1 VCC VT1 FANIN2/GPIO0 PWMOUT1/DACOUT1/ADDR_TRAP VT2 VREF PWMOUT2/DACOUT2/GPIO1 FAN_FAULT#/SMI#/GPIO2 VIN1 VOLT_FAULT#/OVT#/GPIO3/EXT. CLOCK VIN2 SCLK VIN3 SDATA GND 16 15 14 13 12 11 10 9 T1 T2 VREF VIN1 VIN2 VIN3 C2 VDD1 (2.0V) VDD2 (2.5V) VDD3 (1.5V) 100K VCC3V U1 FANIN1 1 2 PWMOUT1 3 4 5 6 SCLK 7 SDATA 8 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K R1 ON ADDRESS=0x5Ch R1 OFF ADDRESS=0X5Ah R28 optional 8 C3 R11 0.1U 4.7U 150K VIN2 R12 100K F75375S R13 12V 47K VIN3 8 R15 DAC Voltage output 3 + 2 - 100K U2A NDS0605/SOT 1 Q1 VIN1,VIN2,VIN3 SIGNALS BEST INPUT LEVEL IS ABOUT 1V D1 1N4148 LM358 4 JP1 R17 10K TEMPERATURE MONITOR (Thermal Diode) R14 4.7K 3 2 1 C4 47u C5 CON3 R19 3.9K C1 R16 27K T1 FANIN1 VREF 0.1u R18 10K R2 20K 1% 3300p D+ D- TEMPERATURE MONITOR (Thermistor) Linear FAN CONTROL T1 4.7K JP2 PWMOUT1 R26 330 Q3 2N7002 C6 47u 3 2 1 CON3 10K THERMISTOR R23 R25 27K C7 RT2 VREF R24 4.7K RT1 10K 1% T2 D2 2N39061N4148 Q2 R22 4.7K R20 t VREF 10K 1% t R21 12V 10K THERMISTOR FANIN1 0.1u R27 10K Title Size A PWM FAN CONTROL Date: 1 Feature Integration Technology Inc. Document Number F75375S Rev 0.32 Sheet 1 of 1 July 2007 V0.26P