MPS MP28248 High-efficiency, fast-transient, 3a, 4.2v-20v input synchronous step-down converter in a qfn12 (2x3mm) package Datasheet

MP28248
The Future of Analog IC Technology
High-Efficiency, Fast-Transient, 3A, 4.2V-20V Input
Synchronous Step-down Converter
in a QFN12 (2x3mm) Package
DESCRIPTION
FEATURES




The MP28248 is a fully-integrated, highefficiency, synchronous, step-down, switch
mode converter. It offers a very compact
solution that can achieve a 3A continuous
output current over a wide input supply range
with excellent load and line regulation. The
MP28248 operates at high efficiency over a
wide output-current load range.



Constant-On-Time control mode provides fast
transient response and eases loop stabilization.
Full protective features include short-circuit
protection, over-current protection, over-voltage
protection, under-voltage protection, and
thermal shutdown.
The MP28248 requires a minimal number of
readily-available standard external components.
This device is available in a space-saving
2mmx3mm 12-pin QFN package.


Wide 4.2V to 20V Operating Input Range
3A Output Current
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching-Loss Reduction
Technique
Soft Startup/Shutdown
Programmable Switching Frequency
SCP, OCP, UVP, OVP, and Thermal
Shutdown
Output Adjustable from 0.815V to 13V
Available in a QFN12 (2mmx3mm) Package
APPLICATIONS


Networking Systems
Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS
green status, please visit MPS website under the Products, Quality
Assurance page.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
100
90
80
Vin=12V
70
60
50
40
MP28248 Rev 1.0
1/5/2012
0.01
0.1
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1
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
ORDERING INFORMATION
Part Number
Package
Top Marking
MP28248GD*
QFN12 (2x3mm)
ACR
*For Tape & Reel, add suffix –Z (e.g. MP28248GD–Z).
PACKAGE REFERENCE
TOP VIEW
GND
12
11
GND
10
SW
GND
1
SW
2
BST
3
9
IN
VCC
4
8
FREQ
EN
5
7
FB
SW
6
SS
QFN12 (2x3mm)
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 22V
VSW ..................................... -0.3V to (VIN + 0.3V)
VBS ....................................................... VSW + 6V
IVIN (RMS) ........................................................ 3.5A
All Other Pins ..................................-0.3V to +6V
(2)
Continuous Power Dissipation (TA = 25°C)
QFN12 (2X3mm)........................................ 1.8W
Junction Temperature ..............................150°C
Lead Temperature ....................................260°C
Storage Temperature ............... -65°C to +150°C
Recommended Operating Conditions
(3)
Supply Voltage VIN ........................... 4.2V to 20V
Output Voltage VOUT ..................... 0.815V to 13V
Maximum Junction Temp. (TJ) ... -40°C to 125°C
MP28248 Rev 1.0
1/5/2012
Thermal Resistance
(4)
θJA
θJC
QFN12 (2mmx3mm) ............... 70 ...... 15... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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2
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameters
Supply current (shutdown)
Supply current (quiescent)
HS switch-on resistance(5)
LS switch-on resistance(5)
Switch leakage
Current limit
One-shot on-time
tON
Minimum off time
tOFF
tFB-OCP
tFB-SCP
IL=ILIM=1 FB=0.6V
IL=ILIM=1 FB=0.2V
Typ
0
440
120
50
0
5
480
160
100
125
5
10
OCP hold-off time(5)
tOC
IL=ILIM=1 FB=0.6V
50
Feedback voltage
VFB
TA=25°C
Fold-back off Time(5)
Feedback current
EN rising threshold
EN threshold hysteresis
Symbol
IIN
IQ
HSRDS-ON
LSRDS-ON
SWLKG
ILIMIT
IFB
ENVth-Hi
ENVth-Hys
EN input current
IEN
Soft-start charging current
Soft stop charging current
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
Thermal shutdown
Thermal shutdown hysteresis
ISS
ISS
Condition
VEN = 0V
VEN = 2V, VFB = 0.9V
VEN = 0V, VSW = 0V or 12V
After Soft-Start time-out
R7 = 600kΩ, VOUT = 1.2V
R7 = 200kΩ, VOUT = 1.2V
R7 = 120kΩ, VOUT = 1.2V
Min
4
807
VFB=815mV
1.05
VEN = 2V
VEN = 0V
VSS = 0V
VSS=0.815V
Max
490
1
Units
μA
μA
mΩ
mΩ
μA
A
ns
ns
ns
ns
μs
μs
μs
815
823
mV
30
1.3
500
1.5
0
14
4.5
50
1.6
nA
V
mV
µA
µA
µA
μA
3.1
V
INUVVth
INUVHYS
300
mV
TSD
150
25
°C
°C
TSD-HYS
Note:
5) Guaranteed by design and characterization
MP28248 Rev 1.0
1/5/2012
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MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
PIN FUNCTIONS
QFN12
(2x3mm)
Pin #
Name
Description
1, 11, 12
GND
System Ground. Reference ground for the regulated output voltage. Requires special
consideration during PCB layout.
2, 10,
exposed pad
SW
3
BST
4
VCC
5
EN
6
SS
7
FB
8
FREQ
9
IN
MP28248 Rev 1.0
1/5/2012
Switch Output. Connect using wide PCB traces.
Bootstrap. Requires a capacitor connected between SW and BST pins to form a
floating supply across the high-side switch driver.
Internal Bias Supply. Decouple with a 1µF ceramic capacitor as close to the pin as
possible.
EN = 1 to enable the MP28248. For automatic start-up, connect EN pin to VIN with a
pull-up resistor.
Soft-Start. Connect an external SS capacitor to program the soft-start time for the
switch mode regulator. When the EN pin goes high, an internal current source (14µA)
charges up the SS capacitor and the SS voltage smoothly ramps up from 0 to VFB.
When the EN pin goes low, an internal current source (4.5μA) discharges the SS
capacitor and the SS voltage smoothly drops.
Feedback. Sets the output voltage when connected to the tap of an external resistor
divider that is connected between output and GND.
Frequency. Set during CCM operation. Connect a resistor R7 to IN to set the switching
frequency. Decouple with a 1nF capacitor.
Supply Voltage. The MP28248 operates from a +4.2V to +20V input rail. Requires C1 to
decouple the input rail. Use wide PCB traces and multiple vias to make the connection.
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MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL CHARACTERISTICS
VIN=12V, Vout=1.2V, L=2μH, TA=+25°C,unless otherwise noted.
Enable Supply Current vs.
Input Voltage
Disable Supply Current vs.
Input Voltage
1
0.8
550
0.6
530
0.4
520
0.2
510
0
500
490
-0.4
480
-0.6
470
-0.8
460
-1
700
540
-0.2
600
500
400
300
200
450
4
8
12
16
20
4
VCC vs. Input Voltage
8
12
16
20
IO=3A
15
20
460
450
5.12
440
430
5.08
4.9
420
5.04
4.8
5
10
15
20
5
Fs vs.Output Current
410
400
0
0.5
1
1.5
2
2.5
3
4
No Load
350
5
4.5
300
4
4
250
200
100
50
Full Load
1
2.5
0.5
1
MP28248 Rev 1.0
1/5/2012
1.5
2
2.5
3
Vin=12V
Vin=4.5V
2
3
0
20
3
3.5
150
16
Vin=20V
6
5
400
12
7
5.5
450
8
Current Limit vs. Temperature
BST vs. Vin
500
0
10
470
5.16
5
4.7
5
480
5.2
IO=1.5A
0
Fs vs. Input Voltage
IO=0A
5.1
100
VCC vs. Io
5.3
5.2
No Load Supply Current vs.
Input Voltage
4
8
12
16
20
0
-40 -20
0
20
40
60
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80 100
5
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL CHARACTERISTICS (continued)
VIN=12V, Vout=1.2V, L=2μH, TA=+25°C,unless otherwise noted.
5.5
500
5.15
490
5.25
5.13
VCC (V)
4.75
4.5
4.25
4
480
FREQUENCY(kHz)
5
5.11
5.09
5.07
3.75
3.5
-40 -20
460
450
440
430
420
410
0
20
40
60
5.05
-40 -20
80 100
5.5
4
5.25
BST VOLTAGE(V)
4.25
3.75
3.5
3.25
3
2.75
2.5
-40 -20
470
0
20
40
60
80 100
0
20
40
60
80 100
400
-40 -20
0
20
40
60
80 100
5
4.75
4.5
4.25
4
3.75
0
MP28248 Rev 1.0
1/5/2012
20
40
60
80 100
3.5
-40 -20
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MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1.2V, L = 2µH, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current
Power Loss vs. Load Current
Vo=1.2V
Vo=1.2V
100
Vin=12V
80
Vin=20V
70
1200
100
1000
95
POWER LOSS(mW)
Vin=5V
90
60
50
800
90
600
85
400
Vin=20V
Vin=12V
0.01
0.1
1
OUTPUT CURRENT(A)
10
200
0
0
Line Regulation
Vo=1.2V
Vo=1.2V
0.6
0.2
Vin=20V
0.5
0
Vin=20V
Vin=12V
600
-0.5
-0.6
Vin=5V
200
0
0.5
1
1.5
2
2.5
3
-1
-1.2
-1.5
0
OUTPUT CURRENT(A)
0.5
1 1.5
2 2.5
OUTPUT CURRENT(A)
3
Vo=1.2V
25
Vo=1.2V
OUTPUT VOLTAGE(V)
No Load
15
Half Load
Full Load
Vin=20V
5
5
10
15
INPUT VOLTAGE(V)
MP28248 Rev 1.0
1/5/2012
0
12
16
20
Vo vs. Io
Vo=1.2V
0.5
1 1.5
2 2.5
OUTPUT CURRENT(A)
1.19
Vin=20V
1.185
1.18
1.175
Vin=12V
1.17
Vin=5V
1.165
Vin=12V
0
8
1.195
20
10
4
INPUT VOLTAGE(V)
Case Temperature Rise vs.
Output Current
Vo vs. Vin
Full Load
-0.8
-1
Vin=8V
Half Load
-0.4
Vin=12V
400
1.186
1.184
1.182
1.18
1.178
1.176
1.174
1.172
1.17
1.168
1.166
1.164
No Load
0
-0.2
800
10
0.4
1
1000
0.1
1
OUTPUT CURRENT(A)
Load Regulation
1200
0
70
0.01
3
OUTPUT VOLTAGE(V)
POWER LOSS(mW)
0.5
1 1.5
2 2.5
OUTPUT CURRENT(A)
1.5
1400
Vin=20V
75
Power Loss vs. Load Current
1600
Vin=12V
Vin=8V
80
Vin=5V
40
Efficiency vs. Load Current
3
1.16
0
0.5
1
1.5
2
2.5
OUTPUT CURRENT(A)
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MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2µH, TA = 25°C, unless otherwise noted.
Shut Down Through Vin
Start Up Through EN
Start Up Through EN
Io=3A
Io=0A
Io=3A
MP28248 Rev 1.0
1/5/2012
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© 2012 MPS. All Rights Reserved.
8
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2µH, TA = 25°C, unless otherwise noted.
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
9
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
BLOCK DIAGRAM
IN
VCC
EN
5V LDO
REFERENCE
Over-Current
Timer
+
-
ILIM
1MEG
SS
Refresh
Timer
xS Q
0.4V
1.0V
0.8V
RSEN
OC
OFF
Timer
HS Ilimit
Comparator
+
Current Sense
Amplifer
FREQ
xR
HS
Driver
PWM
FB
START
HS-FET
LOGIC
SW
SOFT
START/STOP
+
+
-
BST
BSTREG
VCC
ON
Timer
LS
Driver
Loop
Comparator
LS-FET
Current
Modulator
+
-
UV
UV Detect
Comparator
+
-
GND
AGND
OV
OV Detect
Comparator
Figure 1: Functional Block Diagram
MP28248 Rev 1.0
1/5/2012
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MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
to zero, and the switching frequency (fSW) is fairly
constant. Figure 2 shows the timing diagram
during this operation.
OPERATION
PWM Operation
The MP28248 is a fully-integrated, synchronous,
rectified, step-down switch converter. The device
uses constant-on-time (COT) control to provide
fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) turns ON
whenever the feedback voltage (VFB) is lower
than the reference voltage (VREF)—a low VFB
indicates insufficient output voltage. The input
voltage and the frequency-set resistor determine
the ON period as follows:
t ON 
9.3  R7 (k )
 40(ns)
VIN (V)  0.4
(1)
Light-Load Operation
During light-load operation—when the output
current is low—the MP28248 reduces the
switching frequency to maintain high efficiency,
and the inductor current drops near zero. When
the inductor current reaches zero, the LS-FET
driver goes into tri-state (high Z). The current
modulator controls the LS-FET and limits the
inductor current to around -1mA as shown in
Figure 3. Hence, the output capacitors discharge
slowly to GND through LS-FET, R1, and R2. This
operation greatly improves device efficiency
when the output current is low.
After the ON period elapses, the HS-FET enters
the OFF state. By cycling HS-FET between the
ON and OFF states, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) turns on when the HS-FET is in its OFF
state to minimize the conduction loss.
Shoot-through occurs when both the HS-FET
and the LS-FET are turned on at the same time,
causing a dead short between input and GND.
Shoot-through dramatically reduces efficiency,
and the MP28248 avoids this by internally
generating a dead-time (DT) between when HSFET turns off and LS-FET turns on, and when
LS-FET turns off and HS-FET turns on.
Heavy-Load Operation
Figure 3: Light-Load Operation
Light-load operation is also called skip mode
because the HS-FET does not turn on as
frequently as during heavy-load conditions. The
frequency at which the HS-FET turns on is a
function of the output current—as the output
current increases, the time period that the current
modulator regulates becomes shorter, and the
HS-FET turns on more frequently. The switching
frequency increases in turn. The output current
reaches the critical level when the current
modulator time is zero, and can be determined
using the following equation:
IOUT =
(VIN -VOUT )  VOUT
2  L  fSW  VIN
(2)
The device reverts to PWM mode once the
output current exceeds the critical level. After
that, the switching frequency stays fairly constant
over the output current range.
Figure 2: Heavy-Load Operation
During heavy-load operation—when the output
current is high—the MP28248 enters continuousconduction mode (CCM) where the HS-FET and
LS-FET repeat the on/off operation described for
PWM operation, the inductor current never goes
MP28248 Rev 1.0
1/5/2012
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11
MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
noise immunity proportional to the steepness of
VFB’s downward slope. However, VFB ripple does
not directly affect noise immunity.
BST
V S L O PE1
VNOISE
N1
LSG
VFB
C3
VREF
VCC
C5
SW
HS D river
L
J itter
Figure 5: Jitter in PWM Mode
COUT
VNOISE
VS LOPE 2
Figure 4: Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection with a rising
threshold of 2.2V and a hysteresis of 150mV.
The bootstrap capacitor is charged from VCC
through N1 (Figure 4). N1 turns on when the LSFET turns on and turns off when the LS-FET
turns off.
Switching Frequency
MP28248 uses constant-on-time control because
there is no dedicated oscillator in the IC. The
input voltage is feed-forwarded to the on-time
one-shot timer through the resistor R7. The duty
ratio is kept as VOUT/VIN, and the switching
frequency is fairly constant over the input voltage
range. The switching frequency can be
determined with the following equation:
fSW (kHz)=
V FB
V REF
HS D river
Jitter
Figure 6: Jitter in Skip Mode
Ramp with Large ESR Capacitor
For POSCAP or other types of capacitors with
large ESR as the output capacitors, the ESR
ripple dominates the output ripple, and the slope
on the FB is related to the ESR. Figure 7 shows
an equivalent circuit in PWM mode with the HSFET off and without an external ramp circuit. Go
to the application information section for design
recommendations for large ESR capacitors.
106
(3)
9.3  R 7 (kΩ) VIN (V)

+t DELAY (ns)
VIN (V)-0.4 VOUT (V)
Where tDELAY is the comparator delay, and equals
approximately 40ns.
MP28248 is optimized to operate at high
switching frequency with high efficiency. High
switching frequency makes it possible to use
small-sized LC filter components to save system
PCB space.
Figure 7: Simplified Circuit in PWM Mode without
External Ramp Compensation
To realize a stable output without an external
ramp, select an ESR value using the following
equation:
Jitter and FB Ramp Slope
Jitter occurs in both
the noise in the VFB
the HS-FET driver,
Figure 6. Jitter can
MP28248 Rev. 1.0
1/5/2012
PWM and skip modes when
ripple propagates a delay to
as shown in Figure 5 and
affect system stability, with
RESR
t SW
t
 ON
 0.7   2
COUT
(4)
Where tSW is the switching period.
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12
MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
Ramp with small ESR Capacitor
When using ceramic output capacitors, the ESR
is insufficient to stabilize the system and requires
external ramp compensation. The application
section discusses this in further depth.
used or not. Figure 9 shows the simplified circuit
of the skip mode when both the HS-FET and LSFET are off.
Figure 9: Simplified Circuit in Skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as follow:
.
Figure 8: Simplified Circuit in PWM Mode with
External Ramp Compensation
Figure 8 shows a simplified external ramp
compensation circuit (R4 and C4) for PWM mode,
with the HS-FET off. Chose R1, R2, and C4 of
the external ramp to meet the following condition:

1  R  R2
<  1
+R 9 
2π  fSW  C4 5  R1 +R 2

1
(5)
Where:
IR4  IC4  IFB  IC4
(6)
And VRAMP on VFB can then be estimated as:
V  VOUT
R1 // R2
 IN
 t ON 
R 4  C4
R1 // R2  R9
VRAMP
(7)
The downward slope of the VFB ripple then
follows:
VSLOPE1 
 VOUT
 VRAMP

t off
R 4  C4
(8)
As shown in equation 8, either reduce R4 or C4 if
there is instability in PWM mode. If C4 can not be
reduced further due to limitation from equation 5,
then reduce R4. For stable PWM operation,
design Vslope1 based on equation 9.
t SW
t
+ ON -RESRCOUT
Io(mA)
(9)
-Vslope1  0.7  π 2
VOUT +
2  L  COUT
t SW -t on
Where IO is the load current.
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
MP28248 Rev. 1.0
1/5/2012
VSLOPE2 
 VREF
(R1  R2  // Ro)  COUT
(10)
Where RO is the equivalent load resistor.
As shown in Figure 6, VSLOPE2 in skip mode is
lower than that is in the PWM mode, so generally
the jitter in skip mode is larger. For a system with
less jitter in light-load condition, select smaller
VFB resistors, though smaller resistors decrease
the light-load efficiency.
When using a large-ESR capacitor on the output,
add a 10µF or smaller ceramic capacitor in
parallel to minimize ESL effects.
Soft-Start/Stop
The MP28248 employs a soft start/stop (SS)
mechanism to ensure smooth output during
power up and power shut-down. When the EN
pin goes high, an internal current source (14μA)
charges up the external SS cap. The SS cap
voltage takes over the REF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches VREF, it continues to ramp up while the
PWM comparator only compares the VREF and
the VFB. At this point, the soft start finishes and it
enters into steady state operation.
When the EN pin goes low, an internal 4.5μA
current source discharges the external SS cap
voltage. Once the SS voltage falls below the
VREF, the PWM comparator will only compare the
VFB to the SS voltage. The output voltage will
decrease smoothly with the SS voltage until the
voltage level zeros out at high load. The SS cap
value can be determined as follows:
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13
MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
CSS  nF  
t SS  ms   ISS  A 
VREF  V 
(11)
If the output capacitors are large, avoid setting a
short SS time to avoid hitting the current limit
during SS. Table 1 lists SS times with different
external capacitor value.
Table 1: Soft-Start Time vs. Capacitor Value
tSS(ms)
CSS(nF)
0.58
10
1.92
33
2.74
47
3.96
68
5.82
100
MP28248 has UVLO protection. When VIN
exceeds the UVLO rising threshold voltage, the
chip powers up. It shuts off when VIN is less than
the UVLO falling threshold voltage. This is nonlatch protection.
Thermal Shutdown
The junction temperature of the IC is monitored
internally. If the junction temperature exceeds the
threshold value (typically 150°C), the converter
shuts off. This is non-latch protection. There is
about 25°C hysteresis. Once the junction
temperature drops to around 125°C, it initiates a
soft start.
Over-Current Protection and Short-Circuit
Protection
The MP28248 has cycle-by-cycle over-current
limit control that monitors the inductor current
during the HS-FET ON state. Once the inductor
current exceeds the current limit, the HS-FET
turns off. At the same time, the OCP timer—set
at 50µs—starts. OCP will trigger if the current
reaches or exceeds the current limit every cycle
during those 50µs, and the MP28248 enters
hiccup mode to periodically restart the part.
If VFB < 0.5xVREF and the current hits its limit, the
MP28248 triggers the short-circuit protection
(SCP) immediately and the MP28248 enters
hiccup mode to periodically restart the part.
If VFB < 0.5xVREF and the inductor current peak
value exceeds the set current limit threshold,
MP28248 enters hiccup mode to periodically
restart the part. This protection mode is
especially useful when the output shorts to
ground, greatly reducing the average short-circuit
current and any thermal build-up to protect the
regulator. The MP28248 exits the hiccup mode
once the over current condition is removed.
Over-Voltage Protection (OVP)
MP28248 monitors the output voltage through
the tap of a resistor divider connected to FB.
When VFB exceeds 1.25xVREF, MP28248 triggers
OVP. LS-FET is then left on, while the HS-FET is
off. Exiting OVP requires power cycling the
MP28248.
UVLO protection
MP28248 Rev. 1.0
1/5/2012
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14
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
APPLICATION INFORMATION
Setting the
Capacitors
Output
Voltage—Large
ESR
For applications that use electrolytic or POS
capacitors as output capacitors, the output
voltage is set by feedback resistors R1 and R2
as shown in Figure 10.
Figure 10: Simplified Circuit of POS Capacitor
To design the feedback circuit, first select a value
for R2: a small R2 will lead to considerable
quiescent current loss while a large R2 makes
the FB pin noise-sensitive. For best results,
choose a value between 5kΩ and 50kΩ for R2,
and choose a comparatively larger R2 when VO
is low—e.g. 1.05V—and a smaller R2 when VO is
high. Then determine R1 using the following
equation that takes the output ripple into
consideration:
1
VOUT  VOUT  VREF
2
(12)
R1 
 R2
VREF
Where VOUT is the output ripple determined by
equation 21.
Setting the
Capacitors
Output
Voltage—Small
ESR
equation 7. Select an appropriate R2: typically in
the range of 5kΩ to 50kΩ for most applications;
use a relatively large R2 when VO is low—
e.g.,1.05V—and a small R2 when VO is high.
Determine R1 as follows:
R2
(13)
R=
1
VFB(AVG)
R2
(VOUT -VFB(AVG) ) R4 +R9
-
Where VFB(AVG) is the average value on the FB pin.
Its value in skip mode is lower than in PWM
mode, meaning load regulation is strictly
conditional to to the VFB(AVG). Line regulation is
also related to VFB(AVG). For improved load or line
regulation, use a lower VRAMP as per equation 9.
For PWM mode, use the following equation to
determine VFB(AVG):
R1 //R2
1
VFB(AVG)  VREF  VRAMP 
(14)
2
R1 //R2  R9
Typically R9 is 0Ω, but the appropriate non-zero
value, as per equation 15, improves noise
immunity. Select a value that is around
0.2×R1//R2 to minimize its effect on VRAMP.
R9 
1
2 C4  2fSW
To simplify the calculation of R1 for equation 14,
add a DC-blocking capacitor, CDC, to filter the DC
influence from R4 and R9. Figure 12 shows a
simplified
circuit
with
external
ramp
compensation and a DC-blocking capacitor.
Approximating R1 is now much easier with CDC
using equation 16 for PWM mode.
1
(VOUT  VREF  VRAMP )
2
R1 
R2
1
VREF  VRAMP
2
Figure 11: Simplified Circuit with Ceramic
Capacitor
When using a low-ESR ceramic capacitors on
the output, add an external voltage ramp to the
FB pin. As Figure 11 shows, the resistive divider
and the ramp voltage, VRAMP, influences the
output voltage. As discussed in the previous
section, the VRAMP can be calculated as per
MP28248 Rev 1.0
1/5/2012
(15)
(16)
Select a CDC value at least 10× the value of C4
for better DC blocking, though do not select a
CDC that exceeds 0.47µF to avoid long start-up
times. Larger CDC values improve FB noise
immunity when combined with smaller R1 and R2
values to limit system start-up effects. Note that
even with CDC, the load and line regulation are
still VRAMP-related.
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15
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
IOUT
1
ΔVIN = 
4 fSW  CIN
Figure 12: Simplified Ceramic Capacitor Circuit
with DC Blocking Capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and
X7R ceramic dielectrics are recommended
because they are fairly stable with temperature
fluctuations.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
VOUT
V
(17)
ICIN  IOUT 
 (1  OUT )
VIN
VIN
The worst-case condition occurs at VIN = 2VOUT,
where:
ICIN 
IOUT
2
(18)
For simplification, choose an input capacitor with
an RMS current rating greater than half of the
maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
The input voltage ripple can be estimated as
follows:
ΔVIN =
 V 
IOUT
V
 OUT  1- OUT  (19)
fSW  CIN VIN  VIN 
(20)
Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic or POSCAP capacitors for
best results. The output voltage ripple can be
estimated as:
V
V
1
) (21)
VOUT  OUT  (1  OUT )  (RESR 
fSW  L
VIN
8  fSW  COUT
For ceramic capacitors, the impedance at the
switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
VOUT
V
(22)
VOUT 
 (1  OUT )
8  fSW 2  L  COUT
VIN
The output voltage ripple caused by ESR is very
small and requires an external ramp to stabilize
the system. The external ramp can be generated
through resistor R4 and capacitor C4 following
equations 5, 8 and 9.
For POSCAP capacitors, the ESR dominates the
impedance at the switching frequency. The ramp
voltage generated from the ESR is high enough
to stabilize the system and therefore does not
need an external ramp. Use a minimum ESR
value of around 12mΩ to ensure stable converter
operation. For simplification, the output ripple can
be approximated as:
VOUT 
VOUT
V
 (1  OUT )  RESR (23)
fSW  L
VIN
The application design must also consider the
maximum output capacitor value. If the output
capacitor value is too high, the output voltage
can’t reach the designated value during the softstart time, and then the device will fail to regulate.
The maximum output capacitor value CO_MAX can
be approximately by:
CO _ MAX  (ILIM _ AVG  IOUT )  t ss / VOUT (24)
Where ILIM_AVG is the average start-up current
during soft-start period and tss is the soft-start
time.
Under worst-case conditions where VIN = 2VOUT:
MP28248 Rev. 1.0
1/5/2012
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16
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
Table 2: 1.2V VOUT (L = 2μH)
Inductor
The inductor supplies constant current to the
output load while being driven by the switched
input voltage. A larger-value inductor will result in
less ripple current that will result in lower output
ripple voltage. However, a larger-value inductor
will have a larger physical footprint, higher series
resistance, and/or lower saturation current. A
good rule for determining the inductance value is
to design the peak-to-peak ripple current in the
inductor to be in the range of 30% to 40% of the
maximum output current, and that the peak
inductor current is below the maximum switch
current limit. The inductance value can be
calculated by:
L=
VOUT
V
 (1- OUT )
fSW  ΔI L
VIN
VIN VOUT
(V) (V)
12
1.2
R7
R4
C4
R1
R2
FSW
(Ω)
(Ω)
(F)
(Ω)
(Ω)
(Hz)
301k 806k 220p 17.4k 40.2k
Table 3: 1.8V VOUT (L = 2μH)
VIN
VOUT R7 R4 C4
(V) (Ω) (Ω) (F)
(V)
R1
(Ω)
440k
R2 FSW
(Ω) (Hz)
12
1.8 402k 649k 220p 30k 24.3k 500k
Table 4: 2.5V VOUT (L = 2μH)
VIN VOUT R7
R4
C4
R1
R2 FSW
(V) (V) (Ω)
(Ω) (F) (Ω) (Ω) (Hz)
12 2.5 499k 499k 330p 21.5k 10k 544k
Table 5: 3.3V VOUT (L = 4.7μH)
VIN VOUT R7
R4
C4
R1 R2 FSW
(V)
(V)
(Ω)
(Ω)
(F)
(Ω) (Ω) (Hz)
(25)
12 3.3 680k 806k 330p 31.6k 10k 520k
Table 6: 5V VOUT (L = 8μH)
VIN VOUT R7
R4
C4 R1
R2 FSW
(V)
(V)
(Ω)
(Ω) (F) (Ω) (Ω) (Hz)
Where ΔIL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
VOUT
V
(26)
 (1  OUT )
ILP  IOUT 
2fSW  L
VIN
12
5
1M
1.2M 220p 53.6k 10k 544k
The detailed application schematic is shown in
Figure 13. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
possible applications of this device, please refer
to related Evaluation Board Data Sheets.
Design Example
Some design examples with typical outputs are
provided in the following tables:
Typical Application Schematic
U1
R3
4.2V-20V
VIN
R7
C1A
GND
IN
9
BST
3
J1
NS
MP28248
301k
0
C3
25V
SW
C7
VCC
R5
8
FREQ
4
VCC
SW
2
SW
10
C5
C4
806K
220pF
R9
0
GND
SS
GND
SS
12
6
GND
EN
11
5
1
NS
R4
NS
FB
R8
VOUT
D1
499k
EN
L1
7443552200
1nF
C2A
C2B
C2C
1210
1210
0603
C2D
1.2V@3A
VOUT
NS
GND
R1
17.4k
7
R2
40.2k
C6
33nF
Figure 13: Detailed Application Schematic
MP28248 Rev. 1.0
1/5/2012
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MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
Layout Recommendation
1)
The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, wide, and direct traces.
2)
Put the input capacitors as close to the IN
and GND pins as possible.
5)
Keep the BST voltage path (BST, R3, C3,
and SW) as short as possible.
3)
Put the decoupling capacitor as close to the
VCC and GND pins as possible.
6)
Use a four-layer board to achieve better
thermal performance.
4)
Keep the switching node SW short and away
from the feedback network.
MP28248 Rev. 1.0
1/5/2012
The external feedback resistors should be placed
next to the FB pin. Make sure that there is no via
on the FB trace.
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18
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
PACKAGE INFORMATION
QFN12 (2x3mm)
1.90
2.10
PIN 1 ID
MARKING
12
0.35
0.45
2.90
3.10
PIN 1 ID
INDEX AREA
0.45
0.55
0.20
0.30
11
1
0.35
0.45
1.10
0.40
0.00
0.20
0.30
0.50
BSC
5
7
0.35
0.45
TOP VIEW
0.35
0.45
6
BOTTOM VIEW
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
1.90
0.60
0.25
1.80
1.30
0.90
0.60
0.20
0.00
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) JEDEC REFERENCE DRAWING IS JEDEC MO-220
5) DRAWING IS NOT TO SCALE.
0.25
0.50
0.70
1.45
0.70
0.25
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP28248 Rev 1.0
1/5/2012
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19