Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package A 18-pin DIP The merging of low-power CMOS logic and bipolar output power drivers permit the A6841 integrated circuits to be used in a wide variety of peripheral power driver applications. Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The 500 mA NPN Darlington outputs, with integral transient-suppression diodes, are suitable for use with relays, solenoids, and other inductive loads. All package variations of the A6841 offer premium performance with a minimum output-breakdown voltage rating of 50 V (35 V sustaining). All drivers can be operated with a split supply where the negative supply is up to –20 V. Package LW 18-pin Wide Body SOIC Package LW-20 20-pin Wide Body SOIC The CMOS inputs are compatible with standard CMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, drivers can be cascaded for interface applications requiring additional drive lines. The A6841SA devices are furnished in a standard 18-pin plastic DIP. The A6841SLW device is available in an 18-lead SOIC package. A 20-pin SOIC version, A6841SLW-20 has improved thermal characteristics. The SOIC drivers are also available for operation to a temperature of –40°C (part number suffix ELW). These devices are lead (Pb) free, with 100% matte tin plated leadframes. FEATURES ABSOLUTE MAXIMUM RATINGS Output Voltage VCE ..............................................................50 V VCE(SUS) (for inductiove load applications) .......35 V Logic Supply Voltage, VDD...................................7 V Emitter Supply Voltage, VEE.............................–20 V Input Voltage Range, VIN ..............–0.3 V to VDD +0.3 V Continuous Output Current (each output), IOUT ... 500 mA Package Power Dissipation, PD, see chart, page 6 Operating Temperature Range Ambient Temperature, TA ............–20°C to +85°C Storage Temperature, TS ..........–55°C to +150°C Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. 3.3 V to 5 V logic supply range Power on reset (POR) To 10 MHz data input rate CMOS, TTL compatible inputs –40°C operation available Low-power CMOS logic and latches Schmitt trigger inputs for improved noise immunity High-voltage current-sink outputs Internal pull-up/pull down resistors Output transient-protection diodes Single or split supply operation APPLICATIONS Relays Solenoids Inductive loads Use the following complete part numbers when ordering: Part Number A6841SA-T A6841SLW-T A6841SLW-20-T A6841ELW-T A6841ELW-20-T Package 18-pin DIP 18-pin wide body SOIC 20-pin wide body SOIC (enhanced thermals) 18-pin wide body SOIC 20-pin wide body SOIC (enhanced thermals) Ambient –20ºC to +85ºC –20ºC to +85ºC –20ºC to +85ºC –40ºC to +85ºC –40ºC to +85ºC Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Functional Block Diagram C LOC K LOG IC S UP P LY V DD S E R IAL DAT A IN S E R IAL DAT A OUT S E R IAL-P AR ALLE L S HIF T R E G IS T E R LOG IC G R OUND S T R OB E LAT C HE S OUT P UT E NAB LE (AC T IV E LOW) MOS B IP OLAR VE E or P OWE R G R OUND VE E or P OWE R G R OUND S UB OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 Typical Input Circuits K Typical Output Driver VDD K OUT STROBE OUTPUT ENABLE VEE SUB VDD CLOCK SERIAL DATA IN www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, Vee = 0 V, logic supply operating voltage Vdd = 3.0 V to 5.5 V Vdd = 3.3 V Characteristic Min. Typ. Typ. Max. Units VOUT = 50 V – – 10 – – 10 μA IOUT = 350 mA, L = 3 mH 35 – – 35 – – V IOUT = 100 mA – – 1.1 – – 1.1 V IOUT = 200 mA – – 1.3 – – 1.3 V V Symbol Output Leakage Current ICEX Output Sustaining Voltage VCE(SUS) Collector–Emitter Saturation Voltage VCE(SAT) Test Conditions IOUT = 350 mA Input Voltage Input Resistance Maximum Clock Frequency2 – – 1.6 – – 1.6 2.2 – – 3.3 – – V VIN(0) – – 1.1 – – 1.7 V kΩ 50 – – 50 – – VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V fc Logic Supply Current Max. Min. VIN(1) RIN Serial Data Output Voltage Vdd = 5 V 10 – – 10 – – MHz IDD(1) One output on, OE = L, ST = H – – 2.0 – – 2.0 mA IDD(0) All outputs off, OE = H, ST = H, P1 through P8 = L – – 100 – – 100 μA μA Clamp Diode Leakage Current Ir Vr = 50 V – – 50 – – 50 Clamp Diode Forward Voltage Vf If = 350 mA – – 2 – – 2 V tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Enable-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Fall Time tf VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Rise Time tr VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs IOUT = ±200 μA – 50 – – 50 – ns Strobe-to-Output Delay Clock-to-Serial Data Out Delay tp(CH-SQX) 1Positive (negative) current is defined as conventional current going into (coming out of) the specified device pin. 2Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. Truth Table Serial Data Clock Input Input Shift Register Contents I8 Serial Data Output R1 R2 ... R7 R7 R1 R2 ... R7 R7 R1 R2 R3 ... R8 R8 X X X P8 P8 I1 I2 H H L L X X I3 X ... ... P1 P2 P3 ... L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State Latch Contents Strobe Input I1 I2 Output Contents I1 I2 I3 ... I8 ... I8 L R1 R2 R3 ... R8 H P1 P2 P3 ... P8 L P 1 P2 P3 ... P8 X X H H X I3 Output Enable Input X ... H H ... H R = Previous State OE = Output Enable ST = Strobe www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% t p(CH-SQX) SERIAL DATA OUT DATA 50% D 50% STROBE OUTPUT ENABLE E LOW = ALL OUTP UTS E NABLE D tp(STH-QH) tp(STH-QL) 90% DATA OUT N 10% HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D) OUTPUT ENABLE 50% t en(BQ) tr tf t dis(BQ) OUT N 10% Key Description A Data Active Time Before Clock Pulse (Data Set-Up Time) B DATA 90% 50% Symbol tsu(D) Time (ns) Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50 NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Powering-on with the inputs in the low state ensures that the registers and latches power-on in the low state (POR). Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. 25 Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF). The information stored in the latches or shift register is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Terminal List Table Name Description Pin 18-pin 20-pin VEE Power Ground to substrate 1, 9 1, 9 CLK Clock 2 2 DATA IN Serial Data In 3 3 GND Logic Ground 4 4 VDD Logic Supply 5 5 Serial Data Out, for cascading devices 6 6 DATA OUT ST Strobe 7 7 OE Output Enable (active low) 8 8 Common to +VL , for inductive loads 10 12 NC Not connected – 10, 11 OUT8 Sink Output 8 11 13 OUT7 Sink Output 7 12 14 OUT6 Sink Output 6 13 15 OUT5 Sink Output 5 14 16 OUT4 Sink Output 4 15 17 OUT3 Sink Output 3 16 18 OUT2 Sink Output 2 17 19 OUT1 Sink Output 1 18 20 Allowable Package Power Dissipation, PD 2.5 18-P IN DIP , R θJA = 60°C /W 2.0 20-LE AD S OIC , R θJA = 70°C /W P OWE R DIS S IP A T ION (W) K 18-LE AD S OIC , R θJA = 80°C /W 1.5 1.0 0.5 0 25 50 75 100 125 A MB IE NT T E MP E R A T UR E (º C ) 150 www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package LW Package LW[TBD] (20-pin Wide Body SOIC) (18-pin Wide Body SOIC) 1 18 Package A (18-pin DIP) VE E 1 20 OUT 1 19 OUT 2 18 OUT 3 17 OUT 4 16 OUT 5 15 OUT 6 S UB 3 LOGIC GROUND 4 LOGIC SUPPLY 5 SERIAL DATA OUT 6 STROBE 7 OUTPUT ENABLE VEE 8 9 C LOC K 2 CLK 17 OUT 2 DAT A IN 3 16 OUT 3 G ND 4 15 OUT 4 LOG IC S UP P LY 5 VDD 14 OUT 5 DAT A OUT 6 13 OUT 6 S T R OB E 7 ST 14 OUT 7 ST 12 OUT 7 OUT P UT E NAB LE 8 OE 13 OUT 8 OUT 8 VE E 9 12 K 11 NO C ONNE C T . 11 OE 10 C LK VDD LAT C HE S 2 OUT 1 S HIF T R E G IS T E R CLOCK SERIAL DATA IN 18 SUB LATCHES 1 SHIFT REGISTER VEE S UB NO C ONNE C T . K SUB 10 NC NC Note the 18-pin DIP package and the SOIC packages are electrically identical and share common terminal number assignments. Typical Application Relay/solenoid driver using split supply +5 V –15 V +30 V 18 1 S UB S E R IAL DAT A IN 3 C LK 4 5 V DD 17 16 LAT C HE S 2 S HIF T R E G IS T E R C LOC K 15 14 S E R IAL DAT A OUT 6 S T R OB E 7 ST 12 OUT P UT E NAB LE 8 OE 11 13 10 9 S UB www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6 Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package A 18-pin DIP Dimensions in Inches (controlling dimensions) 18 0.014 0.008 10 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 0.920 0.880 9 0.005 BSC MIN 0.210 MAX 0.150 0.115 0.015 MIN 0.022 0.014 Dwg. MA-001-18A in Dimensions in Millimeters (for reference only) 0.355 0.204 10 18 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 23.37 22.35 9 0.13 BSC MIN 5.33 MAX 3.81 2.93 0.39 MIN 0.558 0.356 Dwg. MA-001-18A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7 Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package LW 18-pin Wide Body SOIC Dimensions in Inches (for reference only) 18 10 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0° TO 8° BSC 0.4625 0.4469 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-18A in Dimensions in Millimeters (controlling dimensions) 18 10 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 11.75 11.35 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-18A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 Data Sheet 26185.114B A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package LW-20 20-pin Wide Body SOIC Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0° TO 8° BSC 0.5118 0.4961 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-20 in Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 13.00 12.60 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 9 DABiC-5 8-Bit Serial Input Latched Sink Drivers The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2004, 2005 AllegroMicrosystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 10 Data Sheet 26185.114B A6841