ATMEL AT71200 8m-pixel color image sensor Datasheet

Features
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Full-field Image Sensor 3500 x 2300 Pixels
Pixel 10 µm x 10 µm Photo-MOS
Image Zone: 35 mm x 23 mm
Additional Full-frame Operating Mode: 2627 x 2300 pixels of 10 µm x 10 µm (3 zones)
Frame Readout Through One, Two or Four Outputs
Built-in Region of Interest (ROI) Selection
Data Rates Up to 4 x 25 MHz (Compatibility with 10 Frames/Seconds)
High Dynamic Range (Up to 3000), at Room Temperature and at 25 MHz Frequency
Very Low Dark Current (MPP Mode)
Bayer Standard Color Mosaic
Flexibility and Performance Make Device Suitable for Digital Photography, Graphic
Arts, Medical and Industrial Applications
8M-pixel Color
Image Sensor
Description
Atmel’s AT71200M is a progressive scan sensor based on charge-coupled device
(CCD) technology. It can be used in a wide range of applications thanks to operating
mode flexibility, very high definition and high dynamic range.
AT71200M
The nominal photosensitive area is made up of 2300 x 3500 useful pixels and is split
into four independent zones that are driven separately by four independant four-phase
clocksets. Thus the sensor can be used in up to 12 main modes.
The large format and high definition make the device suitable for any application
requiring precision and accuracy.
The Bayer standard RGB color mosaic has been specially designed for colorimetric
applications and the three colors balanced for a 3800K standard illuminant.
Two serial registers and four independent output amplifiers offer a high-frequency
functionality of up to 10 frames per second and a 12-bit dynamic range.
Rev. 2133A–IMAGE–02/03
1
Pinout
Figure 1. AT71200M Pinout – Top View
VGS3
ΦS3
ΦLA8 ΦLA5
18
VOS3 VDR3 VGL3
ΦR3
VSS
17
VDEA
VSS
16
FCA
ΦTA
19
15
14
VDD3
VS3
VSS
ΦLA1
ΦLA7 ΦLA3
LA2
VSS
ΦLA6
ΦLA4 ΦS4
VGS4
ΦR4
VGL4
VSS
VS4
VDR4 VOS4
VSS
Register A
VOS3
VDD4
VSS
VOS4
VSS1 VFCA
ΦPB4 ΦPB3
ΦPA3 ΦPA4
Zone A
ΦPB1 ΦPB2
ΦPA2 ΦPA1
Zone B
6
5
4
Zone C
ΦPD1 ΦPD4
ΦPD2 ΦPD3
2
1
2
ΦPC3 ΦPC2
Zone D
VFCB VSS1
Register B
VOS1
3
ΦPC4 ΦPC1
VSS
VSS
VOS1 VDR1
VGL1 ΦR1
VDD1
VS1
VGS1
ΦS1
A
B
C
D
VSS
ΦLB2
ΦLB4 ΦLB1
E
F
ΦTB
ΦFCB
VSS
VDEB
VOS2
ΦLB3 ΦLB7
ΦLB6
VSS
ΦR2
VGL2 VDR2 VOS2
VSS
VSS
ΦLB5
ΦLB8
ΦS2
VGS2 VS2
G
H
J
K
L
M
N
VDD2
P
AT71200M
2133A–IMAGE–02/03
AT71200M
Table 1. AT71200M Pinout
Signal Name
Pin Number
Function
ΦLB[1:8]
F1, F2, G2, E1, J1, J2, H2, K1
B readout register clocks
ΦLA[1:8]
J19, J18, H18, K19, F19, F18,
G18, E19
A readout register clocks
ΦS[1:4]
D1, L1, D19, L19
Summing clocks of the outputs 1, 2, 3 and 4
VGL[1:4]
C2, M2, C18, M18
Readout gate bias of the outputs 1, 2, 3 and 4
VGS[1:4]
C1, M1, C19, M19
Output gate bias of the outputs 1, 2, 3 and 4
VOS[1:4]
A2, P2, A18, P18
Output video signals 1, 2, 3 and 4
VDD[1:4]
A1, P1, A19, P19
Output amplifier drain supplies of the outputs 1, 2, 3 and 4
VS[1:4]
B1, N1, B19, N19
Output amplifier source biases of the outputs 1, 2, 3 and 4
ΦR[1:4]
D2, L2, D18, L18
Reset clocks of the outputs 1, 2, 3 and 4
VDR[1:4]
B2, N2, B18, N18
Reset bias of the outputs 1, 2, 3 and 4
ΦPA[1:4]
P14, N14, N15, P15
A image zone clocks
ΦPB[1:4]
A14, B14, B15, A15
B image zone clocks
ΦPC[1:4]
P6, P5, N5, N6
C image zone clocks
ΦPD[1:4]
A6, A5, B5, B6
D image zone clocks
ΦTA, ΦTB
B16, N4
Transfer gates from the image zone to the readout registers A
and B respectively
VDEA, VDEB
A17, P3
Shield drains
VFCA, VFCB
P16, A4
Region of interest drains
ΦFCA, ΦFCB
A16, P4
Region of interest clocks
VSS
A3, B3, B4, E2, G1, H1, K2, M3,
B17, E18, G19, H19, K18, N16,
N17, P17
Substrate bias
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2133A–IMAGE–02/03
Block Diagram
Figure 2. AT71200M Block Diagram – Top View
ΦLAi (i = 1 to 8) 2-phase horizontal clocks
Fast clear structure
(ΦFCA, VFCA)
12 pre-scan elements
VOS3
Uni- or Bi-directional Readout Register A
12
G R
G R
B G
B G
12
VOS4
ΦPAi (i = 1 to 4)
vertical clocks
873 lines - Zone A
4 dummy lines
(photosensitive)
ΦPBi (i = 1 to 4)
vertical clocks
877 lines - Zone B
16 dark references
(100% black)
16 dark references
(100% black)
Full-field Image Sensor
3500 x 2300 active pixels
877 lines - Zone C
8 insulating columns
(photosensitive)
ΦPCi (i = 1 to 4)
vertical clocks
8 insulating columns
(photosensitive)
4 dummy lines
(photosensitive)
873 lines - Zone D
First useful pixel
on VOS1 output (Blue)
VOS1
12
G R
G R
B G
B G
Uni- or Bi-directional Readout Register B
ΦLBi (i = 1 to 8) 2-phase horizontal clocks
4
ΦPDi (i = 1 to 4)
vertical clocks
12
VOS2
Fast clear structure
(ΦFCB, VFCB)
AT71200M
2133A–IMAGE–02/03
AT71200M
Architectural
Overview
General Parameters
Table 2. General Parameters
Parameters
Value
Pixel size
10 µm x 10 µm
Number of useful pixels on one line
2300
Number of useful lines
3500
Number of readout register
2
Number of outputs
4(1)
MPP technology
yes
Region of interest structures on readout registers
yes
Built-in antiblooming
no
Pixel mode
4 phase
Readout register mode
2 phase
Note:
1. The design allows the full frame to be read through one, two or four outputs.
Vertical Characteristics – AT71200M is made up of four zones, A, B, C and D. The configuration of each zone is
shown in Table 3.
Top to Bottom
Table 3. Vertical Characteristics
Zone
Configuration
4 dummy photosensitive lines
A
873 active lines, 100% photosensitive
B
877 active lines, 100% photosensitive
C
877 active lines, 100% photosensitive
873 active lines, 100% photosensitive
D
4 dummy photosensitive lines
Horizontal
Characteristics
Table 4 gives information on the characteristics seen by one output (VOS1, VOS2, VOS3 or
VOS4) in different readout modes.
Table 4. Horizontal Characteristics
Readout Mode
Characteristic
One Output
Two Outputs on Same Register
Pre-scan elements
12
12
Dark references
16
16
Insulating elements
8
8
2300
1150
Useful pixels
5
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Color Mosaic
Architecture
Output Amplifiers
The color mosaic architecture corresponds to the Bayer standard represented by the following grid:
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
The charge packets are clocked to the output nodes and the charges are converted to
voltages. The potential at the output node is read through two stage source follower
amplifiers. Refer to Figure 3.
Figure 3. On-chip Output Amplifier Structure
VDD
Output
Node
VS
6
AT71200M
2133A–IMAGE–02/03
AT71200M
Absolute Maximum Ratings*
Storage Temperature Range ......................... -55°C to +150°C
Operating Temperature Range........................ -40°C to +85°C
Thermal Cycling..........................................................15°C/mn
*NOTICE:
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Electrical limits of applied signals are given in Table 5.
Shorting the video output to VSS or VDD, even temporarily, can permanently damage the output amplifier.
Due to MPP mode or negative voltages, image zone gates and region of interest gates do not include ESD protection.
To avoid degradation, the devices (including pins and package) should be handled with a grounded bracelet and stored
on conductive layer used for shipment.
Table 5. Maximum Applied Voltages(1)
Signal Name
Parameter
Min
Max
Unit
ΦLA[1:8]
Readout A Register Clocks
-0.3
+15
V
ΦLB[1:8]
Readout B Register Clocks
-0.3
+15
V
ΦS[1:4]
Summing Gate
-0.3
+15
V
VGL[1:4]
Readout Gate
-0.3
+15
V
VGS[1:4]
Output Gate
-0.3
+15
V
VOS[1:4]
Output Video Signal
-0.3
+15
V
VDD[1:4]
Amplifier Drain Supply
-0.3
+15
V
VS[1:4]
Source Bias
-0.3
+15
V
ΦR[1:4]
Reset Gate
-0.3
+15
V
VDR[1:4]
Reset Bias
-0.3
+15
V
ΦPA[1:4]
Image Zone A Clocks
-15 and ΦPA[other] - 20
+15 and ΦPA[other] + 20
V
ΦPB[1:4]
Image Zone B Clocks
-15 and ΦPB[other] - 20
+15 andΦPB[other] + 20
V
ΦPC[1:4]
Image Zone C Clocks
-15 and ΦPC[other] - 20
+15 and ΦPC[1:4] + 20
V
ΦPD[1:4]
Image Zone D Clocks
-15 and ΦPD[other] - 20
+15 and ΦPD[other] + 20
V
ΦTA
Transfer Gates Zone A
ΦLA - 15 and ΦPA[4] - 15
+15 and ΦPA[4] + 15
V
ΦTB
Transfer Gates Zone B
ΦLB - 15 and ΦPD[4 ] - 15
+15 and ΦPD[4] + 15
V
VDEA, VDEB
Shield Drains
-0.3
+15
V
VFCA, VFCB
Region Of Interest Drains
-0.3
+15
V
ΦFCA
Region Of Interest Gates Zone A
ΦLA[1:8] - 15
+15
V
ΦFCB
Region Of Interest Gates Zone B
ΦLB[1:8] - 15
+15
V
VSS
Substrate Bias
0
V
Note:
1. If not specified, all voltages are applied with respect to the substrate VSS.
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2133A–IMAGE–02/03
DC Characteristics
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VS(1)
Source bias
0
0
1
V
< 12 mA
14.5
15
15.5
V
< 12 mA
V
–
VDD
Note:
8
(1)
Amplifier drain supply
Typical Currents
VSS
Substrate bias
0
0
VGS
Output gate
7
7.5
8
V
< 1 µA
VDR
Reset diode
13.5
14
14.5
V
< 5 µA
VGL
Readout gate
3
3.5
4
V
< 1 µA
VDE
Shield drain
3
5
6
V
< 1 µA
VFC
Regions of interest drains
12.5
13
13.5
V
< 5 µA
1. If corresponds to inactive output, may be stated to [3V, 7V] in order to reduce power consumption.
AT71200M
2133A–IMAGE–02/03
AT71200M
Drive Clock Characteristics
Symbol
ΦPij
Parameter
(1)(2)
Image Zone Clocks
ΦLmn(3)(4)
Readout Register Clocks
ΦSj(2)
Summing Gates
ΦRj(2)
Reset Gates
ΦTm(3)
Transfer Gates
ΦFCm(3)
Notes:
1.
2.
3.
4.
Region of Interest Gates
State
Minimum
Typical
Maximum
Unit
Low
-10
-9
-8
V
High
+2.5
+3
+3.5
V
Low
0
0
+0.5
V
High
+7.5
+8
+9
V
Low
0
0
+0.5
V
High
+7.5
+8
+9
V
Low
+1
+2
+3
V
High
+8
+9
+10
V
Low
-6
-5
-4
V
High
+2.5
+3
+3.5
V
FC
inactive
-3.5
-2.5
-2
V
Low
0
0
+0.5
V
High
+3.5
+4
+4.5
V
Remarks
For each A, B, C and D
zone, the typical
capacitances to drive are
CPij approx. 12 nF
After the eight clocks have
been grouped together to
form the two clocks ΦL1
and ΦL2, the typical
capacitances to drive for
each register A or B are
CΦL1 approx. 310 pF and
CΦL2 approx. 310 pF
For each ΦSj, the typical
capacitance to drive is
CΦSj approx. 40 pF
For each ΦRj, the typical
capacitance to drive is
CΦRj approx. 40 pF
For each ΦTm, the typical
capacitance to drive is
CΦTm approx. 150 pF
For each ΦFCm, the typical
capacitance to drive is
CΦFCm approx. 50 pF
i = A, B, C or D
j = 1, 2, 3 or 4
m = A or B
n = 1, 2, 3, 4, 5, 6, 7 or 8
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2133A–IMAGE–02/03
Operating Modes
For the required readout mode, the vertical and horizontal clocks must be tied together
externally as shown in Figure 4.
Figure 4. Operating Modes
3508 transfers min
NBV = 3508
VERTICAL TRANSFER
3508 transfers min 1754 transfers min
NBV = 3508
NBV = 1754
2631 transfers min
NBV = 2631
1-2-3 modes
4-5-6 modes
10-11-12 modes
ΦPA1=ΦPB1=ΦPC1=ΦPD1=
ΦPA2=ΦPB2=ΦPC2=ΦPD2=
ΦPA3=ΦPB3=ΦPC3=ΦPD3=
ΦPA4=ΦPB4=ΦPC4=ΦPD4=
ΦTA = Low Level
3
ΦA
ΦB
ΦC
ΦD
ΦTB = ΦA
Inactive
ΦPA1=ΦPB1=ΦPC1=ΦPD1=
ΦPA2=ΦPB2=ΦPC2=ΦPD2=
ΦPA3=ΦPB3=ΦPC3=ΦPD3=
ΦPA4=ΦPB4=ΦPC4=ΦPD4=
ΦTA = ΦA
4
ΦA
ΦB
ΦC
ΦB
ΦTB = Low Level
3
Mode1
7-8-9 modes
4
ΦPA1=ΦPB1=ΦPC1=ΦPD1=
ΦPA2=ΦPB2=ΦPC2=ΦPD2=
ΦPA3=ΦPB3=ΦPC3=ΦPD3=
ΦPA4=ΦPB4=ΦPC4=ΦPD4=
ΦTA = ΦA
ΦTB = ΦA
3
Mode4
ΦA
ΦB
ΦC
ΦD
ΦPA1=ΦPB1=ΦPC1=ΦPD1=
ΦPA2=ΦPB2=ΦPC2=ΦPD2=
ΦPA3=ΦPB3=ΦPC3=ΦPD3=
ΦPA4=ΦPB4=ΦPC4=ΦPD4=
ΦTA = ΦA
4
ΦTB = ΦA
3
Mode7
ΦA
ΦB
ΦC
ΦD
4
2336 PIXELS PERIODS
NBH = 2336
4-7-10 modes
Mode10
ΦLA1=ΦLA3=ΦLA5=ΦLA8=ΦL1
ΦLA2=ΦLA4=ΦLA6=ΦLA7=ΦL2
3
Inactive
2
1
4
3
Mode2
Inactive
2
1
2
1
2
4
3
4
3
4
Mode5
Mode8
ΦLB1=ΦLB4=ΦLB5=ΦLB7=ΦL1
ΦLB2=ΦLB3=ΦLB6=ΦLB8=ΦL2
2336 PIXELS PERIODS
NBH = 2336
5-8-11 modes
Mode11
ΦLA1=ΦLA4=ΦLA5=ΦLA7=ΦL1
ΦLA2=ΦLA3=ΦLA6=ΦLA8=ΦL2
2-8-11 modes
1
3
Inactive
2
1
4
3
Mode3
Inactive
2
1
2
1
2
4
3
4
3
4
Mode6
Mode9
ΦLB1=ΦLB3=ΦLB5=ΦLB8=ΦL1
ΦLB2=ΦLB4=ΦLB6=ΦLB7=ΦL2
1186 PIXELS PERIODS
NBH = 1186
HORIZONTAL TRANSFER
1-7-10 modes
1
6-9-12 modes
Mode12
ΦLA1=ΦLA4=ΦLA5=ΦLA8=ΦL1
ΦLA2=ΦLA3=ΦLA6=ΦLA7=ΦL2
3-9-12 modes
1
Note:
10
2
1
Inactive
2
1
2
1
2
ΦLB1=ΦLB4=ΦLB5=ΦLB8=ΦL1
ΦLB2=ΦLB3=ΦLB6=ΦLB7=ΦL2
Symbols ΦA, ΦB, ΦC and ΦD correspond to the clocks described in the full-frame mode timing diagrams. Abbreviations NBV
and NBH correspond respectively to the vertical and horizontal number of transfers.
The unused horizontal clocks (ΦL, ΦR, ΦS) must be stated to higher level of ΦL.
AT71200M
2133A–IMAGE–02/03
AT71200M
Timing Diagrams
Figure 5. Full-frame Mode Timing Diagram
Cleaning
Integration time
Readout time
Cleaning
NBV pulses
1234
ΦA ...
nbv
...
ΦB ...
...
ΦC ...
...
ΦD ...
...
NBH pulses
ΦL1
See expanded view in Fig. 6
L2
ΦR
Note:
ΦA, ΦB, ΦC, ΦD, ΦL1 and ΦL2 (command phases) and NBV and NBH (number of vertical transfers and number of horizontal
transfers respectively) are defined in Figure 4.
11
2133A–IMAGE–02/03
Figure 6. Line Timing Diagram
t0
ΦA
ΦB
ΦC
ΦD
t0
9 t0
t0
11 t0
ΦL1
ΦL2
ΦR
First prescan
Figure 7. Region of Interest Operating Mode
ΦPij
First following line is a dummy line
ΦLi1
ΦLi2
ΦFCi
ta
Fast clear startup
Note:
12
ta
tb
1 line
clearance
Fast clear stop
Typical values of ta, tb, tc, ta ≥ 150 ns, tb ≥ 150 ns, tc ≥ 150 ns
AT71200M
2133A–IMAGE–02/03
AT71200M
Table 6. Typical TR and TF (Time Rise, Time Fall) for Phases
Frame Rate
Characteristics
Phase
Time
ΦP1
500 ns
ΦP2
500 ns
ΦP3
500 ns
ΦP4
500 ns
ΦFC
50 ns
VFC
50 ns
ΦL1
10 ns
ΦL2
10 ns
ΦS
10 ns
ΦR
4 ns
Table 7. Frame Rate Characteristics
One Output
(Modes 1, 2, 3, 4)
Two Outputs
(Modes 13, 14)
Four Outputs
(Mode 15)
Typical 2.8 fps
Typical 5.1 fps
Typical 10.2 fps
Without binning
Table 7 gives typical values for full-frame mode where:
Horizontal pixel frequency = 25 MHz
Note:
•
•
Vertical transfer time TV = 11 x t0 = 10 µs
(delay times before and after line transfer t1 = t2 = t0)
•
Integration time = 0s:
Table 8. Electrical and Miscellaneous Characteristics
Symbol
Parameters
Minimum
Typical
Maximum
Unit
VREF
DC output level
10
V
ZOUT
Output impedance
230
Ohms
Output amplifier supply current
10
15
mA
7.3
7.6
8.0
µV/e-
IDD
(1)
CVF
Charge-to-voltage conversion factor
TV
Vertical transfer time
5
10
Maximum Readout pixel frequency
25
–
FH
Note:
µs
–
MHz
1. For each output.
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Electrooptical Data
Table 9. Performance Data(1)
Symbol
Minimum
Typical
Maximum
Unit
Pixel saturation output voltage
500
600
700
mV
Responsivity blue
0.45
0.60
V/(µJ/cm2)
Responsivity green
0.45
0.60
V/(µJ/cm2)
R-Red(2)
Responsivity red
0.70
0.92
V/(µJ/cm2)
R-Blue(2)
Responsivity blue
0.19
V/(lux.s)
Responsivity green
0.19
V/(lux.s)
Responsivity red
0.25
V/(lux.s)
VSAT
R-Blue(2)
R-Green(2)
R-Green(2)
R-Red
(2)
Photo response non uniformity, σ
PRNU
1
6
% VOS
DSI1
Image zone MPP mode
0.3
mV/s
DSI2
Image zone non-MPP mode
60
mV/s
DSR
Readout register (non-MPP mode)
150
mV/s
(3)
VDS
Average dark signal
7
20
mV
Dark signal non-uniformity, σ
3.5
5.5
mV
VN
Temporal RMS noise in darkness at BW = 150 MHz
270
µV
DR
Dynamic range
67
dB
Linearity
1
%
Modulated transfer function
86
%
(3)
DSNU
MTF
(4)
VCTE(5)
(5)
HCTE
Notes:
14
Parameters
Vertical charge transfer efficiency (per stage)
0.99995
0.999998
–
Horizontal charge transfer efficiency (per stage)
0.99995
0.999998
–
1. General measurement conditions:
TC = 25°C (chip temperature)
Vertical transfer time TV = 10 ms
Readout pixel frequency FH = 5 MHz
Readout through 4 outputs and standard mode 9 (see figure 4)
3200K Halogen lamp with 2 mm BG38 filter at f/11 aperture
2. Blue, Green, Red channels
The responsivity are well balanced for 3800K source
3. Integration time Ti = 10s in darkness
4. Green
5. Output voltage > 10% VSAT
AT71200M
2133A–IMAGE–02/03
AT71200M
Figure 8. Typical Spectral Response with BG38 Infrared Filter (2 mm thickness), light source powered between 400 and
700 nm
2.0
1.8
1.6
V/µJ/cm²
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
350
400
450
500
550
600
650
700
750
nm
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Image Grade
Table 10 gives results of image grade testing.
Table 10. Image Grade(1)
Blemishes
Cluster 1
(2)
Grade
Total
E
≤ 500
3
≤ 30
50
≤6
H
≤ 300
3
≤ 10
50
0
Notes:
D min
Cluster 2
(2)
Total
D min
Total
Column
(2)
D min
100
Total
D min(2)
≤4
150
0
1. Testing has been carried out under the following conditions:
Operating temperature: 25°C (unless otherwise specified)
Illumination conditions: 3200K Halogen lamp with BG38 Infrared filter and f/11 aperture
Integration time = 10s in darkness
Test under illumination at 50% of saturation level
Standard mode, TV = 10 µs, FH = 5 MHz
2. D min: Minimum number of pixels separating defects in any direction. All occurences are non-contiguous.
Definitions
Defect Sizes
Type
Description
Blemish
1 x 1 defect
Cluster
Blemish grouping of not more than a given number of adjacent defects:
1 x 1 < cluster 1 size ≤ 2 x 2
2 x 2 < cluster 2 size ≤ 5 x 5
Column
One-pixel-wide column with more than seven contiguous defective pixels
Defects in Darkness
Type
Description
Blemish/Cluster
Pixel signal deviation of more than 200 mV from the average output signal
Column
Column signal deviation of more than 20 mV from the average output signal
Defects under Illumination
Type
Description
Blemish/Cluster
Pixel deviation of more than +20% or -30% from the average output signal
Column
Column deviation of more than 10% from the average output signal
16
AT71200M
2133A–IMAGE–02/03
AT71200M
33.02 ± 0.40
45.72 ± 0.5
19
18
17
16
15
14
8 X 2.54
50.60 ± 0.51
+0.05
-0.30
0.46 ± 0.05
1.20
38.0 ± 0.38
19.5 ± 0.1
6
38.0 ± 0.1
Y = 42.80 ± 0.075
2.0 ± 0.1
Package Drawing
6
5
4
3
2
1
6
4.57 ± 0.25
X = 7.50 ± 0.075
3
2
Z top = 1.73 +0.25
-0.41
3.26 ± 0.33
4.52 +0.4
-0.65
2.54 typ
first pixel
P N M L K J H G F E D C B A
5
2.54 typ
1 Anti-reflective window 400-700 nm 98% min transmission
2 Photosensitive area
3 Z top = optical distance between top surface and 2
4 Zbot = optical distance between back side and 2
5 pin A1 index mark
6 Mechanical references/die positionning (first pixel)
4 Zbot = 2.79 +0.22
-0.30
All dimensions in mm
17
2133A–IMAGE–02/03
Ordering Information
Figure 9. Ordering Code Key
1
2
3
4
5
6
7
8
9 10 11
AT71200
Customer specification
Technological variants
Temperature range:
C: 0 C to +70 C
Package families:
R: Pin Grid Array (PGA)
Image grade:
E: Standard
H: High
Quality assurance level
- : Standard screening
E = On chip color filter
Package variants:
N: Non-sealed window
R: Anti-reflective window
The following part numbers are available:
•
AT71200MCRERE: version grade E
•
AT71200MCRHRE: version grade H
18
AT71200M
2133A–IMAGE–02/03
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