Numonyx M29DW640F70N1 64 mbit (8mb x8 or 4mb x16, multiple bank, page, boot block) 3v supply flash memory Datasheet

M29DW640F
64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block)
3V Supply Flash Memory
Feature summary
■
Supply voltage
– VCC = 2.7V to 3.6V for Program, Erase and
Read
– VPP =12V for Fast Program (optional)
■
Asynchronous Page Read mode
– Page Width 8 Words
– Page Access 25, 30ns
– Random Access 60, 70ns
■
Programming time
– 10µs per Byte/Word typical
– 4 Words / 8 Bytes at-a-time Program
■
Memory blocks
– Quadruple Bank Memory Array:
8Mbit+24Mbit+24Mbit+8Mbit
– Parameter Blocks (at both Top and Bottom)
■
■
Dual operations
– While Program or Erase in a group of
banks (from 1 to 3), Read in any of the
other banks
Program/Erase Suspend and Resume
– Read from any Block during Program
Suspend
– Read and Program another Block during
Erase Suspend
■
Unlock Bypass Program command
– Faster Production/Batch Programming
■
VPP/WP pin for Fast Program and Write Protect
■
Temporary Block Unprotection mode
■
Common Flash Interface
– 64 bit Security Code
■
Extended Memory Block
– Extra block used as security block or to
store additional information
December 2007
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZE)
6 x 8 mm
■
Low power consumption
– Standby and Automatic Standby
■
100,000 Program/Erase cycles per block
■
Electronic Signature
– Manufacturer Code: 0020h
– Device Code: 227Eh + 2202h + 2201
■
ECOPACK® packages available
Rev 4
1/74
www.numonyx.com
1
Contents
M29DW640F
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
2.1
Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2
Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 13
2.5
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8
VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9
Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10
Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.11
Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.12
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.13
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6
Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.2
Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
2/74
3.6.1
Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.1
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.2
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.3
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M29DW640F
4.2
4.3
5
Contents
4.1.4
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.5
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.6
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.7
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.8
Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.9
Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.10
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.1
Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.2
Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.3
Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.4
Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.5
Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.6
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.7
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.8
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.1
Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.2
Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.3
Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 29
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.1
Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.2
Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.3
Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.4
Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 36
7
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3/74
Contents
M29DW640F
Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C.1
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C.2
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Appendix D Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
D.1
Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
D.2
In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4/74
M29DW640F
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 31
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Toggle and Alternative Toggle Bits AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 52
TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . . . . 53
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Extended Block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5/74
List of figures
M29DW640F
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
6/74
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Toggle and Alternative Toggle Bits mechanism, Chip Enable controlled . . . . . . . . . . . . . . 49
Toggle and Alternative Toggle Bits mechanism, Output Enable controlled . . . . . . . . . . . . 49
Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 52
TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . . . . 53
Programmer Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
In-System Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
M29DW640F
1
Summary description
Summary description
The M29DW640F is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.
The device features an asymmetrical block architecture, with 16 parameter and 126 main
blocks, divided into four Banks, A, B, C and D, providing multiple Bank operations. While
programming or erasing is underway in one group of banks (from 1 to 3), reading can be
conducted in any of the other banks. The bank architecture is summarized in Table 2. Eight
of the Parameter Blocks are at the top of the memory address space, and eight are at the
bottom.
The M29DW640F has one extra 256 Byte block (Extended Block) that can be accessed
using a dedicated command. The Extended Block can be protected and so is useful for
storing security information. However the protection is irreversible, once protected the
protection cannot be undone.
Each block can be erased independently, so it is possible to preserve valid data while old
data is erased. The blocks can be protected to prevent accidental Program or Erase
commands from modifying the memory. Program and Erase commands are written to the
Command Interface of the memory. An on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase
operation can be detected and any error conditions identified. The command set required to
control the memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12x20mm), and TFBGA48 (6x8mm, 0.8mm pitch)
packages.
In order to meet environmental requirements, Numonyx also offers the in ECOPACK®
packages. ECOPACK packages are Lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
The memory is supplied with all the bits erased (set to ’1’).
7/74
Summary description
Figure 1.
M29DW640F
Logic diagram
VCC VPP/WP
22
15
A0-A21
DQ0-DQ14
W
E
DQ15A–1
M29DW640F
G
RB
RP
BYTE
VSS
Table 1.
8/74
Signal names
A0-A21
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organization Select
VCC
Supply voltage
VPP/WP
VPP/Write Protect
VSS
Ground
NC
Not Connected Internally
AI11247
M29DW640F
Figure 2.
Summary description
TSOP connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
W
RP
A21
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
12
37
M29DW640F
13
36
24
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI11248
9/74
Summary description
Figure 3.
M29DW640F
TFBGA48 connections (top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP/WP
RP
A8
A12
C
A2
A6
A18
A21
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI11
1. Balls are shorted together via the substrate but not connected to the die.
Table 2.
Bank
10/74
Bank architecture
Bank
Size
Parameter Blocks
Main Blocks
No. of Blocks
Block Size
No. of Blocks
Block Size
A
8 Mbit
8
8KByte/ 4 KWord
15
64KByte/ 32 KWord
B
24 Mbit
—
—
48
64KByte/ 32 KWord
C
24 Mbit
—
—
48
64KByte/ 32 KWord
D
8 Mbit
8
8KByte/ 4 KWord
15
64KByte/ 32 KWord
M29DW640F
Figure 4.
Summary description
Block addresses (x8)
(x8)
Address lines A21-A0, DQ15A-1
000000h
001FFFh
400000h
8 KByte or
4 KWord
40FFFFh
Total of 8
Parameter
Blocks
00E000h
Bank A
00FFFFh
010000h
01FFFFh
64 KByte or
32 KWord
Total of 48
Main Blocks
Bank C
6F0000h
8 KByte or
4 KWord
6FFFFFh
700000h
64 KByte or
32 KWord
70FFFFh
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 15
Main Blocks
0F0000h
0FFFFFh
100000h
10FFFFh
Total of 15
Main Blocks
7E0000h
64 KByte or
32 KWord
Bank D
64 KByte or
32 KWord
7EFFFFh
7F0000h
7F1FFFh
64 KByte or
32 KWord
8 KByte or
4 KWord
Total of 48
Main Blocks
Bank B
3F0000h
3FFFFFh
64 KByte or
32 KWord
Total of 8
Parameter
Blocks
7FE000h
7FFFFFh
8 KByte or
4 KWord
AI06880
1. Also see Appendix A, Table 24 for a full listing of the Block addresses.
11/74
Summary description
Figure 5.
M29DW640F
Block addresses (x16)
(x16)
Address lines A21-A0
000000h
000FFFh
200000h
8 KByte or
4 KWord
207FFFh
Total of 8
Parameter
Blocks
007000h
Bank A
007FFFh
008000h
00FFFFh
64 KByte or
32 KWord
Total of 48
Main Blocks
Bank C
378000h
8 KByte or
4 KWord
37FFFFh
380000h
64 KByte or
32 KWord
387FFFh
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 15
Main Blocks
Total of 15
Main Blocks
078000h
07FFFFh
080000h
087FFFh
3F0000h
64 KByte or
32 KWord
Bank D
64 KByte or
32 KWord
3F7FFFh
3F8000h
3F8FFFh
64 KByte or
32 KWord
8 KByte or
4 KWord
Total of 8
Parameter
Blocks
Total of 48
Main Blocks
Bank B
1F8000h
1FFFFFh
64 KByte or
32 KWord
3FF000h
3FFFFFh
8 KByte or
4 KWord
AI05555
1. Also see Appendix A, Table 24 for a full listing of the Block addresses.
12/74
M29DW640F
2
Signal descriptions
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the internal state machine.
2.3
Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
2.4
Data Input/Output or Address Input (DQ15A–1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data Input/Output to include this pin when BYTE is High and
references to the Address Inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
13/74
Signal descriptions
2.7
M29DW640F
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
2.8
VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Program
operations. This is achieved by bypassing the unlock cycles and/or using the multiple Word
(2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands. The Write
Protect function provides a hardware method of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the address space).
When VPP/Write Protect is Low, VIL, the memory protects the four outermost boot blocks;
Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low,
even when RP is at VID.
When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status
of the four outermost boot blocks (two at the top, and two at the bottom of the address
space). Program and Erase operations can now modify the data in these blocks unless the
blocks are protected using Block Protection.
Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected
(including the four outermost parameter blocks) using a High Voltage Block Protection
technique (In-System or Programmer technique). See Table 3: Hardware protection for
details.
When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock
Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes.
During Unlock Bypass Program operations the memory draws IPP from the pin to supply the
programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than
tVHVPP, see Figure 17.
Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating or unconnected or the device may
become unreliable. A 0.1µF capacitor should be connected between the VPP/Write Protect
pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during Unlock Bypass Program,
IPP.
Table 3.
VPP/WP
RP
Function
VIH
4 outermost parameter blocks protected from Program/Erase
operations
VID
All blocks temporarily unprotected except the 4 outermost blocks
VIH or VID
VID
All blocks temporarily unprotected
VPPH
VIH or VID
All blocks temporarily unprotected
VIL
14/74
Hardware protection
M29DW640F
2.9
Signal descriptions
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if VPP/WP is at VIL, then the four outermost boot blocks will remain protected even
if RP is at VID.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last.
See the Ready/Busy Output section, Table 20 and Figure 16: Reset/Block Temporary
Unprotect AC waveforms.
Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
2.10
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 20 and Figure 16: Reset/Block Temporary Unprotect
AC waveforms.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11
Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus
modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in
x8 mode, when it is High, VIH, the memory is in x16 mode.
2.12
VCC Supply Voltage
VCC provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout
voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, ICC3.
15/74
Signal descriptions
2.13
M29DW640F
VSS Ground
VSS is the reference for all voltage measurements. The device features two VSS pins both of
which must be connected to the system ground.
16/74
M29DW640F
3
Bus operations
Bus operations
There are five standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Using the multiple bank architecture of the M29DW640F, while programming or erasing is
underway in one group of banks (from 1 to 3), reading can be conducted in any of the other
banks. Write operations are only allowed in one bank at a time.
See Table 4 and Table 5, Bus operations, for a summary. Typically glitches of less than 5ns
on Chip Enable, Write Enable, and Reset pins are ignored by the memory and do not affect
bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The Page has a size of 8 Words
and is addressed by the address inputs A0-A2.
A valid Bus Read operation involves setting the desired address on the Address Inputs,
applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the value, see Figure 10: Random Read AC
waveforms, Figure 11: Page Read AC waveforms, and Table 16: Read AC characteristics,
for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure 12 and Figure 13, Write AC waveforms,
and Table 17 and Table 18, Write AC characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the
Standby current level see Table 15: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, ICC3, for Program or Erase operations until the operation completes.
17/74
Bus operations
3.5
M29DW640F
Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
3.6
Special bus operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.6.1
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 4
and Table 5, Bus operations.
3.6.2
Block Protect and Chip Unprotect
Groups of blocks can be protected against accidental Program or Erase. The Protection
Groups are shown in Appendix A, Table 24: Block addresses The whole chip can be
unprotected to allow the data inside the blocks to be changed.
The VPP/Write Protect pin can be used to protect the four outermost boot blocks. When
VPP/Write Protect is at VIL the four outermost boot blocks are protected and remain
protected regardless of the Block Protection Status or the Reset/Block Temporary
Unprotect pin status.
Block Protect and Chip Unprotect operations are described in Appendix D.
18/74
M29DW640F
Table 4.
Bus operations
Bus operations, BYTE = VIL(1)
Address Inputs
Operation
E
G
W
A21A12
A3
A2
A1
A0
Data Inputs/Outputs
Others, DQ14
DQ15A-1 -DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell address
Hi-Z
Data Output
Bus Write
VIL
VIH
VIL
Command address
Hi-Z
Data Input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code
(Cycle 1)
VIL
VIL
VIH
Read Device Code
(Cycle 2)
VIL
VIL
Read Device Code
(Cycle 3)
VIL
Extended Block
Indicator Bit
(DQ7)
Block Protection
Verification
Output Disable
VIL
VIL
VIL
VIL
Hi-Z
20h
VIL
VIL
VIL
VIH
Hi-Z
7Eh
VIH
VIH
VIH
VIH
VIL
Hi-Z
02h
VIL
VIH
VIH
VIH
VIH
VIH
Hi-Z
01h
VIL
VIL
VIH
Bank
A
VIL
VIL
VIH
VIH
Hi-Z
80h (factory locked)
00h (not locked)
VIL
VIL
VIH
Block
addrs
VIL
VIL
VIH
VIL
Hi-Z
01h (protected)
00h (unprotected)
Bank
addrs
A6 = VIL
A9 = VID,
others =X
1. X = VIL or VIH.
19/74
Bus operations
Table 5.
M29DW640F
Bus operations, BYTE = VIH (1)
Address Inputs
Operation
E
G
W
A21A12
A3
A2
A1
A0
Data Inputs/Outputs
Others
DQ15A-1, DQ14-DQ0
Bus Read
VIL
VIL
VIH
Cell address
Data Output
Bus Write
VIL
VIH
VIL
Command address
Data Input
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code
(Cycle 1)
VIL
VIL
VIH
Read Device Code
(Cycle 2)
VIL
VIL
Read Device Code
(Cycle 3)
VIL
Extended Block
Indicator Bit
(DQ7)
Block Protection
Verification
Output Disable
1. X = VIL or VIH.
20/74
VIL
VIL
VIL
VIL
0020h
VIL
VIL
VIL
VIH
227Eh
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIH
Bank
A
VIL
VIL
VIH
VIH
0080h (factory locked)
0000h (not locked)
VIL
VIL
VIH
Block
addrs
VIL
VIL
VIH
VIL
0001h (protected)
0000h (unprotected)
Bank
addrs
2202h
A6 = VIL
A9 = VID,
others =X
2201h
M29DW640F
4
Command interface
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 6, or Table 7, depending on the configuration that is being
used, for a summary of the commands.
4.1
Standard commands
4.1.1
Read/Reset command
The Read/Reset command returns the memory to its Read mode. It also resets the errors in
the Status Register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the timeout of a Block erase operation then the memory will take up to 10µs
to abort. During the abort period no valid data can be read from the memory. The
Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
4.1.2
Auto Select command
The Auto Select command is used to read the Manufacturer Code and Device Code, the
Block Protection Status and the Extended Block Indicator. It can be addressed to either
Bank. Three consecutive Bus Write operations are required to issue the Auto Select
command. The final Write cycle must be addressed to one of the Banks. Once the Auto
Select command is issued Bus Read operations to the Bank where the command was
issued output the Auto Select data. Bus Read operations to the other Bank will output the
contents of the memory array. The memory remains in Auto Select mode until a Read/Reset
or CFI Query command is issued. This command must be issued addressing the same
Bank, as was given when entering Auto Select Mode.
In Auto Select mode the Manufacturer Code can be read using a read operation, A6 and A3
to A0 each held at VIL, and A21-A19 set to the Bank Address. The other address bits may
be set to either VIL or VIH.
The Device Codes can be read using a read operation, A6 held at VIL, A3 to A0 each held at
the levels given in Table 4 and Table 5, and A21-A19 set to the Bank Address. The other
address bits may be set to either VIL or VIH.
The Block Protection Status of each block can be read using a read operation, A6 A3 A2 A0
each held at VIL, A1 held at VIH, and A21-A19 set to the Bank Address, and A18-A12
specifying the address of the block inside the Bank. The other address bits may be set to
either VIL or VIH. If the addressed block is protected then 01h is output on Data
Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
21/74
Command interface
M29DW640F
The Extended Block Status of the Extended Block can be read using a read operation, A6,
A3 and A2, at VIL, A0 and A1, at VIH, and A21-A19 set to Bank Address A. The other bits
may be set to either VIL or VIH (Don't Care). If the Extended Block is "Factory Locked" then
80h is output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output.
4.1.3
Read CFI Query command
The Read CFI Query Command is used to put the addressed bank in Read CFI Query
mode. Once in Read CFI Query mode Bus Read operations to the same bank will output
data from the Common Flash Interface (CFI) Memory Area. If the read operations are to a
different bank from the one specified in the command then the read operations will output
the contents of the memory array and not the CFI data.
One Bus Write cycle is required to issue the Read CFI Query Command. Care must be
taken to issue the command to one of the banks (A21-A19) along with the address shown in
Table 4 and Table 5 (A-1, A0-A10). Once the command is issued subsequent Bus Read
operations in the same bank (A21-A19) to the addresses shown in Appendix B (A7-A0), will
read from the Common Flash Interface Memory Area.
This command is valid only when the device is in the Read Array or Autoselected mode. To
enter Read CFI query mode from Auto Select mode, the Read CFI Query command must
be issued to the same bank address as the Auto Select command, otherwise the device will
not enter Read CFI Query mode.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Autoselected mode). A second Read/Reset command would be
needed if the device is to be put in the Read Array mode from Autoselected mode.
See Appendix B, Table 25, Table 26, Table 27, Table 28, Table 29 and Table 30 for details on
the information contained in the Common Flash Interface (CFI) memory area.
4.1.4
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 8. All Bus Read operations during the Chip Erase
operation will output the Status Register on the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
22/74
M29DW640F
4.1.5
Command interface
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks in one or more
Banks. It sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the
selected blocks is lost.
Six Bus Write operations are required to select the first block in the list. Each additional
block in the list can be selected by repeating the sixth Bus Write operation using the address
of the additional block. The Block Erase operation starts the Program/Erase Controller after
a time-out period of 50µs after the last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any more blocks. Each additional block must
therefore be selected within 50µs of the last block. The 50µs timer restarts when an
additional block is selected. After the sixth Bus Write operation a Bus Read operation within
the same Bank will output the Status Register. See the Status Register section for details on
how to identify if the Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the 50µs
time-out period. Typical block erase times are given in Table 8.
After the Erase operation has started all Bus Read operations to the Banks being erased will
output the Status Register on the Data Inputs/Outputs. See the section on the Status
Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs Bus Read operations to the Banks
where the command was issued will continue to output the Status Register. A Read/Reset
command must be issued to reset the error condition and return to Read mode.
4.1.6
Erase Suspend command
The Erase Suspend command may be used to temporarily suspend a Block or multiple
Block Erase operation. One Bus Write operation specifying the Bank Address of one of the
Blocks being erased is required to issue the command. Issuing the Erase Suspend
command returns the whole device to Read mode.
The Program/Erase Controller will suspend within the Erase Suspend Latency time (see
Table 8 for value) of the Erase Suspend Command being issued. Once the Program/Erase
Controller has stopped the memory will be set to Read mode and the Erase will be
suspended. If the Erase Suspend command is issued during the period when the memory is
waiting for an additional block (before the Program/Erase Controller starts) then the Erase is
suspended immediately and will start immediately when the Erase Resume Command is
issued. It is not possible to select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.
23/74
Command interface
M29DW640F
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
During Erase Suspend a Bus Read operation to the Extended Block will output the
Extended Block data. Once in the Extended Block mode, the Exit Extended Block command
must be issued before the erase operation can be resumed.
4.1.7
Erase Resume command
The Erase Resume command is used to restart the Program/Erase Controller after an
Erase Suspend. The command must include the Bank Address of the Erase-Suspended
Bank, otherwise the Program/Erase Controller is not restarted.
The device must be in Read Array mode before the Resume command will be accepted. An
Erase can be suspended and resumed more than once.
4.1.8
Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the Program Suspend
Latency time (see Table 8 for value) and updates the Status Register bits. The Bank
Addresses of the Block being programmed must be specified in the Program Suspend
command.
After the program operation has been suspended, the system can read array data from any
address. However, data read from Program-Suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in Erase
Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time
Program area), the user must use the proper command sequences to enter and exit this
region.
The system may also issue the Auto Select command sequence when the device is in the
Program Suspend mode. The system can read as many Auto Select codes as required.
When the device exits the Auto Select mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See Auto Select command sequence for
more information.
4.1.9
Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. See Write Operation Status for more
information.
The system must write the Program Resume command, specifying the Bank addresses of
the Program-Suspended Block, to exit the Program Suspend mode and to continue the
programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
24/74
M29DW640F
4.1.10
Command interface
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final Write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 4.1.8: Program
Suspend command and Section 4.1.9: Program Resume command).
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
After programming has started, Bus Read operations in the Bank being programmed output
the Status Register content, while Bus Read operations to the other Bank output the
contents of the memory array. See the section on the Status Register for more details.
Typical program times are given in Table 8.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations to the Bank where the
command was issued will continue to output the Status Register. A Read/Reset command
must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.2
Fast Program commands
There are five Fast Program commands available to improve the programming throughput,
by writing several adjacent Words or Bytes in parallel.
When VPPH is applied to the VPP/Write Protect pin the memory automatically enters the Fast
Program mode. The user can then choose to issue any of the Fast Program commands.
Care must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect
any protected block. Fast programming should not be attempted when VPP is not at VPPH.
4.2.1
Double Word Program command
This is used to write two adjacent Words in x16 mode, in parallel. The addresses of the two
Words must differ only in A0.
Three bus write cycles are necessary to issue the command.
1.
The first bus cycle sets up the command.
2.
The second bus cycle latches the Address and the Data of the first Word to be written.
3.
The third bus cycle latches the Address and the Data of the second Word to be written
and starts the Program/Erase Controller.
25/74
Command interface
4.2.2
M29DW640F
Quadruple Word Program command
This is used to write a page of four adjacent Words, in x16 mode, in parallel. The addresses
of the four Words must differ only in A1 and A0.
Five bus write cycles are necessary to issue the command.
1.
4.2.3
The first bus cycle sets up the command.
2.
The second bus cycle latches the Address and the Data of the first Word to be written.
3.
The third bus cycle latches the Address and the Data of the second Word to be written.
4.
The fourth bus cycle latches the Address and the Data of the third Word to be written.
5.
The fifth bus cycle latches the Address and the Data of the fourth Word to be written
and starts the Program/Erase Controller.
Double Byte Program command
This is used to write two adjacent Bytes in x8 mode, in parallel. The addresses of the two
Bytes must differ only in DQ15A-1.
Three bus write cycles are necessary to issue the command.
4.2.4
1.
The first bus cycle sets up the command.
2.
The second bus cycle latches the Address and the Data of the first Byte to be written.
3.
The third bus cycle latches the Address and the Data of the second Byte to be written
and starts the Program/Erase Controller.
Quadruple Byte Program command
This is used to write four adjacent Bytes in x8 mode, in parallel. The addresses of the four
Bytes must differ only in A0, DQ15A-1.
Five bus write cycles are necessary to issue the command.
26/74
1.
The first bus cycle sets up the command.
2.
The second bus cycle latches the Address and the Data of the first Byte to be written.
3.
The third bus cycle latches the Address and the Data of the second Byte to be written.
4.
The fourth bus cycle latches the Address and the Data of the third Byte to be written.
5.
The fifth bus cycle latches the Address and the Data of the fourth Byte to be written and
starts the Program/Erase Controller.
M29DW640F
4.2.5
Command interface
Octuple Byte Program command
This is used to write eight adjacent Bytes, in x8 mode, in parallel. The addresses of the eight
Bytes must differ only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the command.
1.
The first bus cycle sets up the command.
2.
The second bus cycle latches the Address and the Data of the first Byte to be written.
3.
The third bus cycle latches the Address and the Data of the second Byte to be written.
4.
The fourth bus cycle latches the Address and the Data of the third Byte to be written.
5.
The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.
6.
The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.
7.
The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.
8.
The eighth bus cycle latches the Address and the Data of the seventh Byte to be
written.
9.
The ninth bus cycle latches the Address and the Data of the eighth Byte to be written
and starts the Program/Erase Controller.
Only one bank can be programmed at any one time. The other bank must be in Read mode
or Erase Suspend.
After programming has started, Bus Read operations in the Bank being programmed output
the Status Register content, while Bus Read operations to the other Bank output the
contents of the memory array.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively. (See Section 4.1.8: Program
Suspend command and Section 4.1.9: Program Resume command)
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations to the Bank where the
command was issued will continue to output the Status Register. A Read/Reset command
must be issued to reset the error condition and return to Read mode.
Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical Program times are given in Table 8: Program, Erase times and Program, Erase
Endurance cycles.
4.2.6
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode.
The Unlock Bypass Program command can then be issued to program addresses within the
bank, or the Unlock Bypass Reset command can be issued to return the bank to Read
mode. In Unlock Bypass mode the memory can be read as if in Read mode.
27/74
Command interface
M29DW640F
When VPP is applied to the VPP/Write Protect pin the memory automatically enters the
Unlock Bypass mode and the Unlock Bypass Program command can be issued
immediately.
4.2.7
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two Bus Write operations, the final write operation
latches the address and data in the internal state machine and starts the Program/Erase
Controller.
The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. The operation cannot be aborted, a
Bus Read operation to the Bank where the command was issued outputs the Status
Register. See the Program command for details on the behavior.
4.2.8
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
4.3
Block Protection commands
4.3.1
Enter Extended Block command
The M29DW640F has one extra 256-Byte block (Extended Block) that can only be accessed
using the Enter Extended Block command. Three Bus write cycles are required to issue the
Extended Block command. Once the command has been issued the device enters
Extended Block mode where all Bus Read or Program operations to the 000000h-00007Fh
(Word) or 000000h-0000FFh (Byte) addresses access the Extended Block. The Extended
Block cannot be erased, and can be treated as one-time programmable (OTP) memory. In
Extended Block mode only array cell locations (Bank A) with the same addresses as the
Extended Block (000000h-00007Fh (Word) or 000000h-0000FFh (Byte)) are not accessible.
In Extended Block mode dual operations are allowed and the Extended Block physically
belongs to Bank A.
When in Extended Block mode, Erase, Chip Erase, Erase Suspend and Erase resume
commands are not allowed.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Block can be protected, however once protected the protection cannot be
undone.
4.3.2
Exit Extended Block command
The Exit Extended Block command is used to exit from the Extended Block mode and return
the device to Read mode. Four Bus Write operations are required to issue the command.
28/74
M29DW640F
4.3.3
Command interface
Block Protect and Chip Unprotect commands
Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are
shown in Appendix A, Table 24: Block addresses. The whole chip can be unprotected to allow the data
inside the blocks to be changed.
Block Protect and Chip Unprotect operations are described in Appendix D.
Table 6.
Commands, 16-bit mode, BYTE = VIH
Command
Length
Bus Write operations(1)
1st
2nd
Add
Data
1
X
F0
3
555
Auto Select
3
Program
3rd
4th
Add
Data
Add
Data Add
AA
2AA
55
X
F0
555
AA
2AA
55
(BKA)
555
90
4
555
AA
2AA
55
555
A0
Double Word Program
3
555
50
PA0
PD0
PA1
PD1
Quadruple Word Program
3
555
56
PA0
PD0
PA1
PD1
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
Erase/Program Suspend
1
BKA
B0
Erase/Program Resume
1
BKA
30
Read CFI Query(2)
1
(BKA)
55
98
Enter Extended Block
3
555
AA
2AA
Exit Extended Block
4
555
AA
2AA
5th
Data
6th
Add
Data Add
Data
Read/Reset
PA
PD
PA2
PD2
PA3
PD3
80
555
AA
2AA
55
555
10
555
80
555
AA
2AA
55
BA
30
55
555
88
55
555
90
X
00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the
table are in hexadecimal.
2. Normally the Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands and A11-A21 are Don’t
Care, however for the Read CFI command A21-A14 must specify a bank address, and the subsequent read operations
must be addressed to the same bank.
29/74
Command interface
Table 7.
M29DW640F
Commands, 8-bit mode, BYTE = VIL
AAA A0
Double
Byte
Program
3
AAA
50 PA0 PD1 PA1 PD1
Quadruple
Byte
Program
5
AAA
56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Octuple
Byte
Program
5
AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7
Unlock
Bypass
3
AAA AA 555 55
Unlock
Bypass
Program
2
X
A0 PA PD
Unlock
Bypass
Reset
2
X
90
Chip Erase
6
PA PD
AAA
20
AAA AA 555 55
AAA
80 AAA AA 555
55 AAA 10
Block Erase 6+ AAA AA 555 55
AAA
80 AAA AA 555
55
00
Erase/
Program
Suspend
1
BKA B0
Erase/
Program
Resume
1
BKA
Read CFI
Query(2)
1
Enter
Extended
Block
3
AAA AA 555 55
AAA
88
Exit
Extended
Block
4
AAA AA 555 55
AAA
90
BA
30
30
(BKA)
98
AA
X
00
1.
X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
2.
Normally the Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands and A11-A21 are Don’t Care, however for
the Read CFI command A21-A14 must specify a bank address, and the subsequent read operations must be addressed to the same bank.
30/74
Data
AAA AA 555 55
Add
Data
4
Add
Program
X
Data
(BKA)
90
AAA
Add
AAA AA 555 55
Add
Auto Select 3
Add
Data
9th
F0
Add
Data
8th
X
Add
Data
7th
Data
6th
Add
5th
AAA AA 555 55
1
F0
4th
3
Read/Reset
X
3rd
Data
2nd
Data
1st
Add
Command
Length
Bus Write operations(1)
M29DW640F
Table 8.
Command interface
Program, Erase times and Program, Erase Endurance cycles
Parameter
Min
Typ(1)(2)
Chip Erase
80
Block Erase (64 KBytes)
0.8
Max(2)
400
Unit
(3)
s
6(4)
s
(4)
Erase Suspend latency time
50
Byte Program (1, 2, 4 or 8 at-a-time)
10
200(3)
µs
Word Program (1, 2 or 4 at-a-time)
10
200(3)
µs
Chip Program (Byte by Byte)
80
400(3)
s
40
200(3)
s
20
100(3)
s
10
50(3)
s
4
µs
Chip Program (Word by Word)
Chip Program (quadruple Byte or double Word)
Chip Program (octuple Byte or quadruple Word)
Program Suspend latency time
Program/Erase cycles (per Block)
Data Retention
µs
100,000
cycles
20
years
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC.
31/74
Status register
5
M29DW640F
Status register
The M29DW640F has one Status Register. The Status Register provides information on the
current or previous Program or Erase operations executed in each bank. The various bits
convey information and errors on the operation. Bus Read operations from any address
within the Bank, always read the Status Register during Program and Erase operations. It is
also read during Erase Suspend when an address within a block being erased is accessed.
The bits in the Status Register are summarized in Table 9: Status Register Bits.
5.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 6: Data Polling flowchart, gives an example of how to use the Data Polling Bit. A Valid
Address is the address being programmed or an address within the block being erased.
5.1.1
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 7: Toggle flowchart, gives an example of how to use the Data Toggle Bit. Figure 14
and Figure 15 describe Toggle Bit timing waveform.
32/74
M29DW640F
5.1.2
Status register
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
5.1.3
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.
5.1.4
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.
Figure 14 and Figure 15 describe Alternative Toggle Bit timing waveform.
33/74
Status register
Table 9.
M29DW640F
Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Bank address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Bank address
DQ7
Toggle
0
–
–
0
Program Error
Bank address
DQ7
Toggle
1
–
–
Hi-Z
Chip Erase
Any address
0
Toggle
0
1
Toggle
Hi-Z
Block Erase before
timeout
Erasing block
0
Toggle
0
0
Toggle
0
Non-Erasing block
0
Toggle
0
0
No Toggle
0
Erasing block
0
Toggle
0
1
Toggle
Hi-Z
Non-Erasing block
0
Toggle
0
1
No Toggle
0
Erasing block
1
No Toggle
0
–
Toggle
Hi-Z
Block Erase
Erase Suspend
Non-Erasing block
Data read as normal
Hi-Z
Good Block address
0
Toggle
1
1
No Toggle
0
Faulty Block address
0
Toggle
1
1
Toggle
0
Erase Error
1. Unspecified data bits should be ignored.
1. Figure 14 and Figure 15 describe Toggle and Alternative Toggle Bits timing waveforms.
Figure 6.
Data Polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5 = 1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
NO
FAIL
YES
PASS
AI07760
34/74
M29DW640F
Figure 7.
Status register
Toggle flowchart
START
READ DQ6
ADDRESS = BA
READ
DQ5 & DQ6
ADDRESS = BA
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
TWICE
ADDRESS = BA
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI08929b
1. BA = Address of Bank being Programmed or Erased.
35/74
Dual operations and multiple bank architecture
6
M29DW640F
Dual operations and multiple bank architecture
The Multiple Bank Architecture of the M29DW640F gives greater flexibility for software developers to split
the code and data spaces within the memory array. The Dual Operations feature simplifies the software
management of the device by allowing code to be executed from one bank while another bank is being
programmed or erased.
The Dual Operations feature means that while programming or erasing in one bank, read operations are
possible in another bank with zero latency.
Only one bank at a time is allowed to be in program or erase mode. However, certain commands can
cross bank boundaries, which means that during an operation only the banks that are not concerned with
the cross bank operation are available for dual operations. For example, if a Block Erase command is
issued to erase blocks in both Bank A and Bank B, then only Banks C or D are available for read
operations while the erase is being executed.
If a read operation is required in a bank, which is programming or erasing, the program or erase
operation can be suspended.
Also if the suspended operation was erase then a program command can be issued to another block, so
the device can have one block in Erase Suspend mode, one programming and other banks in read mode.
By using a combination of these features, read operations are possible at any moment in the device.
Table 10 and Table 11 show the dual operations possible in other banks and in the same bank. Note that
only the commonly used commands are represented in these tables.
Table 10.
Dual operations allowed in other banks
Commands allowed in another bank(1)
Status of bank(1)
Read
Array
Read
Status
Register(2)
Read
CFI
Query
Select
Idle
Yes
Yes(3)
Yes
Programming
Yes
No
Erasing
Yes
Program Suspended
Erase Suspended
Auto
Program/ Program/
Erase
Erase
Suspend Resume
Program
Erase
Yes
Yes
Yes
Yes(3)
Yes(4)
No
No
–
–
No
No
No
No
No
–
–
No
No
Yes
No
Yes
Yes
No
No
–
Yes(5)
Yes
No
Yes
Yes
Yes
No
–
Yes(6)
1. If several banks are involved in a program or erase operation, then only the banks that are not concerned with the operation
are available for dual operations.
2. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.
3. Only after a program or erase operation in that bank.
4. Only after a Program or Erase Suspend command in that bank.
5. Only a Program Resume is allowed if the bank was previously in Program Suspend mode.
6. Only an Erase Resume is allowed if the bank was previously in Erase Suspend mode.
36/74
M29DW640F
Table 11.
Dual operations and multiple bank architecture
Dual operations allowed in same bank
Commands allowed in same bank
Read
Array
Read Status
Register(1)
Read
CFI
Query
Select
Idle
Yes
Yes
Yes
Programming
No
Yes
Erasing
No
Program
Suspended
Erase Suspended
Status of bank
Auto
Program/ Program/
Erase
Erase
Suspend Resume
Program
Erase
Yes
Yes
Yes
Yes(2)
Yes(3)
No
No
–
–
Yes(4)
–
Yes
No
No
–
No
Yes(5)
–
Yes(6)
No
Yes
Yes
No
–
–
Yes
Yes(6)
Yes(7)
Yes
Yes
Yes(6)
No
–
Yes
1. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.
2. Only after a program or erase operation in that bank.
3. Only after a Program or Erase Suspend command in that bank.
4. Only a Program Suspend.
5. Only an Erase suspend.
6. Not allowed in the Block or Word that is being erased or programmed.
7. The Status Register can be read by addressing the block being erase suspended.
37/74
Maximum ratings
7
M29DW640F
Maximum ratings
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the Numonyx SURE
Program and other relevant quality documents.
Table 12.
Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature Under Bias
–50
125
°C
TSTG
Storage Temperature
–65
150
°C
–0.6
VCC +0.6
V
(1)(2)
VIO
Input or Output voltage
VCC
Supply voltage
–0.6
4
V
VID
Identification voltage
–0.6
13.5
V
Program voltage
–0.6
13.5
V
VPP(3)
1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
3. VPP must not remain at 12V for more than a total of 80hrs.
38/74
M29DW640F
8
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 13: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 13.
Operating and AC measurement conditions
M29DW640F
Parameter
60
70
Unit
Min
Max
Min
Max
VCC Supply voltage
2.7
3.6
2.7
3.6
V
Ambient Operating Temperature
–40
85
–40
85
°C
Load capacitance (CL)
30
Input Rise and Fall times
10
Input pulse voltages
pF
10
ns
0 to VCC
0 to VCC
V
VCC/2
VCC/2
V
Input and Output Timing Ref. voltages
Figure 8.
30
AC measurement I/O waveform
VCC
VCC/2
0V
AI05557
39/74
DC and AC parameters
Figure 9.
M29DW640F
AC measurement Load Circuit
VPP
VCC
VCC
25kΩ
DEVICE
UNDER
TEST
CL
0.1µF
25kΩ
0.1µF
CL includes JIG capacitance
AI05558
Table 14.
Symbol
CIN
COUT
Device capacitance(1)
Parameter
Input capacitance
Output capacitance
1. Sampled only, not 100% tested.
40/74
Test condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
M29DW640F
Table 15.
Symbol
DC and AC parameters
DC characteristics
Parameter
Test condition
Min
Max
Unit
0V ≤VIN ≤VCC
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤VOUT ≤VCC
±1
µA
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
10
mA
Supply Current (Standby)
E = VCC ±0.2V,
RP = VCC ±0.2V
100
µA
VPP/WP =
VIL or VIH
20
mA
VPP/WP = VPP
20
mA
ICC1(1)
ICC2
ICC3
(1)(2)
Supply Current
(Program/Erase)
Program/Erase
Controller active
VIL
Input Low voltage
–0.5
0.8
V
VIH
Input High voltage
0.7VCC
VCC +0.3
V
VPP
Voltage for VPP/WP Program
Acceleration
VCC = 2.7V ±10%
11.5
12.5
V
IPP
Current for VPP/WP Program
Acceleration
VCC =2.7V ±10%
15
mA
VOL
Output Low voltage
IOL = 1.8mA
0.45
V
VOH
Output High voltage
IOH = –100µA
VID
Identification voltage
11.5
12.5
V
Program/Erase Lockout supply
voltage
1.8
2.3
V
VLKO
VCC –0.4
V
1. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).
2. Sampled only, not 100% tested.
41/74
DC and AC parameters
M29DW640F
Figure 10. Random Read AC waveforms
tAVAV
A0-A21/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGLQV
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI05559
42/74
BYTE
DQ0-DQ15
G
E
A0-A2
A3-A21
A-1
tELBL/tELBH
tBHQV
tELQV
tAVQV
VALID
VALID
tGLQV
VALID
tAVQV1
VALID
VALID
VALID
VALID
VALID
VALID
tBLQZ
VALID
VALID
VALID
VALID
VALID
VALID
tGHQZ
tGHQX
tEHQZ
VALID
VALID
tEHQX
AI11309
M29DW640F
DC and AC parameters
Figure 11. Page Read AC waveforms
43/74
DC and AC parameters
Table 16.
M29DW640F
Read AC characteristics
M29DW640F
Symbol
Alt
Parameter
Test condition
Unit
60
70
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
60
70
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
60
70
ns
tAVQV1
tPAGE
Address Valid to Output Valid (Page)
E = VIL,
G = VIL
Max
25
25
ns
tBLQZ
tFLQZ
BYTE Low to Output Hi-Z
Max
25
25
ns
tBHQV
tFHQV
BYTE High to Output valid
Max
30
30
ns
tELQX(1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tEHQZ(1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
25
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
60
70
ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
5
5
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output Transition
Min
0
0
ns
tGLQX(1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
Min
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
25
25
ns
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
25
25
ns
tGHQZ
(1)
1. Sampled only, not 100% tested.
44/74
M29DW640F
DC and AC parameters
Figure 12. Write AC waveforms, Write Enable controlled
tAVAV
A0-A21/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI05560
45/74
DC and AC parameters
Table 17.
M29DW640F
Write AC characteristics, Write Enable controlled
M29DW640F
Symbol
Alt
Parameter
Unit
60
70
tAVAV
tWC
Address Valid to Next Address Valid
Min
60
70
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
45
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
Output Enable High to Write Enable Low
Min
0
0
ns
tGHWL
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
µs
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
45
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
45
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
ns
tWHRL(1)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
ns
1. Sampled only, not 100% tested.
46/74
M29DW640F
DC and AC parameters
Figure 13. Write AC waveforms, Chip Enable controlled
tAVAV
A0-A21/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI05561
47/74
DC and AC parameters
Table 18.
M29DW640F
Write AC characteristics, Chip Enable controlled
M29DW640F
Symbol
Alt
Parameter
Unit
60
70
tAVAV
tWC
Address Valid to Next Address Valid
Min
60
70
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
45
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
45
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
45
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
ns
tBUSY
Program/Erase Valid to RB Low
Max
30
30
ns
Output Enable High Chip Enable Low
Min
0
0
ns
tEHRL
(1)
tGHEL
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
µs
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
ns
1. Sampled only, not 100% tested.
48/74
M29DW640F
DC and AC parameters
Figure 14. Toggle and Alternative Toggle Bits mechanism, Chip Enable controlled
Address Outside the Bank
Being Programmed or Erased
A0-A21
A-1
Address in the Bank
Being Programmed or Erased
Address Outside the Bank
Being Programmed or Erased
tAXEL
E
G
tELQV
tELQV
DQ2(1)/DQ6(2)
Data
Read Operation outside the Bank
Being Programmed or Erased
Toggle/
Alternative Toggle Bit
Toggle/
Alternative Toggle Bit
Read Operation in the Bank
Being Programmed or Erased
Data
Read Operation Outside the Bank
Being Programmed or Erased
AI08914d
1. The Toggle Bit is output on DQ6.
2. The Alternative Toggle Bit is output on DQ2.
3. Refer to Table 16: Read AC characteristics for tELQV value.
Figure 15. Toggle and Alternative Toggle Bits mechanism, Output Enable controlled
Address Outside the Bank
Being Programmed or Erased
A0-A21
A-1
Address in the Bank
Being Programmed or Erased
Address Outside the Bank
Being Programmed or Erased
tAXGL
G
E
tGLQV
tGLQV
DQ2(1)/DQ6(2)
Data
Read Operation outside the Bank
Being Programmed or Erased
Toggle/
Alternative Toggle Bit
Toggle/
Alternative Toggle Bit
Read Operation in the Bank
Being Programmed or Erased
Data
Read Operation Outside the Bank
Being Programmed or Erased
AI08915d
1. The Toggle Bit is output on DQ6.
4. The Alternative Toggle Bit is output on DQ2.
5. Refer to Table 16: Read AC characteristics for tGLQV value.
49/74
DC and AC parameters
Table 19.
M29DW640F
Toggle and Alternative Toggle Bits AC characteristics
Symbol
Alt
Parameter
Unit
60
70
tAXEL
Address Transition to Chip Enable Low
Min
10
10
ns
tAXGL
Address Transition to Output Enable Low
Min
10
10
ns
Figure 16. Reset/Block Temporary Unprotect AC waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Figure 17. Accelerated Program Timing waveforms
VPP
VPP/WP
VIL or VIH
tVHVPP
tVHVPP
AI05563
50/74
M29DW640F
Table 20.
DC and AC parameters
Reset/Block Temporary Unprotect AC characteristics
M29DW640F
Symbol
Alt
Parameter
Unit
60
70
tPHWL(1)
tPHEL
tPHGL(1)
tRH
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
50
50
ns
tRHWL(1)
tRHEL(1)
tRHGL(1)
tRB
RB High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
ns
tPLYH
tREADY
RP Low to Read Mode
Max
20
20
µs
tPHPHH(1)
tVIDR
RP Rise Time to VID
Min
500
500
ns
VPP Rise and Fall Time
Min
250
250
ns
tVHVPP(1)
1. Sampled only, not 100% tested.
51/74
Package mechanical
9
M29DW640F
Package mechanical
Figure 18. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
1. Drawing is not to scale.
Table 21.
TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
0.080
0.0031
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3°
0°
5°
52/74
0.0315
0°
5°
3°
M29DW640F
Package mechanical
Figure 19. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z32
1. Drawing is not to scale.
Table 22.
TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.0472
0.260
A2
0.0102
0.900
b
Max
0.350
0.450
0.0354
0.0138
0.0177
D
6.000
5.900
6.100
0.2362
0.2323
0.2402
D1
4.000
–
–
0.1575
–
–
ddd
0.100
0.0039
E
8.000
7.900
8.100
0.3150
0.3110
0.3189
E1
5.600
–
–
0.2205
–
–
e
0.800
–
–
0.0315
–
–
FD
1.000
–
–
0.0394
–
–
FE
1.200
–
–
0.0472
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
53/74
Part numbering
10
Part numbering
Table 23.
Ordering information scheme
Example:
M29DW640F
M29DW640F
70
N
1
T
Device Type
M29
Architecture
D = Dual or Multiple Bank
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
640F = 64 Mbit (x8/x16), Boot Block, 8+24+24+8 partitioning, 0.13µm technology
Speed
60 = 60ns
70 = 70ns
Package
N = TSOP48: 12 x 20 mm
ZE = TFBGA48 6 x 8mm, 0.8 mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
Note:
This product is also available with the Extended Block factory locked. For further details and
ordering information contact your nearest Numonyx sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
54/74
M29DW640F
Block addresses
Appendix A
Bank A
Bank
Table 24.
Block addresses
Block addresses
Block
(KBytes/
KWords)
Protection Block
Group
(x8)
(x16)
0
8/4
Protection Group
000000h-001FFFh(1)
000000h–000FFFh(1)
1
8/4
Protection Group
002000h-003FFFh(1)
001000h–001FFFh(1)
2
8/4
Protection Group
004000h-005FFFh(1)
002000h–002FFFh(1)
3
8/4
Protection Group
006000h-007FFFh(1)
003000h–003FFFh(1)
4
8/4
Protection Group
008000h-009FFFh(1)
004000h–004FFFh(1)
5
8/4
Protection Group
00A000h-00BFFFh(1)
005000h–005FFFh(1)
6
8/4
Protection Group
00C000h-00DFFFh(1)
006000h–006FFFh(1)
7
8/4
Protection Group
00E000h-00FFFFh(1)
007000h–007FFFh(1)
8
64/32
010000h-01FFFFh
008000h–00FFFFh
9
64/32
020000h-02FFFFh
010000h–017FFFh
10
64/32
030000h-03FFFFh
018000h–01FFFFh
11
64/32
040000h-04FFFFh
020000h–027FFFh
12
64/32
050000h-05FFFFh
028000h–02FFFFh
Protection Group
Protection Group
13
64/32
060000h-06FFFFh
030000h–037FFFh
14
64/32
070000h-07FFFFh
038000h–03FFFFh
15
64/32
080000h-08FFFFh
040000h–047FFFh
16
64/32
090000h-09FFFFh
048000h–04FFFFh
Protection Group
17
64/32
0A0000h-0AFFFFh
050000h–057FFFh
18
64/32
0B0000h-0BFFFFh
058000h–05FFFFh
19
64/32
0C0000h-0CFFFFh
060000h–067FFFh
20
64/32
0D0000h-0DFFFFh
068000h–06FFFFh
Protection Group
21
64/32
0E0000h-0EFFFFh
070000h–077FFFh
22
64/32
0F0000h-0FFFFFh
078000h–07FFFFh
55/74
Block addresses
Bank
Table 24.
M29DW640F
Block addresses (continued)
Block
(KBytes/
KWords)
23
64/32
24
64/32
Protection Block
Group
(x8)
(x16)
100000h-10FFFFh
080000h–087FFFh
110000h-11FFFFh
088000h–08FFFFh
Protection Group
25
64/32
120000h-12FFFFh
090000h–097FFFh
26
64/32
130000h-13FFFFh
098000h–09FFFFh
27
64/32
140000h-14FFFFh
0A0000h–0A7FFFh
28
64/32
150000h-15FFFFh
0A8000h–0AFFFFh
Protection Group
29
64/32
160000h-16FFFFh
0B0000h–0B7FFFh
30
64/32
170000h-17FFFFh
0B8000h–0BFFFFh
31
64/32
180000h-18FFFFh
0C0000h–0C7FFFh
32
64/32
190000h-19FFFFh
0C8000h–0CFFFFh
Protection Group
33
64/32
1A0000h-1AFFFFh
0D0000h–0D7FFFh
34
64/32
1B0000h-1BFFFFh
0D8000h–0DFFFFh
35
64/32
1C0000h-1CFFFFh
0E0000h–0E7FFFh
36
64/32
1D0000h-1DFFFFh
0E8000h–0EFFFFh
Bank B
Protection Group
37
64/32
1E0000h-1EFFFFh
0F0000h–0F7FFFh
38
64/32
1F0000h-1FFFFFh
0F8000h–0FFFFFh
39
64/32
200000h-20FFFFh
100000h–107FFFh
40
64/32
210000h-21FFFFh
108000h–10FFFFh
Protection Group
41
64/32
220000h-22FFFFh
110000h–117FFFh
42
64/32
230000h-23FFFFh
118000h–11FFFFh
43
64/32
240000h-24FFFFh
120000h–127FFFh
44
64/32
250000h-25FFFFh
128000h–12FFFFh
Protection Group
45
64/32
260000h-26FFFFh
130000h–137FFFh
46
64/32
270000h-27FFFFh
138000h–13FFFFh
47
64/32
280000h-28FFFFh
140000h–147FFFh
48
64/32
290000h-29FFFFh
148000h–14FFFFh
Protection Group
49
64/32
2A0000h-2AFFFFh
150000h–157FFFh
50
64/32
2B0000h-2BFFFFh
158000h–15FFFFh
51
64/32
2C0000h-2CFFFFh
160000h–167FFFh
52
64/32
2D0000h-2DFFFFh
168000h–16FFFFh
Protection Group
56/74
53
64/32
2E0000h-2EFFFFh
170000h–177FFFh
54
64/32
2F0000h-2FFFFFh
178000h–17FFFFh
M29DW640F
Bank
Table 24.
Block addresses
Block addresses (continued)
Block
(KBytes/
KWords)
55
64/32
56
64/32
Protection Block
Group
(x8)
(x16)
300000h-30FFFFh
180000h–187FFFh
310000h-31FFFFh
188000h–18FFFFh
Protection Group
57
64/32
320000h-32FFFFh
190000h–197FFFh
58
64/32
330000h-33FFFFh
198000h–19FFFFh
59
64/32
340000h-34FFFFh
1A0000h–1A7FFFh
60
64/32
350000h-35FFFFh
1A8000h–1AFFFFh
Bank B
Protection Group
61
64/32
360000h-36FFFFh
1B0000h–1B7FFFh
62
64/32
370000h-37FFFFh
1B8000h–1BFFFFh
63
64/32
380000h-38FFFFh
1C0000h–1C7FFFh
64
64/32
390000h-39FFFFh
1C8000h–1CFFFFh
Protection Group
65
64/32
3A0000h-3AFFFFh
1D0000h–1D7FFFh
66
64/32
3B0000h-3BFFFFh
1D8000h–1DFFFFh
67
64/32
3C0000h-3CFFFFh
1E0000h–1E7FFFh
68
64/32
3D0000h-3DFFFFh
1E8000h–1EFFFFh
Protection Group
69
64/32
3E0000h-3EFFFFh
1F0000h–1F7FFFh
70
64/32
3F0000h-3FFFFFh
1F8000h–1FFFFFh
71
64/32
400000h–40FFFFh
200000h–207FFFh
72
64/32
410000h–41FFFFh
208000h–20FFFFh
Protection Group
73
64/32
420000h–42FFFFh
210000h–217FFFh
74
64/32
430000h–43FFFFh
218000h–21FFFFh
75
64/32
440000h–44FFFFh
220000h–227FFFh
76
64/32
450000h–45FFFFh
228000h–22FFFFh
Bank C
Protection Group
77
64/32
460000h–46FFFFh
230000h–237FFFh
78
64/32
470000h–47FFFFh
238000h–23FFFFh
79
64/32
480000h–48FFFFh
240000h–247FFFh
80
64/32
490000h–49FFFFh
248000h–24FFFFh
Protection Group
81
64/32
4A0000h–4AFFFFh
250000h–257FFFh
82
64/32
4B0000h–4BFFFFh
258000h–25FFFFh
83
64/32
4C0000h–4CFFFFh
260000h–267FFFh
84
64/32
4D0000h–4DFFFFh
268000h–26FFFFh
Protection Group
85
64/32
4E0000h–4EFFFFh
270000h–277FFFh
86
64/32
4F0000h–4FFFFFh
278000h–27FFFFh
57/74
Block addresses
Bank
Table 24.
M29DW640F
Block addresses (continued)
Block
(KBytes/
KWords)
87
64/32
88
64/32
Protection Block
Group
(x8)
(x16)
500000h–50FFFFh
280000h–287FFFh
510000h–51FFFFh
288000h–28FFFFh
Protection Group
89
64/32
520000h–52FFFFh
290000h–297FFFh
90
64/32
530000h–53FFFFh
298000h–29FFFFh
91
64/32
540000h–54FFFFh
2A0000h–2A7FFFh
92
64/32
550000h–55FFFFh
2A8000h–2AFFFFh
Protection Group
93
64/32
560000h–56FFFFh
2B0000h–2B7FFFh
94
64/32
570000h–57FFFFh
2B8000h–2BFFFFh
95
64/32
580000h–58FFFFh
2C0000h–2C7FFFh
96
64/32
590000h–59FFFFh
2C8000h–2CFFFFh
Protection Group
97
64/32
5A0000h–5AFFFFh
2D0000h–2D7FFFh
98
64/32
5B0000h–5BFFFFh
2D8000h–2DFFFFh
99
64/32
5C0000h–5CFFFFh
2E0000h–2E7FFFh
100
64/32
5D0000h–5DFFFFh
2E8000h–2EFFFFh
Bank C
Protection Group
101
64/32
5E0000h–5EFFFFh
2F0000h–2F7FFFh
102
64/32
5F0000h–5FFFFFh
2F8000h–2FFFFFh
103
64/32
600000h–60FFFFh
300000h–307FFFh
104
64/32
610000h–61FFFFh
308000h–30FFFFh
Protection Group
105
64/32
620000h–62FFFFh
310000h–317FFFh
106
64/32
630000h–63FFFFh
318000h–31FFFFh
107
64/32
640000h–64FFFFh
320000h–327FFFh
108
64/32
650000h–65FFFFh
328000h–32FFFFh
Protection Group
109
64/32
660000h–66FFFFh
330000h–337FFFh
110
64/32
670000h–67FFFFh
338000h–33FFFFh
111
64/32
680000h–68FFFFh
340000h–347FFFh
112
64/32
690000h–69FFFFh
348000h–34FFFFh
Protection Group
113
64/32
6A0000h–6AFFFFh
350000h–357FFFh
114
64/32
6B0000h–6BFFFFh
358000h–35FFFFh
115
64/32
6C0000h–6CFFFFh
360000h–367FFFh
116
64/32
6D0000h–6DFFFFh
368000h–36FFFFh
Protection Group
58/74
117
64/32
6E0000h–6EFFFFh
370000h–377FFFh
118
64/32
6F0000h–6FFFFFh
378000h–37FFFFh
M29DW640F
Bank
Table 24.
Block addresses
Block addresses (continued)
Block
(KBytes/
KWords)
119
64/32
120
64/32
Protection Block
Group
(x8)
(x16)
700000h–70FFFFh
380000h–387FFFh
710000h–71FFFFh
388000h–38FFFFh
Protection Group
121
64/32
720000h–72FFFFh
390000h–397FFFh
122
64/32
730000h–73FFFFh
398000h–39FFFFh
123
64/32
740000h–74FFFFh
3A0000h–3A7FFFh
124
64/32
750000h–75FFFFh
3A8000h–3AFFFFh
Protection Group
125
64/32
760000h–76FFFFh
3B0000h–3B7FFFh
126
64/32
770000h–77FFFFh
3B8000h–3BFFFFh
127
64/32
780000h–78FFFFh
3C0000h–3C7FFFh
128
64/32
790000h–79FFFFh
3C8000h–3CFFFFh
Bank D
Protection Group
129
64/32
7A0000h–7AFFFFh
3D0000h–3D7FFFh
130
64/32
7B0000h–7BFFFFh
3D8000h–3DFFFFh
131
64/32
7C0000h–7CFFFFh
3E0000h–3E7FFFh
132
64/32
7D0000h–7DFFFFh
3E8000h–3EFFFFh
133
64/32
7E0000h–7EFFFFh
3F0000h–3F7FFFh
134
8/4
Protection Group
7F0000h–7F1FFFh
3F8000h–3F8FFFh
135
8/4
Protection Group
7F2000h–7F3FFFh
3F9000h–3F9FFFh
136
8/4
Protection Group
7F4000h–7F5FFFh
3FA000h–3FAFFFh
137
8/4
Protection Group
7F6000h–7F7FFFh
3FB000h–3FBFFFh
138
8/4
Protection Group
7F8000h–7F9FFFh
3FC000h–3FCFFFh
139
8/4
Protection Group
7FA000h–7FBFFFh
3FD000h–3FDFFFh
140
8/4
Protection Group
7FC000h–7FDFFFh
3FE000h–3FEFFFh
141
8/4
Protection Group
7FE000h–7FFFFFh
3FF000h–3FFFFFh
Protection Group
1. Used as Extended Block addresses in Extended Block mode.
59/74
Common Flash Interface (CFI)
Appendix B
M29DW640F
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from
the Flash memory device. It allows a system software to query the device to determine various electrical
and timing parameters, density information and functions supported by the memory. The system can
interface easily with the device, enabling the software to upgrade itself when necessary.
When the Read CFI Query command is issued the addressed bank enters Read CFI Query mode and
read operations in the same bank (A21-A19) output the CFI data. Table 25, Table 26, Table 27, Table 28,
Table 29 and Table 30 show the addresses (A-1, A0-A10) used to retrieve the data.
The CFI data structure also contains a security area where a 64 bit unique security number is written
(see Table 30: Security Code Area). This area can be accessed only in Read mode by the final user. It is
impossible to change the security number after it has been written by Numonyx.
Table 25.
Query structure overview
Address
Sub-section name
Description
x16
x8
10h
20h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
36h
System Interface Information
Device timing & voltage information
27h
4Eh
Device Geometry Definition
Flash device layout
40h
80h
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
61h
C2h
Security Code Area
64 bit unique device number
1. Query data are always presented on the lowest order data outputs.
Table 26.
CFI Query Identification String
Address
Data
x16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
19h
32h
0000h
1Ah
34h
0000h
Description
“Q”
Query Unique ASCII String "QRY"
"R"
"Y"
AMD
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
Compatible
Address for Primary Algorithm extended Query table (see Table 29)
P = 40h
Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported
NA
Address for Alternate Algorithm extended Query table
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
60/74
Value
M29DW640F
Table 27.
Common Flash Interface (CFI)
CFI Query System Interface Information
Address
Data
Description
Value
x16
x8
1Bh
36h
0027h
VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV
2.7V
1Ch
38h
0036h
VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV
3.6V
1Dh
3Ah
00B5h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5V
12.5V
16µs
1Eh
3Ch
00C5h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
1Fh
3Eh
0004h
Typical timeout per single Byte/Word program = 2n µs
20h
40h
0000h
Typical timeout for minimum size write buffer program =
21h
42h
000Ah
Typical timeout per individual block erase = 2n ms
22h
23h
44h
46h
0000h
0004h
Typical timeout for full Chip Erase =
2n
2n
µs
ms
NA
Maximum timeout for Byte/Word program =
times typical
256 µs
2n
times typical
NA
48h
0000h
Maximum timeout for write buffer program =
25h
4Ah
0003h
Maximum timeout per individual block erase = 2n times typical
4Ch
0000h
1s
2n
24h
26h
NA
Maximum timeout for Chip Erase =
2n
times typical
8s
NA
61/74
Common Flash Interface (CFI)
Table 28.
M29DW640F
Device Geometry Definition
Address
Data
Description
Value
x16
x8
27h
4Eh
0017h
Device Size = 2n in number of Bytes
28h
29h
50h
52h
0002h
0000h
Flash Device Interface Code description
2Ah
2Bh
54h
56h
0003h
0000h
Maximum number of Bytes in multi-Byte program or page = 2n
8
2Ch
58h
0003h
Number of Erase Block Regions(1). It specifies the number of
regions containing contiguous Erase Blocks of the same size.
3
2Dh
2Eh
5Ah
5Ch
0007h
0000h
Erase Block Region 1 Information
Number of Erase Blocks of identical size = 0007h+1
8
2Fh
30h
5Eh
60h
0020h
0000h
Erase Block Region 1 Information
Block size in Region 1 = 0020h * 256 Byte
31h
32h
62h
64h
007Dh
0000h
Erase Block Region 2 Information
Number of Erase Blocks of identical size = 007Dh+1
33h
34h
66h
68h
0000h
0001h
Erase Block Region 2 Information
Block size in Region 2 = 0100h * 256 Byte
35h
36h
6Ah
6Ch
0007h
0000h
Erase Block Region 3 information
Number of Erase Blocks of identical size = 0007h + 1
37h
38h
6Eh
70h
0020h
0000h
Erase Block Region 3 information
Block size in region 3 = 0020h * 256 Bytes
8 MBytes
x8, x16
Async.
8 KBytes
126
64 KBytes
8
8 KBytes
1. Erase Block Region 1 corresponds to addresses 000000h to 007FFFh; Erase block Region 2 corresponds to addresses
008000h to 3F7FFFh and Erase Block Region 3 corresponds to addresses 3F8000h to 3FFFFFh.
62/74
M29DW640F
Table 29.
Common Flash Interface (CFI)
Primary Algorithm-specific Extended Query table
Address
Data
Description
Value
x16
x8
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
"1"
44h
88h
0033h
Minor version number, ASCII
"3"
Yes
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
45h
8Ah
0000h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
46h
8Ch
0002h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
47h
8Eh
0001h
Block Protection
00 = not supported, x = number of sectors in per group
1
48h
90h
0001h
Temporary Block Unprotect
00 = not supported, 01 = supported
49h
92h
0005h
Block Protect /Unprotect
04 = M29W400B
05=
4Ah
94h
0077h
Simultaneous Operations,
x = number of blocks (excluding Bank A)
119
4Bh
96h
0000h
Burst Mode, 00 = not supported, 01 = supported
No
4Ch
98h
0002h
Page Mode, 00 = not supported, 01 = 4 page Word, 02 = 8 page
Word
Yes
4Dh
9Ah
00B5h
VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5V
4Eh
9Ch
00C5h
VPP Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5V
T/B
Yes
4Fh
9Eh
0001h
Top/Bottom Boot Block Flag
00h = uniform device
01h = 8 x8 KByte Blocks, Top and Bottom Boot with Write Protect
02h = Bottom boot device
03h = Top Boot Device
04h = Both Top and Bottom
50h
A0h
0001h
Program Suspend, 00 = not supported, 01 = supported
57h
AEh
0004h
Bank Organization, 00 = data at 4Ah is zero
X = number of banks
Yes
5
4
63/74
Common Flash Interface (CFI)
Table 29.
M29DW640F
Primary Algorithm-specific Extended Query table
Address
Data
Description
Value
x16
x8
58h
B0h
0017h
Bank A information
X = number of blocks in Bank A
23
59h
B2h
0030h
Bank B information
X = number of blocks in Bank B
48
5Ah
B4h
0030h
Bank C information
X = number of blocks in Bank C
48
5Bh
B6h
0017h
Bank D information
X = number of blocks in Bank D
23
Table 30.
Security Code Area
Address
Data
x16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Description
64 bit: unique device number
64/74
M29DW640F
Extended Memory Block
Appendix C
Extended Memory Block
The has an extra block, the Extended Block, that can be accessed using a dedicated
command.
This Extended Block is 128 Words in x16 mode and 256 Bytes in x8 mode. It is used as a
security block (to provide a permanent security identification number) or to store additional
information.
The Extended Block is either Factory Locked or Customer Lockable, its status is indicated
by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be
changed. When set to ‘1’, it indicates that the device is factory locked and the Extended
Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the
Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is
another security feature which ensures that a customer lockable device cannot be used
instead of a factory locked one.
Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific
procedure must be followed to read it. See “Extended Block Indicator Bit” in Table 4: Bus
operations, BYTE = VIL and Table 5: Bus operations, BYTE = VIH, respectively, for details of
how to read bit DQ7.
The Extended Block can only be accessed when the device is in Extended Block mode. For
details of how the Extended Block mode is entered and exited, refer to Section 4.3: Block
Protection commands and Section 4.3.2: Exit Extended Block command, and to Table 6:
Commands, 16-bit mode, BYTE = VIH and Table 7: Commands, 8-bit mode, BYTE = VIL,
respectively.
C.1
Factory Locked Extended Block
In devices where the Extended Block is factory locked, the Security Identification Number is
written to the Extended Block address space (see Table 31: Extended Block address and
data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.
C.2
Customer Lockable Extended Block
A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to
‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the
Extended Block but care must be taken because the protection of the Extended Block is not
reversible.
There are two ways of protecting the Extended Block:
●
Issue the Enter Extended Block command to place the device in Extended Block mode,
then use the In-System Technique with RP either at VIH or at VID (refer to Appendix D,
Figure 22: In-System Equipment Group Protect flowchart and Figure 23: In-System
Equipment Chip Unprotect flowchart, for a detailed explanation of the technique).
●
Issue the Enter Extended Block command to place the device in Extended Block mode,
then use the Programmer Technique (refer to Appendix D, Figure 20: Programmer
Equipment Group Protect flowchart and Figure 21: Programmer Equipment Chip
Unprotect flowchart, for a detailed explanation of the technique).
65/74
Extended Memory Block
M29DW640F
Once the Extended Block is programmed and protected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return the device to Read mode.
Table 31.
Extended Block address and data
Address(1)
Data
Device
x8
x16
Factory Locked
000000h-00000Fh
000000h-000007h
000010h-00007Fh
000008h-00003Fh
Random Number Security Identification
Number
ESN(2)
000080h-0000FFh
000040h-00007Fh
Unavailable
1. See Table 24: Block addresses.
2. ENS = Electronic Serial Number.
66/74
Customer
Lockable
Determined
by Customer
M29DW640F
Appendix D
Block protection
Block protection
Block protection can be used to prevent any operation from modifying the data stored in the
memory. The blocks are protected in groups, refer to Appendix A, Table 24 for details of the
Protection Groups. Once protected, Program and Erase operations within the protected
group fail to change the data.
There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is
described in the Signal Descriptions section.
To protect the Extended Block issue the Enter Extended Block command and then use
either the Programmer or In-System technique. Once protected issue the Exit Extended
Block command to return to read mode. The Extended Block protection is irreversible, once
protected the protection cannot be undone.
D.1
Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Programming Equipment.
To protect a group of blocks follow the flowchart in Figure 20: Programmer Equipment Group
Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all groups can be unprotected at the same time. To unprotect the chip follow Figure 21:
Programmer Equipment Chip Unprotect flowchart. Table 32: Programmer technique bus
operations, BYTE = VIH or VIL, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
D.2
In-System technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP (1). This can be achieved without violating the maximum ratings of the
components on the microprocessor bus, therefore this technique is suitable for use after the
memory has been fitted to the system.
To protect a group of blocks follow the flowchart in Figure 22: In-System Equipment Group
Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all the groups can be unprotected at the same time. To unprotect the chip follow
Figure 23: In-System Equipment Chip Unprotect flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.
67/74
Block protection
M29DW640F
Note:
RP can be either at VIH or at VID when using the In-System Technique to protect the
Extended Block.
Table 32.
Programmer technique bus operations, BYTE = VIH or VIL
E
G
W
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block (Group)
Protect(1)
VIL
VID
VIL Pulse
A9 = VID, A12-A21 Block Address
Others = X
X
Chip Unprotect
VID
VID
VIL Pulse
A9 = VID, A12 = VIH, A15 = VIH
Others = X
X
VIH
A0 = VIL, A1 = VIH, A2 = VIL, A3 = VIL,
A6 = VIL, A9 = VID,
A12-A21 Block address
Others = X
Pass = xx01h
Retry = xx00h.
VIH
A0 = VIL, A1 = VIH, A2 = VIL, A3 = VIL,
A6 = VIH, A9 = VID,
A12-A21 Block address
Others = X
Pass = xx00h
Retry = xx01h.
Operation
Block (Group)
Protect Verify
Block (Group)
Unprotect Verify
VIL
VIL
VIL
VIL
1. Block Protection Groups are shown in Appendix D, Table 24.
68/74
M29DW640F
Block protection
Figure 20. Programmer Equipment Group Protect flowchart
START
Set-up
ADDRESS =
GROUP ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Wait 4µs
Protect
W = VIL
Wait 100µs
W = VIH
E, G = VIH, A1 = VIH
A0, A2, A3, A6 = VIL
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA = 01h
NO
End
YES
++n
= 25
NO
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
PASS
FAIL
AI07756
1. Block Protection Groups are shown in Appendix D, Table 24.
69/74
Block protection
M29DW640F
Figure 21. Programmer Equipment Chip Unprotect flowchart
START
Set-up
PROTECT ALL
GROUPS
n=0
CURRENT GROUP = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Wait 4µs
Unprotect
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT
GROUP ADDRESS
A0, A2, A3 = VIL
A1, A6 = VIH
E = VIL
Wait 4µs
INCREMENT
CURRENT GROUP
Verify
G = VIL
Wait 60ns
Read DATA
NO
NO
DATA = 00h
++n
= 1000
YES
LAST
GROUP
End
YES
A9 = VIH
E, G = VIH
FAIL
NO
YES
A9 = VIH
E, G = VIH
PASS
AI07757
1. Block Protection Groups are shown in Appendix D, Table 24.
70/74
M29DW640F
Block protection
Figure 22. In-System Equipment Group Protect flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
Wait 100µs
Verify
WRITE 40h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
DATA = 01h
NO
YES
End
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI07758
1. Block Protection Groups are shown in Appendix D, Table 24.
2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.
71/74
Block protection
M29DW640F
Figure 23. In-System Equipment Chip Unprotect flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3, A6 = VIL, A1 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3 = VIL, A1, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS =
CURRENT GROUP ADDRESS
A0, A2, A3 = VIL, A1, A6 = VIH
Wait 4µs
INCREMENT
CURRENT GROUP
READ DATA
ADDRESS =
CURRENT GROUP ADDRESS
A0, A2, A3 = VIL, A1, A6 = VIH
NO
End
NO
DATA = 00h
++n
= 1000
YES
YES
LAST
GROUP
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI07759
1. Block Protection Groups are shown in Appendix D, Table 24.
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Revision history
Revision history
Table 33.
Document revision history
Date
Revision
Changes
02-Dec-2005
1.0
First issue.
10-Mar-2006
2.0
DQ7 changed to DQ7 for Program, Program During Erase
Suspend and Program Error in Table 9: Status Register Bits.
Converted to new template.
Updated address values in Table 31: Extended Block address and
data.
23-Aug-2006
3
Amended data in Table 28: Device Geometry Definition
10-Dec-2007
4
Applied Numonyx branding.
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