ICST ICS181M-03T Low emi clock generator Datasheet

ICS181-03
Low EMI Clock Generator
Description
Features
The ICS181-03 generates a low EMI output clock from
a clock or crystal input. The device uses ICS’
proprietary mix of analog and digital Phase-Locked
Loop (PLL) technology to spread the frequency
spectrum of the output, thereby reducing the frequency
amplitude peaks by several dB.
•
•
•
•
The ICS181-03 offers down spread selection of -1.25%
and -3.75%. Refer to the MK1714-01/02 for the widest
selection of input frequencies and multipliers.
ICS offers a complete line of EMI reducing clock
generators. Consult us when you need to remove
crystals and oscillators from your board.
Pin and function compatible to Cypress W181-03
Packaged in 8-pin SOIC
Provides a spread spectrum output clock
Accepts a clock input and provides same frequency
dithered output
• Input frequency of 46 to 75 MHz for Clock input
• Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
• Spread percentage selection for -1.25% and -3.75%
• Operating voltage of 3.3 V and 5 V
• Advanced, low-power CMOS process
Block Diagram
VDD
FS1
SSON#
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
SS%
CLK
CLK
Clock Buffer
GND
MDS 181-03 A
1
I n t e gra t e d C i r cu i t S y s t e m s l 5 25 Race Street, San Jo se, CA 9 512 6
Revision 110404
l
tel (408 ) 29 7-120 1
l
w w w. i c st . c o m
ICS181-03
LOW EMI CLOCK GENERATOR
Pin Assignment
Spread Spectrum Select Table
CLKIN
1
8
SSON#
NC
2
7
FS1
GND
3
6
VDD
SS%
4
5
CLKOUT
SS%
(Pin 4)
Spread
Direction
Spread
Percentage (%)
0
1
Down
Down
-1.25%
-3.75%
0 = connect to GND
1 = connect directly to VDD
Note: SS% pin has an internal pull-up resistor
8-pin (150 mil) SOIC
Frequency Range Selection Table
FS1
(Pin 7)
Frequency Range Selection
(MHz)
0
1
46-60
58-75
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
1
CLKIN
Input
2
NC
—
3
GND
Power
Connect to ground.
4
SS%
Input
Select pin for spread amount. See table above. Internal pull-up resistor.
5
CLKOUT
Output
Spread spectrum clock output per table above.
6
VDD
Power
Connect to 3.3 V or 5 V.
7
FS1
Input
Select pin for input frequency. See table above. Internal pull-up resistor.
8
SSON#
Input
Spread Spectrum Control. This pin enables spread spectrum when low.
Internal pull-down resistor.
MDS 181-03 A
Pin Description
Clock Input.
No connect. Do not connect this pin to anything.
2
I n t e gra t e d C i r cu i t S y s t e m s l 52 5 Race Stre et, San Jose, CA 95 126
Revision 110404
l
te l (4 08) 297 -1 201 l w w w. i c s t . c o m
ICS181-03
LOW EMI CLOCK GENERATOR
External Components
The ICS181-03 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 6 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 33Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS181-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
value of these capacitors is given by the following
equation:
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS181-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70°C
Storage Temperature
-65 to +150°C
Junction Temperature
125°C
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
MDS 181-03 A
Typ.
Max.
Units
0
+70
°C
+3.135
+5.5
V
3
I n t e gra t e d C i r cu i t S y s t e m s l 52 5 Race Stre et, San Jose, CA 95 126
Revision 110404
l
te l (4 08) 297 -1 201 l w w w. i c s t . c o m
ICS181-03
LOW EMI CLOCK GENERATOR
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ± 5%, Ambient Temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
Typ.
Units
3.465
V
32
mA
Operating Voltage
VDD
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
Output High Voltage
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -15 mA
2.4
V
Output Low Voltage
VOL
IOL = 15 mA
Input Capacitance
CIN
All pins except CLKIN
CLKIN pin only
Output Impedance
3.135
Max.
No load, at 3.3 V
18
2.4
0.8
Rout
Input Pull-up Resistor
Power-up Time
V
V
0.4
V
5
7
pF
6
10
pF
25
ohms
500
KΩ
First locked clock
cycle after steady
power
5
ms
Unless stated otherwise, VDD = 5 V, ±10%, Ambient Temperature 0 to +70°C
Parameter
Symbol
Conditions
Operating Voltage
VDD
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
Output High Voltage
VOH
IOH = -24 mA
Output Low Voltage
VOL
IOL = 24 mA
Output Impedance
Rout
Input Capacitance
CIN
Min.
Typ.
Max.
Units
4.5
5
5.5
V
30
50
mA
No load, at 3.3 V
0.7VDD
0.15VDD
2.4
MDS 181-03 A
V
V
0.4
20
V
ohms
All pins except CLKIN
5
7
pF
CLKIN pin only
6
10
pF
Input Pull-up Resistor
Power-up Time
V
500
First locked clock
cycle after steady
power
5
4
I n t e gra t e d C i r cu i t S y s t e m s l 52 5 Race Stre et, San Jose, CA 95 126
KΩ
ms
Revision 110404
l
te l (4 08) 297 -1 201 l w w w. i c s t . c o m
ICS181-03
LOW EMI CLOCK GENERATOR
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V±5% or 5 V±10%, Ambient Temperature 0 to +70° C, CL=15 pf
Parameter
Symbol
Conditions
Min.
Input/Output Clock Frequency
Typ.
Max. Units
46
75
MHz
60
%
50
60
%
Input Clock Duty Cycle
Time above VDD/2
40
Output Clock Duty Cycle
Note 1
40
Output Rise Time
tOR
0.8 to 2.4 V, note 1
2
5
ns
Output Fall Time
tOF
2.4 to 0.8 V, note 1
2
5
ns
250
300
ps
Jitter
Cycle-to-cycle
Note 1: Measured with 15 pF load
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
150
°C/W
θJA
1 m/s air flow
140
°C/W
θJA
3 m/s air flow
120
°C/W
40
°C/W
θJC
Marking Diagram
Notes:
8
5
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week
that the part was assembled.
181M-03
######
YYWW
1
3. “LF” denotes Pb (lead) free package.
4. Bottom marking: country of origin.
4
Marking Diagram (Pb free)
8
5
181M03LF
######
YYWW
1
MDS 181-03 A
4
5
I n t e gra t e d C i r cu i t S y s t e m s l 52 5 Race Stre et, San Jose, CA 95 126
Revision 110404
l
te l (4 08) 297 -1 201 l w w w. i c s t . c o m
ICS181-03
LOW EMI CLOCK GENERATOR
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Symbol
E
Min
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS181M-03
ICS181M-03T
ICS181M-03LF
ICS181M-03LFT
Marking
see page 5
Shipping
packaging
Package
Temperature
Tubes
Tape and Reel
Tubes
Tape and Reel
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
“LF” denotes Pb free packaging.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 181-03 A
6
I n t e gra t e d C i r cu i t S y s t e m s l 52 5 Race Stre et, San Jose, CA 95 126
Revision 110404
l
te l (4 08) 297 -1 201 l w w w. i c s t . c o m
Similar pages