ON MC74LVX541MG Octal bus buffer Datasheet

MC74LVX541
Octal Bus Buffer
The MC74LVX541 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74LVX541 is a noninverting type. When either OE1 or OE2
are high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
20
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 5.0 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 4 A (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 3.6 V Operating Range
Low Noise: VOLP = 1.2 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
SOIC−20
DW SUFFIX
CASE 751D
20
1
LVX541
AWLYYWWG
1
20
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ−20
M SUFFIX
CASE 967
1
20
1
LVX541
A
WL, L
Y
WW, W
G or G
LVX
541
ALYWG
G
LVX541
AWLYWWG
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 4
1
Publication Order Number:
MC74LVX541/D
MC74LVX541
A1
A2
A3
A4
DATA
INPUTS
A5
A6
A7
A8
OE1
OUTPUT
ENABLES
OE2
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
Y1
Y2
Y3
Y4
NONINVERTING
OUTPUTS
Y5
Y6
Y7
Y8
1
19
Figure 1. LOGIC DIAGRAM
QE1
OE1
1
20
VCC
A1
2
19
OE2
A2
3
18
Y1
A3
4
17
Y2
A4
5
16
Y3
A3
A5
6
15
Y4
A4
A6
7
14
Y5
A7
8
13
Y6
A8
GND
QE2
A1
A2
A5
A6
9
12
Y7
A7
10
11
Y8
A8
Figure 2. PIN ASSIGNMENT
1
&
EN
19
2
1
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
Figure 3. IEC LOGIC DIAGRAM
FUNCTION TABLE
Inputs
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
Output Y
L
H
Z
Z
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2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
MC74LVX541
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
°C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
3.6
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
−40
+ 85
°C
0
100
ns/V
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
VCC = 3.3V ±0.3V
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
1.50
2.0
2.4
VIH
Minimum High−Level Input Voltage
2.0
3.0
3.6
VIL
Maximum Low−Level Input Voltage
2.0
3.0
3.6
VOH
Minimum High−Level Output Voltage
Vin = VIH or VIL
IOH = − 50 A
IOH = − 50 A
IOH = − 4 mA
2.0
3.0
3.0
VOL
Maximum Low−Level Output Voltage
Vin = VIH or VIL
IOL = 50 A
IOL = 50 A
IOL = 4 mA
2.0
3.0
3.0
Iin
Maximum Input Leakage Current
Vin = 5.5 V or GND
IOZ
Maximum Three−State Leakage
Current
ICC
Maximum Quiescent Supply Current
Typ
TA = − 40 to 85°C
Max
Min
1.50
2.0
2.4
0.50
0.80
0.80
1.9
2.9
2.58
Max
2.0
3.0
V
0.50
0.80
0.80
1.9
2.9
2.48
V
V
0.1
0.1
0.36
0.1
0.1
0.44
V
0 to
3.6
±0.1
±1.0
A
Vin = VIL or VIH
Vout = VCC or GND
3.6
±0.2
5
±2.5
A
Vin = VCC or GND
3.6
4.0
40.0
A
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3
0.0
0.0
Unit
MC74LVX541
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Parameter
Maximum Propagation Delay,
A to Y
Output Enable TIme,
OE to Y
Output Disable Time,
OE to Y
Output to Output Skew
Test Conditions
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 2.7 V
CL = 15 pF
CL = 50 pF
5.0
7.5
7.0
10.5
1.0
1.0
8.5
12.0
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
3.5
5.0
5.0
7.0
1.0
1.0
6.0
8.0
VCC = 2.7 V
RL = 1 k
CL = 15 pF
CL = 50 pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
VCC = 3.3 ± 0.3 V
RL = 1 k
CL = 15 pF
CL = 50 pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
VCC = 2.7 V
RL = 1 k
CL = 50 pF
11.2
15.4
1.0
17.5
VCC = 3.3 ± 0.3 V
RL = 1 k
CL = 50 pF
6.0
8.8
1.0
10.0
VCC = 2.7 V
(Note 1)
CL = 50 pF
1.5
1.5
ns
VCC = 3.3 ± 0.3 V
(Note 1)
CL = 50 pF
1.0
1.0
ns
10
10
pF
Cin
Maximum Input Capacitance
4.0
Cout
Maximum Three−State Output
Capacitance
(Output in High Impedance
State)
6.0
CPD
Power Dissipation Capacitance (Note 2)
ns
ns
pF
Typical @ 25°C, VCC = 5.0V
18
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 3.3 V)
TA = 25°C
Symbol
Parameter
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.5
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
SWITCHING WAVEFORMS
VCC
OE1 or OE2
VCC
50%
50%
GND
A
50%
tPZL
GND
tPHL
tPLH
Y
tPLZ
HIGH
IMPEDANCE
50% VCC
VOL +0.3 V
Y
tPZH
50% VCC
tPHZ
VOH -0.3 V
Y
Figure 4.
50% VCC
Figure 5.
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4
HIGH
IMPEDANCE
MC74LVX541
TEST CIRCUITS
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 k
CL*
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
INPUT
Figure 8. INPUT EQUIVALENT CIRCUIT
ORDERING INFORMATION
Package
Shipping†
SOIC−20
(Pb−Free)
38 Units / Rail
MC74LVX541DTR2G
TSSOP−20*
(Pb−Free)
2500 Tape & Reel
MC74LVX541MG
SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74LVX541MELG
SOEIAJ−20
(Pb−Free)
2000 Tape & Reel
Device
MC74LVX541DWG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74LVX541
PACKAGE DIMENSIONS
SOIC−20
CASE 751D−05
ISSUE G
D
A
11
X 45 _
E
h
H
M
10X
0.25
B
M
20
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
1
10
20X
B
B
0.25
DIM
A
A1
B
C
D
E
e
H
h
L
q
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
C
T
SOEIAJ−20
CASE 967−01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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6
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
MC74LVX541
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
PIN 1
IDENT
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
SECTION N−N
0.25 (0.010)
N
10
M
0.15 (0.006) T U
S
N
A
−V−
F
DETAIL E
−W−
C
G
D
H
0.100 (0.004)
−T− SEATING
DETAIL E
SOLDERING FOOTPRINT
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74LVX541/D