ON MMDF4C03HD Complementary soâ 8, dual power mosfet Datasheet

MMDF4C03HD
Power MOSFET
4 Amps, 30 Volts
Complementary SO−8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc−dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
• Logic Level Gate Drive − Can be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Ideal for Synchronous Rectification
• Diode Exhibits High Speed, with Soft Recovery
• IDSS Specified at Elevated Temperature
• Mounting Information for SO−8 Package Provided
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4 AMPERES
30 VOLTS
RDS(on) = 50 m (N−Channel)
RDS(on) = 85 m (P−Channel)
N−Channel
P−Channel
D
D
G
G
S
S
MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
Vdc
Gate−to−Source Voltage
VGS
± 20
Vdc
Rating
Drain Current − Continuous
N−Channel
P−Channel
Drain Current − Pulsed
N−Channel
P−Channel
ID
Adc
5.5
4.4
IDM
Apk
L
Y
WW
25
20
−55 to
+150
°C
Total Power Dissipation @ TA = 25°C
(Note 1)
PD
2.5
Watts
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 5.0 Vdc, IL = 9.0 Apk,
L = 10 mH, RG = 25 )
N−Channel
(VDD = 30 Vdc, VGS = 5.0 Vdc, IL = 9.0 Apk,
L = 10 mH, RG = 25 )
P−Channel
EAS
Thermal Resistance − Junction−to−Ambient
(Note 1)
RθJA
50
°C/W
TL
260
°C
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 sec.
D4C03HD
LYWW
1
TJ, Tstg
Operating and Storage Temperature Range
SO−8, Dual
CASE 751
STYLE 11
8
mJ
325
= Location Code
= Year
= Work Week
PIN ASSIGNMENT
Source−1
1
8
Drain−1
Gate−1
2
7
Drain−1
Source−2
3
6
Drain−2
Gate−2
4
5
Drain−2
Top View
450
1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
ORDERING INFORMATION
Device
MMDF4C03HDR2
Package
SO−8
Shipping
2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
 Semiconductor Components Industries, LLC, 2004
June, 2004 − Rev. XXX
1
Publication Order Number:
MMDF4C03HD/D
MMDF4C03HD
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Characteristic
Polarity
Min
Typ
Max
−
30
−
−
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Vdc
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
IDSS
(N)
(P)
−
−
−
−
1.0
1.0
µAdc
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
−
−
−
±100
nAdc
Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
−
−
1.0
−
−
−
−
−
Vdc
mV/°C
Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 3.5 Adc)
(VGS = 10 Vdc, ID = 3.5 Adc)
RDS(on)
Note 2
(N)
(P)
−
−
0.037
0.075
0.05
0.085
Ohms
Static Drain−to−Source On−Resistance
(VGS = 4.5 Vdc, ID = 2.5 Adc)
(VGS = 4.5 Vdc, ID = 2.0 Adc)
RDS(on)
Note 2
(N)
(P)
−
−
0.55
0.125
0.08
0.16
gFS
(N)
(P)
−
−
9.0
6.0
−
−
mhos
Ciss
(N)
(P)
−
−
430
425
600
600
pF
Coss
(N)
(P)
−
−
217
209
300
300
Crss
(N)
(P)
−
−
67.5
57.2
135
80
td(on)
(N)
(P)
−
−
8.2
11.7
16.4
23.4
tr
(N)
(P)
−
−
8.48
15.8
16.9
31.6
td(off)
(N)
(P)
−
−
89.6
167.3
179
334.6
tf
(N)
(P)
−
−
61.1
102.6
122
205.2
QT
(N)
(P)
−
−
15.7
14.8
31.4
29.6
Q1
(N)
(P)
−
−
2.0
1.7
−
−
Q2
(N)
(P)
−
−
4.6
4.7
−
−
Q3
(N)
(P)
−
−
3.9
3.4
−
−
ON CHARACTERISTICS (Note 2)
Forward Transconductance
(VDS = 15 Vdc, ID = 3.5 Adc)
Ohms
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Vd
(VDS = 24 Vdc,
VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 15 Vdc,
ID = 1.0 Adc,
VGS = 10 Vdc,
RG = 6.0 Ω)
Fall Time
Total Gate Charge
(See Figure
8)
g
(VDS = 10 Vdc,
ID = 3.5
3 5 Adc,
Adc
VGS = 10 Vdc)
2. Switching characteristics are independent of operating junction temperature.
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2
ns
nC
MMDF4C03HD
ELECTRICAL CHARACTERISTICS − continued (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Polarity
Min
Typ
Max
Unit
VSD
(N)
(P)
−
−
0.77
0.90
1.2
1.2
Vdc
trr
(N)
(P)
−
−
54.5
77.4
−
−
ns
ta
(N)
(P)
−
−
14.8
19.9
−
−
tb
(N)
(P)
−
−
39.7
57.5
−
−
QRR
(N)
(P)
−
−
0.048
0.088
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(Note 2)
Reverse Recovery Time
(IS = 1.7 Adc, VGS = 0 Vdc)
(IS = −1.7 Adc, VGS = 0 Vdc)
(N)
(ID = 3.5 Adc,
VGS = 0 Vdc
dIS/dt = 100 A/µs)
(P)
Reverse Recovery Stored
Charge
(ID = 3.5
3 5 Adc,
Adc
VGS = 0 Vdc
dIS/dt = 100 A/µs)
2. Switching characteristics are independent of operating junction temperature.
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3
µC
MMDF4C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
P−Channel
12
3.9 V
10
TJ = 25C
3.7 V
ID , DRAIN CURRENT (AMPS)
ID , DRAIN CURRENT (AMPS)
10 V
6.0 V
6.0
4.5 V
3.5 V
4.3 V
4.1 V
8.0
3.3 V
6.0
3.1 V
4.0
2.9 V
2.0
0
VGS = 2.5 V
2.7 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
3.9 V
4.3 V
4.0
3.7 V
3.0
3.5 V
2.0
3.3 V
3.1 V
2.9 V
2.7 V
1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 1. On−Region Characteristics
2.0
6.0
ID , DRAIN CURRENT (AMPS)
ID , DRAIN CURRENT (AMPS)
4.1 V
4.5 V
2.0
12
10
TJ = 25C
6.0 V
5.0
0
0
VGS = 10 V
VDS ≥ 10 V
8.0
6.0
100C
25C
4.0
TJ = −55C
2.0
5.0
VDS ≥ 10 V
100C
4.0
3.0
2.0
25C
1.0
TJ = −55C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.0
2.5
3.0
3.5
4.0
4.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
Figure 2. Transfer Characteristics
0.30
TJ = 25C
ID = 6 A
0.25
0.20
0.15
0.10
0.05
0
2.0
0
1.5
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
1.5
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.8
TJ = 25C
ID = 3 A
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.0
Figure 3. On−Resistance versus
Gate−To−Source Voltage
3.0
4.0
5.0
6.0
7.0
8.0
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9.0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
4
5.0
10
MMDF4C03HD
0.050
P−Channel
RDS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)
N−Channel
0.18
TJ = 25C
TJ = 25C
0.16
0.045
VGS = 4.5 V
VGS = 4.5 V
0.14
0.040
0.12
0.10
0.035
0.08
10 V
0.030
10 V
0.06
1.0
3.0
2.0
4.0
5.0
6.0
7.0
8.0
9.0
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.8
1.6
VGS = 10 V
ID = 3 A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
−50
−25
25
0
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 5. On−Resistance Variation with
Temperature
1000
0.04
1.0
2.0
1.5
2.5
3.5
4.0
4.5
5.0
5.5
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
VGS = 10 V
ID = 1.5 A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
−50
−25
25
0
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (C)
Figure 5. On−Resistance Variation with
Temperature
100
VGS = 0 V
VGS = 0 V
TJ = 125C
TJ = 125C
100
IDSS , LEAKAGE (nA)
IDSS , LEAKAGE (nA)
3.0
ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
0.025
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
TYPICAL ELECTRICAL CHARACTERISTICS
100C
10
25C
1.0
0.1
0
5.0
10
15
20
25
10
100C
1.0
30
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
5.0
10
15
20
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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30
MMDF4C03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
t QIG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr Q2 RG(VGG VGSP)
tr Q2 RGVGSP
where
VGG the gate drive voltage , which varies zero VGG
RG the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) RG Ciss In [VGG(VGG VGSP)]
td(off) RG Ciss In (VGGVGSP)
N−Channel
P−Channel
1000
1200
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
TJ = 25C
1000
800
600
Ciss
400
Coss
200
TJ = 25C
800
600
Ciss
400
Coss
200
Crss
Crss
0
−10 −5.0
0
VGS
5.0
10
15
20
25
30
0
−10 −5.0
VDS
0
VGS
5.0
VDS
10
15
20
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 7. Capacitance Variation
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6
30
12
30
11
10
9.0
QT
VGS
8.0
7.0
6.0
20
Q2
Q1
5.0
10
ID = 5 A
TJ = 25C
4.0
3.0
2.0
1.0
0
VDS
Q3
2.0
0
4.0
6.0
8.0
10
12
14
0
16
Qg, TOTAL GATE CHARGE (nC)
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
MMDF4C03HD
7.0
30
QT
6.0
VGS
5.0
20
Q2
Q1
4.0
3.0
10
ID = 3 A
TJ = 25C
2.0
1.0
VDS
Q3
0
0
2.0
4.0
6.0
8.0
10
12
14
0
16
Qg, TOTAL GATE CHARGE (nC)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1000
1000
VDD = 15 V, ID = 3 A
VGS = 10 V, TJ = 25C
100
td(off)
tf
t, TIME (ns)
t, TIME (ns)
VDD = 15 V, ID = 6 A
VGS = 10 V, TJ = 25C
tr
10
100
td(off)
tf
10
tr
td(on)
td(on)
1.0
1.0
1.0
10
100
1.0
RG, GATE RESISTANCE (OHMS)
10
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
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MMDF4C03HD
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
N−Channel
P−Channel
IS, SOURCE CURRENT (AMPS)
4.5
2.5
VGS = 0 V
TJ = 25C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VGS = 0 V
TJ = 25C
2.0
1.5
1.0
0.5
0.5
0
0.50 0.55
0.60
0.65
0.70
0.75
0.80
0.85
0
0.50 0.55
0.90
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.60
0.65
0.70
0.75
0.80
0.85 0.90
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
Figure 10. Diode Forward Voltage versus Current
di/dt = 300 A/ms
Standard Cell Density
trr
I S, SOURCE CURRENT
IS, SOURCE CURRENT (AMPS)
5.0
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
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MMDF4C03HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 µs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
N−Channel
P−Channel
VGS = 12 V
SINGLE PULSE
TA = 25C
10
ID, DRAIN CURRENT (AMPS)
100
1.0 ms
10 ms
1.0
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
1.0 ms
10 ms
1.0
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.01
0.1
1.0
10
0.1
100
10
1.0
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
350
ID = 6 A
300
250
200
150
100
50
0
VGS = 12 V
SINGLE PULSE
TA = 25C
10
25
45
65
85
105
125
145
EAS, SINGLE PULSE DRAIN−TO−SOURC
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
100
500
ID = 3 A
450
400
350
300
250
200
150
100
50
0
25
TJ, STARTING JUNCTION TEMPERATURE (C)
45
65
85
105
125
145
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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MMDF4C03HD
Rthja(t)
, EFFECTIVE TRANSIENT
THERMAL RESISTANCE
TYPICAL ELECTRICAL CHARACTERISTICS
10
1.0
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
0.00001
0.0001
0.001
0.01
0.1
t, TIME (seconds)
1.0
10
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
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100
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INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self−align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO−8 POWER DISSIPATION
The power dissipation of the SO−8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient; and the operating
temperature, TA. Using the values provided on the data
sheet for the SO−8 package, PD can be calculated as
follows:
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 2.0 Watts.
PD 150°C 25°C 2.0 Watts
62.5°CW
The 62.5°C/W for the SO−8 package assumes the
recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Clad. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.
T
TA
PD J(max)
RJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177 −189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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MMDF4C03HD
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE V
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
K
−Y−
G
C
N
X 45 SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
XXXXXX
ALYW
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DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
MMDF4C03HD
Notes
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MMDF4C03HD
Notes
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MMDF4C03HD
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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