AZM AZ100LVEL33 Ecl/pecl ã·4 divider Datasheet

ARIZONA MICROTEK, INC.
AZ100LVEL33
ECL/PECL ÷4 Divider
PACKAGE AVAILABILITY
FEATURES










PACKAGE
Green / RoHS Compliant /
Lead (Pb) Free package available
Operating Range of 3.0V to 5.5V
470ps Propagation Delay
5.0+ GHz Toggle Frequency
Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC100EL33 & MC100LVEL33
Transistor Count = 91 Devices
IBIS Model Files Available on Arizona
Microtek Web Site
>2 kV HBM ESD Protection
Additional ESD Data Available on
Arizona Microtek Website
PART NUMBER
MLP 8 (2x2) Green
/ RoHS Compliant /
Lead (Pb) Free
SOIC 8 Green /
RoHS Compliant /
Lead (Pb) Free
MSOP 8 Green /
RoHS Compliant /
Lead (Pb) Free
1
2
3
MARKING
NOTES
AZ100LVEL33NG
C3G
<Date Code>
1,2
AZ100LVEL33DG
AZM100G
LVEL33
1,2,3
AZ100LVEL33TG
AZHG
LV33
1,2,3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K
parts) Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
Date code “YWW” or “YYWW” on underside of part.
DESCRIPTION
The AZ100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low,
Q̄ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for
the synchronization of multiple LVEL33’s in a system.
The LVEL33 provides a VBB output for single-end use or a DC bias reference for AC coupling to the device.
¯¯¯¯ differential
For single-ended input applications, the VBB reference should be connected to one side of the CLK/ CLK
input pair. The input signal is then fed to the other CLK/ CLK
¯¯¯¯ input. The VBB pin can support 1.0mA sink/source
current. When used, the VBB pin should be bypassed to ground via a 0.01F capacitor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM
PIN DESCRIPTION
PIN
CLK, CLK
¯¯¯
RESET
VBB
Q, Q̄
VCC
VEE
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
RESET
R
Q
÷4
CLK
CLK
Q
VBB
1630 S. STAPLEY DR., SUITE 127  MESA, ARIZONA 85204  USA  (480) 962-5881  FAX (623) 505-2414
www.azmicrotek.com
AZ100LVEL33
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VCC
VI
VEE
VI
IOUT
TA
TSTG
Characteristic
PECL Power Supply (VEE = 0V)
PECL Input Voltage
(VEE = 0V)
ECL Power Supply
(VCC = 0V)
ECL Input Voltage
(VCC = 0V)
Output Current
--- Continuous
--- Surge
Operating Temperature Range
Storage Temperature Range
Rating
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
C
C
ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
Characteristic
1
Min
-1085
-1830
-1165
-1810
-1380
-40C
Typ
-1005
-1695
Max
-880
-1555
-880
-1475
-1260
150
Output HIGH Voltage
Output LOW Voltage1
Input HIGH Voltage
Input LOW Voltage
Reference Voltage
Input HIGH Current
Input LOW Current
CLK, CLK
¯¯¯
-150
RESET
0.5
Power Supply Current
27
33
Each output is terminated through a 50 resistor to VCC – 2V.
Min
-1025
-1810
-1165
-1810
-1380
0C
Typ
-955
-1705
Max
-880
-1620
-880
-1475
-1260
150
-150
0.5
Min
-1025
-1810
-1165
-1810
-1380
25C
Typ
-955
-1705
Max
-880
-1620
-880
-1475
-1260
150
-150
0.5
27
33
Min
-1025
-1810
-1165
-1810
-1380
85C
Typ
-955
-1705
Max
-880
-1620
-880
-1475
-1260
150
33
mV
mV
mV
mV
mV
A
A
-150
0.5
27
Unit
31
37
mA
LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
Characteristic
1,2
Min
2215
1470
2135
1490
1920
-40C
Typ
2295
1605
Max
2420
1745
2420
1825
2040
150
Min
2275
1490
2135
1490
1920
0C
Typ
2345
1595
Max
2420
1680
2420
1825
2040
150
Min
2275
1490
2135
1490
1920
Output HIGH Voltage
Output LOW Voltage1,2
Input HIGH Voltage1
Input LOW Voltage1
Reference Voltage1
Input HIGH Current
Input LOW Current
-150
-150
-150
CLK, CLK
¯¯¯
0.5
0.5
0.5
RESET
Power Supply Current
27
33
27
33
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
Each output is terminated through a 50 resistor to VCC – 2V.
25C
Typ
2345
1595
Max
2420
1680
2420
1825
2040
150
Min
2275
1490
2135
1490
1920
85C
Typ
2345
1595
Max
2420
1680
2420
1825
2040
150
33
mV
mV
mV
mV
mV
A
A
-150
0.5
27
Unit
31
37
mA
PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
Characteristic
1,2
Min
3915
3170
3835
3190
3620
-40C
Typ
3995
3305
Max
4120
3445
4120
3525
3740
150
Min
3975
3190
3835
3190
3620
0C
Typ
4045
3295
Max
4120
3380
4120
3525
3740
150
Min
3975
3190
3835
3190
3620
Output HIGH Voltage
Output LOW Voltage1,2
Input HIGH Voltage1
Input LOW Voltage1
Reference Voltage1
Input HIGH Current
Input LOW Current
CLK, CLK
¯¯¯
-150
-150
-150
RESET
0.5
0.5
0.5
Power Supply Current
27
33
27
33
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
Each output is terminated through a 50 resistor to VCC – 2V.
April 2011 * REV - 13
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2
25C
Typ
4045
3295
Max
4120
3380
4120
3525
3740
150
Min
3975
3190
3835
3190
3620
85C
Typ
4045
3295
Max
4120
3380
4120
3525
3740
150
33
mV
mV
mV
mV
mV
A
A
-150
0.5
27
Unit
31
37
mA
AZ100LVEL33
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
Symbol
Characteristic
tRR
Maximum Toggle
Frequency
Propagation Delay
CLK, CLK
¯¯¯ to Q/Q̄
RESET to Q/Q̄
Reset Recovery
tskew
Within-Device Skew
fmax
tPLH / tPHL
Min
-40C
Typ
Max
4.2
360
310
300
Min
0C
Typ
Max
4.2
450
460
540
610
320
340
300
Min
25C
Typ
Max
4.2
460
460
550
580
20
380
360
300
Min
85C
Typ
Max
4.2
470
460
20
560
560
400
380
300
GHz
490
480
580
580
20
Input Swing1
150
1000
150
1000
150
1000
150
1000
Common Mode Range2
VCC VEE +
VCC VEE +
VCC VEE +
VCC VEE +
1.2
0.4
1.1
0.4
1.1
0.4
1.1
0.4
VCMR
Vpp  500mV
1.4
0.4
1.3
0.4
1.3
0.4
1.3
0.4
Vpp  500mV
Output Rise/Fall Times
tr / t f
100
260
100
260
100
260
100
260
Q/Q̄ (20% - 80%)
1.
VPP is the peak-to-peak differential input swing for which AC parameters are guaranteed.
2.
VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that VPP is within the differential input swing range specified.
CLK
RESET
Q
Figure 1. Timing Diagram
Typical Large Signal Output Swing, Q/Q̄
900
800
VOUTpp(mV)
700
fOUT=fIN÷4
600
500
400
300
200
1000
2000
3000
4000
5000
INPUT FREQUENCY (MHz)
Measured with 750mv D input, Q/Q̄ each terminated to VCC-2V via 50 Ω resistors.
April 2011 * REV - 13
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3
ps
ps
20
VPP (AC)
0
Unit
ps
mV
V
ps
AZ100LVEL33
PACKAGE PINOUTS
TOP VIEW
AZ100LVEL33N
RESET
1
8
VCC
CLK
2
7
Q
CLK
3
6
Q
VBB
4
5
VEE
MLP 8
Bottom Center Pad may be left open or tied to VEE.
AZ100LVEL33D
AZ100LVEL33T
April 2011 * REV - 13
RESET 1
8
VCC
CLK
2
7
Q
CLK
3
6
Q
VBB
4
5
VEE
SOIC 8
MSOP 8
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4
AZ100LVEL33
PACKAGE DIAGRAM
SOIC 8
NOTES:
1.
DIMENSIONS D AND E DO NOT
INCLUDE MOLD PROTRUSION.
2.
MAXIMUM MOLD PROTRUSION
FOR D IS 0.15mm.
3.
MAXIMUM MOLD PROTRUSION
FOR E IS 0.25mm.
April 2011 * REV - 13
DIM
A
A1
A2
A3
bp
c
D
E
e
HE
L
Lp
Q
v
w
y
Z

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5
MILLIMETERS
MIN
MAX
1.75
0.10
0.25
1.25
1.45
0.25
0.36
0.49
0.19
0.25
4.8
5.0
3.8
4.0
1.27
5.80
6.20
1.05
0.40
1.00
0.60
0.70
0.25
0.25
0.10
0.30
0.70
0O
8O
INCHES
MIN
MAX
0.069
0.004
0.010
0.049
0.057
0.01
0.014
0.019
0.0075
0.0100
0.19
0.20
0.15
0.16
0.050
0.228
0.244
0.041
0.016
0.039
0.024
0.028
0.01
0.01
0.004
0.012
0.028
0O
8O
AZ100LVEL33
PACKAGE DIAGRAM
MSOP 8
DIM
A
A1
A2
A3
bp
c
D
E
e
HE
L
Lp
v
w
y
Z

NOTES:
1.
DIMENSIONS D AND E DO NOT
INCLUDE MOLD PROTRUSION.
2.
MAXIMUM MOLD PROTRUSION
FOR D IS 0.15mm.
3.
MAXIMUM MOLD PROTRUSION
FOR E IS 0.25mm.
April 2011 * REV - 13
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6
MILLIMETERS
MIN
MAX
1.10
0.05
0.15
0.80
0.95
0.25
0.25
0.45
0.15
0.28
2.90
3.10
2.90
3.10
0.65
4.70
5.10
0.94
0.40
0.70
0.10
0.10
0.10
0.35
0.70
0O
6O
AZ100LVEL33
PACKAGE DIAGRAM
MLP 8 2x2mm
Pin 1 Dot
By Marking
2.000±0.050
MLP 8
(2x2mm)
2.000±0.050
TOP VIEW
Pin 1 Identification
R0.100 TYP
0.350±0.050
0.250±0.050
0.500 bsc
8
1
7
6
2 1.200±0.050
exp. pad
3
5
4
0.600±0.050
exp. pad
BOTTOM VIEW
0.750±0.050
0.000-0.050
1
2
SIDE VIEW
Note: All dimensions are in mm
April 2011 * REV - 13
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7
3 4
0.203±0.025
1.750
Ref.
AZ100LVEL33
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
April 2011 * REV - 13
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8
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