ISSI IS42S16160C-6TL 256 mb single data rate synchronous dram Datasheet

IS42S83200C
IS42S16160C
256 Mb Single Data Rate Synchronous DRAM
APRIL 2009
General Description
IS42S83200C is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and
IS42S16160C is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to
the rising edge of CLK. IS42S83200C and IS42S16160C achieve very high speed data rates up to 166MHz, and
are suitable for main memories or graphic memories in computer systems.
Features
- Single 3.3V ±0.3V power supply
- Max. Clock frequency :
- 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- LDQM and UDQM (IS42S16160C)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Pb-free package is available
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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Rev. C
04/02/09
1
IS42S83200C
IS42S16160C
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
2
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
DQM
A0-12
BA0,1
Vdd
VddQ
VSS
VSSQ
: Output Disable / Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
04/02/09
IS42S83200C
IS42S16160C
Note: This figure shows the IS42S83200C.
The IS42S16160C configuration is 8192x512x16 of cell array and DQ0-15
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Rev. C
04/02/09
3
IS42S83200C
IS42S16160C
Pin Descriptions
SYMBOL
TYPE
DESCRIPTION
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE
Input
/CS
Input
/CAS,
/RAS,
/WE
Input
LDQM,
UDQM (x16)
Input
DQM (x8)
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
bank selection on systems with multiple banks. /CS is considered part of the command code.
Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM
corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are
considered same state when referenced as DQM.
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. These pins also select between the mode register and
the extended mode register.
A0–A12
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is
specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also
used to indicate precharge option. When A10 is high at a read / write command, an auto
precharge is performed. When A10 is high at a precharge command, all banks are precharged.
DQ0-DQ15 (x16)
DQ0-DQ7 (x8)
I/O
NC
–
VDDQ
Supply
VSSQ
Supply
VDD
Supply
VSS
Supply
BA0, BA1
4
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank), DEEP POWER DOWN (all banks idle), or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied HIGH.
Data Input/Output: Data bus.
Internally Not Connected: These could be left unconnected, but it is recommended they be
connected or VSS.
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Core Power Supply.
Ground.
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Rev. C
04/02/09
IS42S83200C
IS42S16160C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VIN,VOUT
-0.5 ~ 4.6
V
VDD, VDDQ
-0.5 ~ 4.6
V
TSTG
-65 ~ +150
C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Voltage on any pin relative to Vss
Voltage on VDD supply relative to V ss
Storage temperature
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
o
Recommended operating conditions (Voltage referenced to VSS = 0V, Commerical grade:TA = 0 to 70 C, Industrial grade:TA = -40 to 85 C)
Parameter
Symbol
Min
Typ
Max
Unit
Vdd
3.0
3.3
3.6
V
VddQ
3.0
3.3
3.6
V
Input logic high voltage
VIH
2.0
VDDQ + 0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH = -0.1mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 0.1mA
Input leakage current
ILI
-5
-
5
uA
3
Output leakage current
IoL
-5
-
5
uA
3
Supply voltage
Note
Note:
1. VIH(max) = VDDQ + 2V AC for pulse width 3ns acceptable.
2. VIL(min) = -2V AC for pulse width 3ns acceptable.
3. Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V VOUT VDD.
CAPACITANCE
( Vdd =3.3V, T A = 25°C, f = 1MHz
Parameter
Symbol
Min
Max
Unit
Clock
Cclk
2.5
4.0
pF
/CAS,/RAS,/WE,/CS,CKE,L/UDQM
Cin
2.5
5.0
pF
Address
CADD
2.5
5.0
pF
DQ0~DQ15
COUT
4.0
6.5
pF
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Rev. C
04/02/09
Note
5
IS42S83200C
IS42S16160C
DC CHARACTERISTICS
o
o
Recommended operating conditions (Voltage referenced to VSS = 0V, Commerical grade:TA = 0 to 70 C, Industrial grade:TA = -40 to 85 C)
Version
Organization
Parameter
Symbol
Test Condition
Unit
Note
-6
-7
-75
Operating Current
(One Bank Active)
Precharge Standby
Current in
power-down mode
Precharge Standby
Current
in non power-down
mode
Active Standby
Current
in power-down mode
Active Standby
Current
in non power-down
mode
(One Bank Active)
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
X8
Burst length = 1
tRC
t RC(min)
IO = 0 mA
CKE
140
130
mA
X 16
V IL(max), t CC = 10ns
CKE & CLK
140
VIL(max), t CC =
V IH(min),
CKE
VIH(min), CS
tCC = 10ns
Input signals are changed one
time during 20ns
CKE
VIH(min), CLK
VIL(max), t CC =
Input signals are stable
140
140
X 8 / X 16
15
15
X 8 / X 16
5
5
X 8 / X 16
40
40
135
15
mA
5
40
mA
X 8 / X 16
30
X 8 / X 16
50
50
50
X 8 / X 16
20
20
20
CKE
VIH(min), CS
V IH(min),
tCC = 10ns
Input signals are changed one
time during 20ns
X 8 / X 16
65
65
65
CKE
V IH(min), CLK
VIL(max), t CC =
Input signals are stable
X 8 / X 16
45
45
45
X 8 / X 16
180
180
180
185
CKE
V IL(max), t CC = 10ns
CKE & CLK
VIL(max), t CC =
1
30
30
mA
mA
Operating Current
(Burst Mode)
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
Refresh Current
ICC5
t ARFC
t ARFC(min)
X 8 / X 16
210
Self Refresh Current
ICC6
CKE
0.2V
X 8 / X 16
6
6
mA
175
mA
6
mA
1
2
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
6
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Rev. C
04/02/09
IS42S83200C
IS42S16160C
AC OPERATING TEST CONDITIONS(VDD = 3.3V, Commerical grade:TA = 0 to 70 C, Industrial grade:TA = -40 to 85 C)
o
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4 / 0.4
V
1.4
V
tr/tf = 1/1
Ns
1.4
V
See Figure 2
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Rev. C
04/02/09
o
7
IS42S83200C
IS42S16160C
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Unit
Note
Symbol
-6
-7
-75
Row active to row active delay
tRRD(min)
12
14
15
ns
1
RAS to CAS delay
tRCD(min)
18
20
20
ns
1
tRP(min)
18
20
20
ns
1
tRAS(min)
42
45
45
ns
1
tRAS(max)
100K
100K
100K
ns
tRC(min)
60
63
65
ns
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
tRDL (min)
2
2
2
CLK
Last data in to active delay
tDAL (min)
5
5
5
CLK
Last data in to new col. address delay
tCDL (min)
1
1
1
CLK
Last data in to burst stop
tDBL (min)
1
1
1
CLK
Mode register set cycle time
tMRD (min)
2
2
2
CLK
R e fre sh in te rva l tim e
tREF(max)
64
64
64
ms
Auto refresh cycle time
t ARFC(min)
60
70
75
ns
1
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
8
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Rev. C
04/02/09
IS42S83200C
IS42S16160C
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
Parameter
Symbol
-6
Min
-7
Max
Min
-75
Max
Min
CAS latency=3
tCC (3)
6
7
75
CAS latency=2
tCC (2)
10
10
10
CAS latency=3
tSAC (3)
Max
CLK cycle time
5.4
5.4
Unit
Note
ns
1
ns
1,2
ns
2
5.4
CLK to valid output delay
CAS latency=2
tSAC (2)
CAS latency=3
tOH (3)
CAS latency=2
tOH (2)
2.5
2.5
CLK high pulse width
tCH
2.5
2.5
2.5
ns
3
CLK low pulse width
tCL
2.5
2.5
2.5
ns
3
Input setup time
tSI
1.5
ns
3
Input hold time
tHI
1.0
ns
3
Transition time of CLK
tT
0.3
6
2.5
6
2.5
6
2.5
Output data hold time
CAS latency=3
CLK to output in Hi-Z
2.5
1.5
1.5
1.0
1.5
0.3
1.0
1.5
0.3
1.5
5.4
5.4
5.4
6
6
6
tSHZ
CAS latency=2
ns
ns
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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Rev. C
04/02/09
9
IS42S83200C
IS42S16160C
TRUTH TABLE
Command Truth Table
X
X
X
V
V
V
V
V
V
X
L
L
A10/
AP
X
X
X
L
H
L
H
V
L
H
L
L
A12-11,
A9 ~ A0
X
X
X
V
V
V
V
V
X
X
X
V
/CAS
X
X
X
L
L
H
X
H
H
X
H
X
X
/WE
X
X
X
H
H
H
X
L
H
X
H
X
X
/Address
X
X
X
X
X
X
X
X
X
X
X
X
X
COMMAND
Symbol
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
BA1
BA0
Device deselect
No operation
Burst stop
Read
Read with auto precharge
Write
Write with auto precharge
Bank activate
Precharge select bank
Precharge all banks
Mode register set
Extended mode register set
DSL
NOP
BST
RD
RDA
WR
WRA
ACT
PRE
PALL
MRS
EMRS
H
H
H
H
H
H
H
H
H
H
H
H
X
X
H
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
L
X
H
H
L
L
L
L
H
H
H
L
L
X
H
L
H
H
L
L
H
L
L
L
L
X
X
X
V
V
V
V
V
V
X
L
H
(V=Valid, X=Don
t Care, H=Logic High, L=Logic Low)
CKE Truth Table
Current state
Activating
Any
Clock suspend
Idle
Idle
Idle
Function
Clock suspend mode entry
Clock suspend mode
Clock suspend mode exit
Auto refresh command
Self refresh entry
Power down entry
Symbol
Idle
Self refresh
Deep power down entry
Self refresh exit
DPD
Power down
Power down exit
Deep power down
(V=Valid, X=Don
10
Deep power down exit
t Care, H=Logic High, L=Logic Low)
REF
SREF
PD
CKEn-1
H
L
L
H
H
H
H
H
L
L
L
L
L
CKEn
L
L
H
H
L
L
L
L
H
H
H
H
H
/CS
X
X
X
L
L
L
H
L
L
H
L
H
X
/RAS
X
X
X
L
L
H
X
H
H
X
H
X
X
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Rev. C
04/02/09
IS42S83200C
IS42S16160C
Function Truth Table
Current state
Idle
Row active
Read
Write
Read with auto
precharge
Write with auto
precharge
/CS
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
/RAS
X
H
H
H
H
L
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
/CAS
X
H
H
L
L
H
H
L
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
/WE
X
H
L
H
L
H
L
H
L
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
/Address
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
OC,BA1=H
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
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Rev. C
04/02/09
Command
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS
EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
Action
NOP
NOP
NOP
ILLEGAL
ILLEGAL
Row activating
NOP
Auto refresh
Mode register set
Extended mode register set
NOP
NOP
NOP
Begin read
Begin write
ILLEGAL
Precharge / Precharge all banks
ILLEGAL
ILLEGAL
Continue burst to end
Row active
Continue burst to end
Row active
Burst stop
Row active
Terminate burst,begin new read
Terminate burst,begin write
ILLEGAL
Terminate burst
Precharging
ILLEGAL
ILLEGAL
Continue burst to end
Write recovering
Continue burst to end
Write recovering
Burst stop
Row active
Terminate burst, start read : Determine AP
Terminate burst,new write : Determine AP
ILLEGAL
Terminate burst
Precharging
ILLEGAL
ILLEGAL
Continue burst to end
Precharging
Continue burst to end
Precharging
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue burst to end
Write recovering
Continue burst to end
Write recovering
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
1
1
2
2
1
3
4
4,5
1
4,5
4
1
6
1
1
1
1
1
1
1
1
11
IS42S83200C
IS42S16160C
Current state
Precharging
Row activating
Write
recovering
Write
recovering with
auto precharge
Refresh
Mode register
accessing
12
/CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
/RAS
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
/CAS
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
/WE
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
/Address
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
MODE
Command
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS/EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS
Action
Nop
Enter idle after tRP
Nop
Enter idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Enter idle after tRP
ILLEGAL
ILLEGAL
Nop
Enter bank active after tRCD
Nop
Enter bank active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Enter row active after tDPL
Nop
Enter row active after tDPL
Nop
Enter row active after tDPL
Begin read
Begin new write
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Enter precharge after tDPL
Nop
Enter precharge after tDPL
Nop
Enter precharge after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Enter idle after tRC1
Nop
Enter idle after tRC1
Nop
Enter idle after tRC1
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Enter idle after tRSC
Nop
Enter idle after tRSC
Nop
Enter idle after tRSC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
1
1
1
1
1
1,7
1
5
1
1
1,5
1
1
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Rev. C
04/02/09
IS42S83200C
IS42S16160C
Notes: 1. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on
the state of that bank.
2. Illegal if tRCD is not satisfied.
3. Illegal if tRAS is not satisfied.
4. Must satisfy burst interrupt condition.
5. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
6. Must mask preceding data which don't satisfy tDPL.
7. Illegal if tRRD is not satisfied
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IS42S83200C
IS42S16160C
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
Address
BA0
BA1
A12
A11
A10/AP
A9*2
A8
A7
Function
0
0
0
0
0
0
0
0
A6
A5
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
Normal MRS Mode
CAS Latency
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
Burst Type
A3
0
1
Type
Sequential
Interleave
Burst Length
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
BT=0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
BT=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
C. BURST SEQUENCE
BURST LENGTH
2
4
8
Full Page (y)
STARTING COLUMN
ADDRESS
A0
0
1
A1 A0
0 0
0 1
1 0
1 1
A2 A1 A0
0 0
0
0 0
1
0 1
0
0 1
1
1 0
0
1 0
1
1 1
0
1 1
1
N=A0 – A8
(location 0 – y)
ORDER OF ACCESSES WITHIN A BURST
TYPE=SEQUENTIAL
TYPE=INTERLEAVED
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2, Cn+3,
Cn+4..., …Cn-1, Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTE:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1–A8 select the block-of-two burst; A0 selects the starting column within the block.
3. For a burst length of four, A2–A8 select the block-of-four burst; A0–A1 select the starting column within the block.
4. For a burst length of eight, A3–A8 select the block-of-eight burst; A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7. For a burst length of one, A0–A8 select the unique column to be accessed, and mode register bit M3 is ignored.
14
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Rev. C
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IS42S83200C
IS42S16160C
Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If the sepins go high
before power up, the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the precharge
command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS)
to initialize the mode register. We recommend that by keeping DQM and CKE to High, the output buffer becomes High-Z
during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device.
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IS42S83200C
IS42S16160C
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank
active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write
command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after
read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the
bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks
specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive
burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
16
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Write operation
Burst write or single write mode is selected
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock
as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read
operations. The write start address is specified by the column address and the bank select address at the write command
set cycle.
.
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is
only written to the column address and the bank select address specified by the write command set cycle without regard to
the burst length setting. (The latency of data input is 0 clock).
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IS42S83200C
IS42S16160C
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
3
2
Precharge start cycle
2 cycle before the final data is output
1 cycle before the final data is output
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation, a
precharge command need not be executed after each write operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is required between the
final valid data input and input of next command.
18
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IS42S83200C
IS42S16160C
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to
High-Z after the /CAS latency from the burst stop command.
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to
High-Z at the same clock with the burst stop command.
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IS42S83200C
IS42S16160C
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank
as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock.
Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands
cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. Even when the first command is a burst read that is not yet finished,
the data read by the second command will be valid.
20
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IS42S83200C
IS42S16160C
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank
as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of
burst writes, the second write command has priority.
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;
it is necessary to separate the two write commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.
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IS42S83200C
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Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as
the preceding read command, the write command can be performed after an interval of no less than 1 clock. However,
UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input.
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;
it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle,
provided that the other bank is in the bank active state. However, UDQM and LDQM must be set High so that the output
buffer becomes High-Z before data input.
22
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Rev. C
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IS42S83200C
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Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as
the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in
the case of a burst write, data will continue to be written until one clock before the read command is executed.
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed;
it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be
written until one clock before the read command is executed (as in the case of the same bank and the same address).
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IS42S83200C
IS42S16160C
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even
when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is
valid. The internal auto-precharge of one bank starts at the next clock of the second command.
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the
case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts 2 clocks later
from the second command.
2. Same bank: The consecutive write command (the same bank) is illegal.
24
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IS42S83200C
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Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However,
UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input. The internal
auto-precharge of one bank starts at the next clock of the second command.
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to
separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However,
in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal
auto-precharge of one bank starts at 2 clocks later from the second command.
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to
separate the two commands with a bank active command.
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IS42S83200C
IS42S16160C
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval
between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by
lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during
burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output
to precharge command execution.
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IS42S83200C
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Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval
between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by
means of UDQM and LDQM for assurance of the clock defined by tDPL.
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IS42S83200C
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Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no less than
tRRD.
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
28
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DQM Control
The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and LDQM is
different during reading and writing.
Reading
When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low, the output
buffer becomes Low-Z, enabling data output. By setting UDQM and LDQM to High, the output buffer becomes High-Z, and
the corresponding data is not output. However, internal reading operations continue. The latency of UDQM and LDQM
during reading is 2 clocks.
Writing
Input data can be masked by UDQM and LDQM. By setting DQM to Low, data can be written. In addition, when UDQM and
LDQM are set to High, the corresponding data is not written, and the previous data is held. The latency of UDQM and LDQM
during writing is 0 clock.
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IS42S83200C
IS42S16160C
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the
internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external
address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.).
The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not required.
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh
operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit
command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period
on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh
addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from
self-refresh mode.
Note: tREF (max.) / refresh cycles.
Others
Power-down mode
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is
suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting
CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode,
internal refresh is not performed.
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During clock
suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the
SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE
Truth Table".
30
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IS42S83200C
IS42S16160C
Timing Waveforms
Read Cycle
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IS42S83200C
IS42S16160C
Write Cycle
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IS42S16160C
Mode Register Set Cycle
Read Cycle/Write Cycle
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Rev. C
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IS42S83200C
IS42S16160C
Read/Single Write Cycle
34
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Rev. C
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IS42S83200C
IS42S16160C
Read/Burst Write Cycle
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IS42S83200C
IS42S16160C
Auto Refresh Cycle
Self Refresh Cycle
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Rev. C
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IS42S16160C
Clock Suspend Mode
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IS42S83200C
IS42S16160C
Power Down Mode
Initialization Sequence
38
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IS42S83200C
IS42S16160C
ORDERING INFORMATION: VDD = 3.3V
o
o
Commercial Range: 0 C to +70 C
Frequency
166 MHz
143 MHz
133 MHz
Speed (ns)
6
7
7.5
Order Part No.
IS42S83200C-6TL
IS42S83200C-7TL
IS42S83200C-75TL
Package
54-pin TSOP-II, Lead-free
54-pin TSOP-II, Lead-free
54-pin TSOP-II, Lead-free
Frequency
166 MHz
143 MHz
133 MHz
Speed (ns)
6
7
7.5
Order Part No.
IS42S16160C-6TL
IS42S16160C-7TL
IS42S16160C-75TL
Package
54-pin TSOP-II, Lead-free
54-pin TSOP-II, Lead-free
54-pin TSOP-II, Lead-free
o
o
Industrial Range: -40 C to +85 C
Frequency
166 MHz
143 MHz
133 MHz
Speed (ns)
6
7
7.5
Order Part No.
IS42S16160C-6TLI
IS42S16160C-7TLI
IS42S16160C-75TLI
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
04/02/09
Package
54-pin TSOP-II, Lead-free
54-pin TSOP-II, Lead-free
54-pin TSOP-II, Lead-free
39