TI1 ADS7049QDCURQ1 Ads7049-q1 small-size, low-power, 12-bit, 2-msps, sar adc Datasheet

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ADS7049-Q1
SBAS763 – NOVEMBER 2016
ADS7049-Q1 Small-Size, Low-Power, 12-Bit, 2-MSPS, SAR ADC
1 Features
2 Applications
•
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1
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±2000 V
– Device CDM ESD Classification Level ±1000 V
Ultra-Low Power Consumption:
– 1.38 mW (max) at 2 MSPS with 3-V AVDD
– Less Than 1 µW at 1 kSPS with 3-V AVDD
Miniature Footprint:
– 8-Pin VSSOP Package: 2.30 mm × 2.00 mm
2-MSPS Throughput with Zero Data Latency
Wide Operating Range:
– AVDD: 2.35 V to 3.6 V
– DVDD: 1.65 V to 3.6 V (Independent of AVDD)
– Temperature Range: –40°C to +125°C
Excellent Performance:
– 12-Bit Resolution with NMC
– ±0.5 LSB DNL; ±0.5 LSB INL
– 70-dB SNR with 3-V AVDD
– –80-dB THD with 3-V AVDD
Unipolar Input Range: 0 V to AVDD
Integrated Offset Calibration
SPI-Compatible Serial Interface: 32 MHz
JESD8-7A Compliant Digital I/O
Automotive Infotainment
Automotive Sensors
Level Sensors
Ultrasonic Flow Meters
Motor Control
Portable Medical Equipment
3 Description
The ADS7049-Q1 device is a an automotive Q100qualified, 12-bit, 2-MSPS, analog-to-digital converter
(ADC). The device supports a wide analog input
voltage range (2.35 V to 3.6 V) and includes a
capacitor-based, successive-approximation register
(SAR) ADC with an inherent sample-and-hold circuit.
The SPI-compatible serial interface is controlled by
the CS and SCLK signals. The input signal is
sampled with the CS falling edge and SCLK is used
for conversion and serial data output. The device
supports a wide digital supply range (1.65 V to 3.6 V),
enabling direct interface to a variety of host
controllers. The ADS7049-Q1 complies with the
JESD8-7A standard for a normal DVDD range
(1.65 V to 1.95 V).
The ADS7049-Q1 is available in an 8-pin, miniature,
VSSOP package and is specified for operation from
–40°C to +125°C. The fast sampling rate of the
ADS7049-Q1, along with miniature form-factor and
low-power consumption, makes this device suitable
for space-constrained and fast-scanning automotive
applications.
Device Information(1)
PART NAME
ADS7049-Q1
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
2.30 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
AVDD
AVDD used as Reference for
device
OPA_AVDD
R
+
VIN+
AVDD
AINP
+
±
C
ADS7049-Q1
AINM
GND
OPA_AVSS
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7049-Q1
SBAS763 – NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 12
8
Detailed Description ............................................ 12
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 23
10.1 AVDD and DVDD Supply Recommendations....... 23
10.2 Estimating Digital Power Consumption................. 23
10.3 Optimizing Power Consumed by the Device ........ 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
7.1 Digital Voltage Levels ............................................. 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
2
DATE
REVISION
NOTES
November 2016
*
Initial release.
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5 Pin Configuration and Functions
DCU Package
8-Pin Leaded VSSOP
Top View
DVDD
1
8
GND
SCLK
2
7
AVDD
SDO
3
6
AINP
CS
4
5
AINM
Not to scale
Pin Functions
NAME
NO.
I/O
DESCRIPTION
AINM
5
Analog input
Analog signal input, negative
AINP
6
Analog input
Analog signal input, positive
AVDD
7
Supply
CS
4
Digital input
DVDD
1
Supply
Digital I/O supply voltage
GND
8
Supply
Ground for power supply, all analog and digital signals are referred to this pin
SCLK
2
Digital input
SDO
3
Digital output
Analog power-supply input, also provides the reference voltage to the ADC
Chip-select signal, active low
Serial clock
Serial data out
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
AVDD to GND
–0.3
3.9
V
DVDD to GND
–0.3
3.9
V
AINP to GND
–0.3
AVDD + 0.3
V
AINM to GND
–0.3
0.3
V
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Storage temperature, Tstg
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
Analog supply voltage range
2.35
3.6
DVDD
Digital supply voltage range
1.65
3.6
V
V
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
ADS7049-Q1
THERMAL METRIC
(1)
DCU (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
181.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.8
°C/W
RθJB
Junction-to-board thermal resistance
73.9
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
73.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 2 MSPS, and VAINM = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input
voltage range
CS
0
AVDD
AINP to GND
–0.1
AVDD + 0.1
AINM to GND
–0.1
0.1
Sampling capacitance
V
15
pF
12
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
12
INL
Integral nonlinearity
AVDD = 3 V
–1
±0.5
1
LSB (2)
DNL
Differential nonlinearity
AVDD = 3 V
–0.99
±0.5
1
LSB
EO
Offset error
AVDD = 3 V
–3
±0.5
dVOS/dT
Offset error drift with temperature
EG
Gain error
AVDD = 3 V
–0.1
±0.05
Gain error drift with temperature
No calibration
Uncalibrated
Calibrated (3)
Bits
±12
3
±5
LSB
ppm/°C
0.1
±2
%FS
ppm/°C
SAMPLING DYNAMICS
tACQ
Acquisition time
Maximum throughput rate
90
ns
32-MHz SCLK, AVDD = 2.35 V to 3.6 V
2
MHz
DYNAMIC CHARACTERISTICS
SNR
Signal-to-noise ratio (4)
fIN = 2 kHz, AVDD = 3 V
THD
Total harmonic distortion (4) (5)
fIN = 2 kHz, AVDD = 3 V
SINAD
Signal-to-noise and distortion (4)
fIN = 2 kHz, AVDD = 3 V
SFDR
Spurious-free dynamic range (4)
fIN = 2 kHz, AVDD = 3 V
80
dB
BW(fp)
Full-power bandwidth
At –3 dB, AVDD = 3 V
25
MHz
68
67.5
70
dB
–80
dB
69.5
dB
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
High-level input voltage (6)
0.65 × DVDD
DVDD + 0.3
V
VIL
Low-level input voltage (6)
–0.3
0.35 × DVDD
V
0.8 × DVDD
DVDD
At Isource = 2 mA
DVDD – 0.45
DVDD
At Isink = 500 µA
0
0.2 × DVDD
At Isink = 2 mA
0
0.45
VOH
High-level output voltage (6)
VOL
Low-level output voltage (6)
At Isource = 500 µA
V
V
POWER-SUPPLY REQUIREMENTS
AVDD
Analog supply voltage
2.35
3
3.6
DVDD
Digital I/O supply voltage
1.65
3
3.6
V
IAVDD
Analog supply current
At 2 MSPS with AVDD = 3 V
380
460
µA
IDVDD
Digital supply current
AVDD = 3 V, no load, no transitions
PD
Power dissipation
At 2 MSPS with AVDD = 3 V
1.38
mW
(1)
(2)
(3)
(4)
(5)
(6)
10
1.14
V
µA
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
See the Offset Calibration section for more details.
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified.
Calculated on the first nine harmonics of the input frequency.
Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Digital Voltage Levels section for
more details.
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6.6 Timing Requirements
all specifications are at TA = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF
(unless otherwise specified)
MIN
TYP
MAX
UNIT
tACQ
Acquisition time
90
ns
fSCLK
SCLK frequency
0.016
tSCLK
SCLK period
31.25
tPH_CK
SCLK high time
tPL_CK
SCLK low time
tPH_CS
CS high time
30
ns
tSU_CSCK
Setup time: CS falling to SCLK falling
12
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
10
ns
32
MHz
0.45
0.55
tSCLK
0.45
0.55
tSCLK
ns
6.7 Switching Characteristics
all specifications are at TA = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF
(unless otherwise specified)
PARAMETER
fTHROUGHP
TEST CONDITIONS
MIN
TYP
Throughput
MAX
UNIT
2
MSPS
UT
tCYCLE
Cycle time
tCONV
Conversion time
0.5
tDV_CSDO
Delay time: CS falling to data enable
tD_CKDO
Delay time: SCLK falling to (next)
data valid on DOUT
tDZ_CSDO
Delay time: CS rising to DOUT going
to tri-state
µs
12.5 × tSCLK + tSU_CSCK
ns
10
ns
25
ns
AVDD = 2.35 V to 3.6 V
5
ns
Sample
N
Sample
N+1
tCYCLE
tCONV
tACQ
tPH_CS
CS
tSU_CSCK
SCLK
1
2
tDV_CSDO
SDO
0
0
tPH_CK
3
4
5
tPL_CK
6
7
8
9
10
11
12
tD_CKDO
D11
D10
tD_CKCS
tSCLK
13
14
tDZ_CSDO
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data for Sample N
Figure 1. Timing Diagram
6
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6.8 Typical Characteristics
0
0
-20
-20
-40
-40
-60
-60
Amplitude (dB)
Amplitude (dB)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
-80
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
0
200
400
600
Frequency (kHz)
800
0
1000
200
400
600
Frequency (kHz)
D001
SNR = 70.29 dB, THD = –84.04 dB, fIN = 2 kHz,
number of samples = 65536
D002
Figure 3. Typical FFT
73
72.5
72.5
72
72
71.5
71.5
SNR, SINAD (dB)
SNR, SINAD (dB)
Figure 2. Typical FFT
71
70.5
70
69.5
69
68
-40
1000
SNR = 69.92 dB, THD = –80.05 dB, fIN = 250 kHz,
number of samples = 65536
73
68.5
800
71
70.5
70
69.5
69
SNR
SINAD
SNR
SINAD
68.5
68
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
0
25
50
75
D003
100 125 150 175
Input Frequency (Hz)
200
225
250
D004
fIN = 2 kHz
Figure 4. SNR and SINAD vs Temperature
Figure 5. SNR and SINAD vs Input Frequency
-75
73
72.5
SNR
SINAD
-78
71
THD (dB)
SNR, SINAD (dB)
72
71.5
70.5
70
-81
-84
69.5
-87
69
68.5
68
2.2
2.4
2.6
2.8
3
3.2
Reference Voltage (V)
3.4
3.6
3.8
-90
-40
-25
D005
fIN = 2 kHz
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D006
fIN = 2 kHz
Figure 6. SNR and SINAD vs Reference Voltage (AVDD)
Figure 7. THD vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
95
-75
-78
THD (dB)
SFDR (dB)
90
85
-81
-84
80
-87
75
-40
-90
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
0
30
60
D007
90
120 150 180
Input Frequency (kHz)
210
240
270
D008
fIN = 2 kHz
Figure 8. SFDR vs Temperature
Figure 9. THD vs Input Frequency
-75
96
93
-78
THD (dB)
SFDR (dB)
90
87
84
-81
-84
81
-87
78
-90
2.2
75
0
30
60
90
120 150 180
Input Frequency (kHz)
210
240
270
2.4
D009
2.6
2.8
3
3.2
Reference Voltage (V)
3.4
3.6
3.8
D010
fIN = 2 kHz
Figure 10. SFDR vs Input Frequency
Figure 11. THD vs Reference Voltage (AVDD)
95
180000
150000
Number of Hits
SFDR (dB)
90
85
120000
90000
60000
80
30000
75
2.2
0
2.4
2.6
2.8
3
3.2
Reference Voltage (V)
3.4
3.6
3.8
2045
D011
fIN = 2 kHz
2047
2048
Code
2049
D012
Mean code = 2046.92, sigma = 0.42
Figure 12. SFDR vs Reference Voltage (AVDD)
8
2046
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Figure 13. DC Input Histogram
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
5
0
4
-0.5
3
Offset (mV), No Callibration
Offset (mV), With Callibration
2
Offset (mV)
Offset (mV)
-1
-1.5
-2
1
0
-1
-2
-2.5
-3
-3
Offset (mV), No Callibration
Offset (mV), With Callibration
-4
-3.5
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
-5
2.2
110 125
0.025
0.025
0
-0.025
2.8
3
3.2
Reference Voltage (V)
3.4
3.6
D014
0
-0.025
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
-0.05
2.2
110 125
2.4
2.6
D015
Figure 16. Gain Error vs Temperature
2.8
3
3.2
Reference Voltage (V)
3.4
3.6
3.8
D016
Figure 17. Gain Error vs Reference Voltage (AVDD)
1
1
0.75
0.75
0.5
0.5
0.25
0.25
INL (LSB)
DNL (LSB)
2.6
Figure 15. Offset vs Reference Voltage (AVDD)
0.05
Gain ( FS)
Gain ( FS)
Figure 14. Offset vs Temperature
0.05
-0.05
-40
2.4
D013
0
-0.25
0
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1
0
512
1024
1536
2048
Code
2560
3072
3584
4096
0
512
D017
AVDD = 3 V
1024
1536
2048
Code
2560
3072
3584
4096
D018
AVDD = 3 V
Figure 18. Typical DNL
Figure 19. Typical INL
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
1
1
Maximum
Minimum
0.5
0.5
0.25
0.25
0
-0.25
0
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
Maximum
Minimum
0.75
DNL (LSB)
DNL (LSB)
0.75
-1
2.2
110 125
Figure 20. DNL vs Temperature
2.6
2.8
3
3.2
Reference Voltage (V)
3.4
3.6
D022
Figure 21. DNL vs Reference Voltage (AVDD)
1
1
Maximum
Minimum
0.75
0.75
0.5
0.5
0.25
0.25
INL (LSB)
INL (LSB)
2.4
D021
0
-0.25
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
Maximum
Minimum
0
-1
2.2
110 125
2.4
D023
Figure 22. INL vs Temperature
2.6
2.8
3
3.2
Reference Voltage (V)
3.4
3.6
D024
Figure 23. INL vs Reference Voltage (AVDD)
0.45
0.5
0.4
0.35
Current (mA)
Current (mA)
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0.3
-40
0
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
400
0
D025
800
1200
Throughput (kSPS)
1600
2000
D026
fSample = 2 MSPS
Figure 24. AVDD Supply Current vs Temperature
10
Figure 25. AVDD Supply Current vs Throughput
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
500
0.475
450
0.45
350
0.4
300
Current (nA)
Current (mA)
400
0.425
0.375
0.35
250
200
150
100
0.325
50
0.3
0
0.275
2.2
2.4
2.6
2.8
3
3.2
Supply Voltage (V)
3.4
-50
-40
3.6
-25
-10
D027
5
20 35 50 65
Temperature (qC)
80
95
110 125
D028
fSample = 2 MSPS
Figure 26. AVDD Supply Current vs Supply Voltage
Figure 27. AVDD Static Current vs Temperature
12
11.9
11.8
11.6
SNR (dB)
ENOB
11.7
11.5
11.4
11.3
11.2
11.1
11
0
200
400
600 800 1000 1200 1400 1600 1800 2000
Sampling Rate (kSPS)
D029
73
72
71
70
69
68
67
66
65
64
63
62
61
60
0
200
400
fIN = 2 kHz
fIN = 2 kHz
Figure 28. ENOB vs Sampling Rate
Figure 29. SNR vs Sampling Rate
75
-75
72
-78
69
-81
THD (dB)
SINAD (dB)
600 800 1000 1200 1400 1600 1800 2000
Sampling Rate (kSPS)
D030
66
63
-84
-87
60
-90
0
200
400
600 800 1000 1200 1400 1600 1800 2000
Sampling Rate (kSPS)
D031
0
200
fIN = 2 kHz
400
600 800 1000 1200 1400 1600 1800 2000
Sampling Rate (kSPS)
D032
fIN = 2 kHz
Figure 30. SINAD vs Sampling Rate
Figure 31. THD vs Sampling Rate
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7 Parameter Measurement Information
7.1 Digital Voltage Levels
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 32 shows voltage
levels for the digital input and output pins.
Digital Output
DVDD
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
ISource= 2 mA, ISink = 2 mA,
DVDD = 1.65 V to 1.95 V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK
0.35DVDD
-0.3V
VIL
DVDD = 1.65 V to 1.95 V
Figure 32. Digital Voltage Levels as per the JESD8-7A Standard
8 Detailed Description
8.1 Overview
The ADS7049-Q1 is an ultra-low-power, miniature analog-to-digital converter (ADC) that supports a wide analog
input range. The analog input range for the device is defined by the AVDD supply voltage. The device samples
the input voltage across the AINP and AINM pins on the CS falling edge and starts the conversion. The clock
provided on the SCLK pin is used for conversion and data transfer. During conversions, both the AINP and AINM
pins are disconnected from the sampling circuit. After the conversion completes, the sampling capacitors are
reconnected across the AINP and AINM pins and the ADS7049-Q1 enters acquisition phase.
The device has an internal offset calibration. The offset calibration can be initiated by the user either on power-up
or during normal operation; see the Offset Calibration section for more details.
The device also provides a simple serial interface to the host controller and operates over a wide range of digital
power supplies. The ADS7049-Q1 requires only a 32-MHz SCLK for supporting a throughput of 2 MSPS. The
digital interface also complies with the JESD8-7A (normal range) standard. The Functional Block Diagram
section provides a block diagram of the device.
12
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8.2 Functional Block Diagram
AVDD
DVDD
GND
Offset
Calibration
AINP
CS
CDAC
Comparator
AINM
±
SCLK
Serial
Interface
SDO
SAR
8.3 Feature Description
8.3.1 Reference
The device uses the analog supply voltage (AVDD) as a reference, as shown in Figure 33. The AVDD pin is
recommended to be decoupled with a 3.3-µF, low equivalent series resistance (ESR) ceramic capacitor.. The
AVDD pin functions as a switched capacitor load to the source powering AVDD. The decoupling capacitor
provides the instantaneous charge required by the internal circuit and helps in maintaining a stable dc voltage on
the AVDD pin. The AVDD pin is recommended to be powered with a low output impedance and low-noise
regulator (such as the TPS73230).
3.3 µF
AVDD
DVDD
GND
Offset
Calibration
AINP
CS
CDAC
Comparator
AINM
±
SCLK
Serial
Interface
SDO
SAR
Figure 33. Reference for the Device
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Feature Description (continued)
8.3.2 Analog Input
The device supports single-ended analog inputs. The ADC samples the difference between AINP and AINM and
converts for this voltage. The device is capable of accepting a signal from –100 mV to 100 mV on the AINM input
and is useful in systems where the sensor or signal-conditioning block is far from the ADC. In such a scenario,
there can be a difference between the ground potential of the sensor or signal conditioner and the ADC ground.
In such cases, use separate wires to connect the ground of the sensor or signal conditioner to the AINM pin. The
AINP input is capable of accepting signals from 0 V to AVDD. Figure 34 represents the equivalent analog input
circuits for the sampling stage. The device has a low-pass filter followed by the sampling switch and sampling
capacitor. The sampling switch is represented by an RS (typically 50 Ω) resistor in series with an ideal switch and
CS (typically 15 pF) is the sampling capacitor. The ESD diodes are connected from both analog inputs to AVDD
and ground.
AVDD
Rs
50
AINP
CS
15 pF
AVDD
50
RS
AINM
CS
Figure 34. Equivalent Input Circuit for the Sampling Stage
The analog input full-scale range (FSR) is equal to the reference voltage of the ADC. The reference voltage for
the device is equal to the analog supply voltage (AVDD). Thus, the device FSR can be determined by
Equation 1:
FSR = VREF = AVDD
14
(1)
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Feature Description (continued)
8.3.3 ADC Transfer Function
The device output is in straight binary format. The device resolution for a single-ended input can be computed by
Equation 2:
1 LSB = VREF / 2N
where:
•
•
VREF = AVDD and
N = 12
(2)
Figure 35 and Table 1 show the ideal transfer characteristics for the device.
ADC Code (Hex)
PFSC
MC + 1
MC
NFSC+1
NFSC
VREF
2
1 LSB
VIN
V REF
2
VREF ± 1 LSB
1LSB
Single-Ended Analog Input
(AINP ± AINM)
Figure 35. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE (AINP – AINM)
CODE
DESCRIPTION
IDEAL OUTPUT CODE
≤1 LSB
NFSC
Negative full-scale code
000
1 LSB to 2 LSBs
NFSC + 1
—
001
800
(VREF / 2) to (VREF / 2) + 1 LSB
MC
Mid code
(VREF / 2) + 1 LSB to (VREF / 2) + 2 LSBs
MC + 1
—
801
≥ VREF – 1 LSB
PFSC
Positive full-scale code
FFF
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8.3.4 Serial Interface
The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one
conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The
SDO pin outputs the ADC conversion results. Figure 36 shows a detailed timing diagram for the serial interface.
A minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The
device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is
available on the SDO pin with the first two bits set to 0, followed by 12 bits of the conversion result. The first zero
is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the
conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains
low after 14 SCLKs. A CS rising edge ends the frame and brings the serial data bus to tri-state. For acquisition of
the next sample, a minimum time of tACQ must be provided after the conversion of the current sample is
completed. For details on timing specifications, see the Timing Requirements table.
The device initiates an offset calibration on the first CS falling edge after power-up and the SDO output remains
low during the first serial transfer frame after power-up. For further details, see the Offset Calibration section.
Sample
N
Sample
N+1
tCYCLE
tCONV
tACQ
CS
SCLK
1
SDO
0
2
0
3
D11
4
5
6
7
8
9
10
11
12
D10
D9
D8
D7
D6
D5
D4
D3
D2
13
D1
14
D0
Data for Sample N
Figure 36. Serial Interface Timing Diagram
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8.4 Device Functional Modes
8.4.1 Offset Calibration
The ADS7049-Q1 includes a feature to calibrate the device internal offset. During offset calibration, the analog
input pins (AINP and AINM) are disconnected from the sampling stage. The device includes an internal offset
calibration register (OCR) that stores the offset calibration result. The OCR is an internal register and cannot be
accessed by the user through the serial interface. The OCR is reset to zero on power-up. Therefore, it is
recommended to calibrate the offset on power-up in order to bring the offset error within the specified limits. If the
operating temperature or analog supply voltage reflect a significant change, the offset can be recalibrated during
normal operation. Figure 37 shows the offset calibration process.
)
(4
cle
Po
Re
cy
th
Device
Power Up
Ca
lib
r
SDatio
O no
= nP
0x o
00 w e
0 rU
p
Data Capture(1)
Calibration during Normal operation(2)
wi
e
am s
r
r F LK
sfe SC
an 16 000
r
l T n 0x
ria tha =
Se ess DO
t
l
S
rs
Fi
r
we
Normal Operation
With Uncalibarted
offset
(3
)
Po
:
we
rR
Data Capture(1)
ec
yc
le
(4
)
Normal Operation
With Calibarted
offset
Calibration during Normal Operation(2)
(1)
See the Timing Requirements section for timing specifications.
(2)
See the Offset Calibration During Normal Operation section for details.
(3)
See the Offset Calibration on Power-Up section for details.
(4)
The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up
state.
Figure 37. Offset Calibration
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Device Functional Modes (continued)
8.4.1.1 Offset Calibration on Power-Up
The device initiates offset calibration on the first CS falling edge after power-up and calibration completes if the
CS pin remains low for at least 16 SCLK falling edges after the first CS falling edge. The SDO output remains
low during calibration. The minimum acquisition time must be provided after calibration for acquiring the first
sample. If the device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up,
the OCR is not updated. Table 2 provides the timing parameters for offset calibration on power-up.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 38
shows the timing diagram for offset calibration on power-up.
Table 2. Offset Calibration on Power-Up
MIN
fCLK-CAL
SCLK frequency for calibration
tPOWERUP-CAL
Calibration time at power-up
tACQ
Acquisition time
tPH_CS
CS high time
tSU_CSCK
tD_CKCS
TYP
MAX
UNIT
16
MHz
15 × tSCLK
ns
90
ns
tACQ
ns
Setup time: CS falling to SCLK falling
12
ns
Delay time: last SCLK falling to CS rising
10
ns
Start
Power-up
Calibration
Sample
#1
tPH_CS
tPOWERUP-CAL
tACQ
CS
tD_CKCS
tSU_CSCK
SCLK(fCLK-CAL)
1
2
15
16
SDO
Figure 38. Offset Calibration on Power-Up Timing Diagram
18
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8.4.1.2 Offset Calibration During Normal Operation
Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in
one serial transfer frame. During the first 14 SCLKs, the device converts the sample acquired on the CS falling
edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling
edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 14th
SCLK falling edge and SDO goes to tri-state after CS goes high. If the device is provided with less than 32
SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset
calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output.
Figure 39 shows the timing diagram for offset calibration during normal operation.
Table 3. Offset Calibration During Normal Operation
MIN
fCLK-CAL
SCLK frequency for calibration
tCAL
Calibration time during normal operation
tACQ
Acquisition time
tPH_CS
CS high time
tSU_CSCK
tD_CKCS
TYP
MAX
UNIT
16
MHz
15 × tSCLK
ns
90
ns
tACQ
ns
Setup time: CS falling to SCLK falling
12
ns
Delay time: last SCLK falling to CS rising
10
ns
Sample
N+1
Sample
N
tPH_CS
tCONV
tCAL
tACQ
CS
tSU_CSCK
tD_CKCS
SCLK(fCLK-CAL)
1
2
3
4
13
SDO
0
0
D11
D10
D1
14
15
16
17
18
31
32
D0
Data for Sample N
Figure 39. Offset Calibration During Normal Operation Timing Diagram
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The two primary circuits required to maximize the performance of a SAR ADC are the input driver and the
reference driver circuits. This section details some general principles for designing the input driver circuit,
reference driver circuit, and provides some application circuits designed for the ADS7049-Q1.
9.2 Typical Application
OPA_VDD
AVDD
33
±
VDD
VIN
+
OPA365-Q1
+
VSOURCE
TI Device
±
1 nF
GND
GND
Device: 12-Bit , 2-MSPS,
Single-Ended Input
Input Driver
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Figure 40. Single-Supply DAQ with the ADS7049-Q1
9.2.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7049Q1 with SNR greater than 70 dB and THD less than –80 dB for input frequencies of 2 kHz at a throughput of
2 MSPS.
9.2.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a charge
kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
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Typical Application (continued)
9.2.2.1 Low Distortion Charge Kickback Filter Design
Figure 41 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and
connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input
pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this
transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched
capacitor load can create stability issues.
RF
Charge Kickback Filter
SAR ADC
RIN
VIN
-
RFLT
SW
+
CSH
VCM
CFLT
f-3dB =
1
2 Πx RFLT x CFLT
Figure 41. Charge Kickback Filter
For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby
increasing the SNR of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also
helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter
capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection
and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition
process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC
sampling capacitance. For this device, the input sampling capacitance is equal to 15 pF. Thus, the value of CFLT
is greater than 300 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, lowtemperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
The input amplifier bandwidth is typically much higher than the cutoff frequency of the antialiasing filter. Thus, a
SPICE simulation is strongly recommended to be performed to confirm that the amplifier has more than 40°
phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some
amplifiers can require more bandwidth than others to drive similar filters.
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Typical Application (continued)
9.2.2.2 Input Amplifier Selection
To achieve a SINAD greater than 70 dB, the operational amplifier must have high bandwidth in order to settle the
input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the
total system noise below 20% of the input-referred noise of the ADC. For the application circuit illustrated in
Figure 40, the OPA365-Q1 is selected for its high bandwidth (50 MHz) and low noise (4.5 nV/√Hz).
For a step-by-step design procedure for a low-power, small form-factor digital acquisition (DAQ) circuit based on
similar SAR ADCs, see the Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and
Ultra-Small Form Factor TI Precision Design.
9.2.2.3 Reference Circuit
The analog supply voltage of the device is also used as a voltage reference for conversion. The AVDD pin is
recommended to be decoupled with a 3.3-µF, low-ESR ceramic capacitor.
9.2.3 Application Curve
Figure 42 shows the FFT plot for the ADS7049-Q1 with a 2-kHz input frequency used for the circuit in Figure 40.
0
-20
Amplitude (dB)
-40
-60
-80
-100
-120
-140
-160
-180
0
200
400
600
Frequency (kHz)
800
1000
D001
SNR = 70.6 dB, THD = –86 dB, SINAD = 70.2 dB, number of samples = 32768
Figure 42. Test Results for the ADS7049-Q1 and OPA365-Q1 for a 2-kHz Input
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10 Power Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The ADS7049-Q1 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges. The AVDD supply also defines the full-scale input range of the device. Always set the AVDD supply to
be greater than or equal to the maximum input signal to avoid saturation of codes. Decouple the AVDD and
DVDD pins individually with 3.3-µF ceramic decoupling capacitors, as shown in Figure 43.
AVDD
AVDD
3.3 PF
GND
3.3 PF
DVDD
DVDD
Figure 43. Power-Supply Decoupling
10.2 Estimating Digital Power Consumption
The current consumption from the DVDD supply depends on the DVDD voltage, load capacitance on the SDO
line, and the output code. The load capacitance on the SDO line is charged by the current from the SDO pin on
every rising edge of the data output and is discharged on every falling edge of the data output. The current
consumed by the device from the DVDD supply can be calculated by Equation 3:
IDVDD = C × V × f
where:
•
•
•
C = Load capacitance on the SDO line
V = DVDD supply voltage and
f = Number of transitions on the SDO output
(3)
The number of transitions on the SDO output depends on the output code, and thus changes with the analog
input. The maximum value of f occurs when data output on SDO change at every SCLK. SDO data changing at
every SCLK results in an output code of AAAh or 555h. For an output code of AAAh or 555h at a 2-MSPS
throughput, the frequency of transitions on the SDO output is 12 MHz.
For the current consumption to remain at the lowest possible value, keep the DVDD supply at the lowest
permissible value and keep the capacitance on the SDO line as low as possible.
10.3 Optimizing Power Consumed by the Device
•
•
•
•
Keep the analog supply voltage (AVDD) as close as possible to the analog input voltage. Set AVDD to be
greater than or equal to the analog input voltage of the device.
Keep the digital supply voltage (DVDD) at the lowest permissible value.
Reduce the load capacitance on the SDO output.
Run the device at the optimum throughput. Power consumption reduces with throughput.
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11 Layout
11.1 Layout Guidelines
Figure 44 shows a board layout example for the ADS7049-Q1.
Some of the key considerations for an optimum layout with this device are:
• Use a ground plane underneath the device and partition the printed circuit board (PCB) into analog and digital
sections.
• Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference
input signals away from noise sources.
• The power sources to the device must be clean and well-bypassed. Use 2.2-μF ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins.
• Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors.
• Connect ground pins to the ground plane using short, low-impedance path.
• Place the fly-wheel RC filters components close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance
precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical
properties over voltage, frequency, and temperature changes.
11.2 Layout Example
GND
Digital
Pins
Analog
Pins
AINM
5
4
CS
6
3
SDO
2
SCLK
CFLT
AINP
RFLT
AVDD
7
ADS7049-Q1
2.2 …F
GND
8
1
DVDD
2.2 …F
GND
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Figure 44. Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• TPS732xx Capacitor-Free, NMOS, 250-mA Low-Dropout Regulator With Reverse Current Protection
(SBVS037)
• Three 12-Bit Data Acquisition Reference Designs Optimized for Low Power and Ultra-Small Form Factor TI
Precision Design (TIDU390)
• OPAx314 3-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier (SBOS563)
• OPAx365-Q1 50-MHz Low-Distortion High-CMRR Rail-to-Rail I/O, Single-Supply Operational Amplifiers
(SBOS512)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
PACKAGE OPTION ADDENDUM
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9-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS7049QDCURQ1
PREVIEW
Package Type Package Pins Package
Drawing
Qty
VSSOP
DCU
8
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
15MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2016
Addendum-Page 2
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