NXP LPC812M101FDH20 32-bit arm cortex-m0 microcontroller; up to 16 kb flash and 4 kb sram Datasheet

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32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and
4 kB SRAM
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Objective data sheet
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Rev. 1.0 — 7 November 2012
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LPC81xM
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1. General description
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The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
2. Features and benefits
 System:
 ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with
single-cycle multiplier and fast single-cycle I/O port.
 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
 System tick timer.
 Serial Wire Debug (SWD) and JTAG boundary scan modes supported.
 Micro Trace Buffer (MTB) supported.
 Memory:
 16 kB on-chip flash programming memory with 64 Byte page write and erase.
 4 kB SRAM.
 ROM API support:
 Boot loader.
 USART drivers.
 I2C drivers.
 Power profiles.
 Flash In-Application Programming (IAP) and In-System Programming (ISP).
 Digital peripherals:
 High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
 GPIO interrupt generation capability with boolean pattern-matching feature on eight
GPIO inputs.
 Switch matrix for flexible configuration of each I/O pin function.
 State Configurable Timer (SCT) with input and output functions (including capture
and match) assigned to pins through the switch matrix.
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The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory
and 4 kB of SRAM.
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LPC81xM
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32-bit ARM Cortex-M0+ microcontroller
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NXP Semiconductors
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 Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to
four programmable, fixed rates.
 Self Wake-up Timer (WKT) clocked from either the IRC or a low-power,
low-frequency internal oscillator.
 CRC engine.
 Windowed Watchdog timer (WWDT).
Analog peripherals:
 Comparator with external voltage reference with pin functions assigned or enabled
through the switch matrix.
Serial interfaces:
 Three USART interfaces with pin functions assigned through the switch matrix.
 Two SPI controllers with pin functions assigned through the switch matrix.
 One I2C-bus interface with pin functions assigned through the switch matrix.
Clock generation:
 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
 Crystal oscillator with an operating range of 1 MHz to 25 MHz.
 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
 10 kHz low-power oscillator for the WKT.
 PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator, the external clock
input CLKIN, or the internal RC oscillator.
 Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
 Integrated PMU (Power Management Unit) to minimize power consumption.
 Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
 Power-On Reset (POR).
 Brownout detect.
Unique device serial number for identification.
Single power supply.
Available as SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.
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
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3. Applications
 8/16-bit applications
 Consumer
 Climate control
LPC81xM
Objective data sheet
 Lighting
 Motor control
 Fire and security applications
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
2 of 67
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LPC812M101FDH16
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
LPC812M101FD20
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
LPC812M101FDH20
TSSOP20
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
4.1 Ordering options
Ordering options
Type number
Flash/kB SRAM/kB USART
I2C
SPI
Comparator
GPIO
Package
LPC810M021FN8
4
1
2
1
1
1
6
DIP8
LPC811M001FDH16
8
2
2
1
1
1
14
TSSOP16
LPC812M101FDH16
16
4
3
1
2
1
14
TSSOP16
LPC812M101FD20
16
4
2
1
1
1
18
SO20
LPC812M101FDH20
16
4
3
1
2
1
18
TSSOP20
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
3 of 67
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SOT403-1
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SOT097-2
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plastic dual in-line package; 8 leads (300 mil)
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
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DIP8
TSSOP16
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Version
LPC811M001FDH16
LPC81xM
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Description
LPC810M021FN8
Table 2.
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Package
Name
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Ordering information
Type number
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4. Ordering information
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Table 1.
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NXP Semiconductors
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32-bit ARM Cortex-M0+ microcontroller
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5. Block diagram
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LPC81xM
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NXP Semiconductors
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Fig 1.
LPC81xM block diagram
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
4 of 67
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6.1 Pinning
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
6. Pinning information
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NXP Semiconductors
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Fig 2.
Pin configuration DIP8 package (LPC810M021FN8)
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Fig 3.
Pin configuration TSSOP16 package
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Fig 4.
Pin configuration SO20 package (LPC812M101FD20)
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
5 of 67
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3,2B
Pin configuration TSSOP20 package
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
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9''
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Fig 5.
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
3,2B
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NXP Semiconductors
© NXP B.V. 2012. All rights reserved.
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32-bit ARM Cortex-M0+ microcontroller
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The pin description table Table 3 shows the pin functions that are fixed to specific pins on
each package. These fixed-pin functions are selectable between the GPIO, comparator,
SWD, and the XTAL pins. By default, the GPIO function is selected except on pins
PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only.
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6.2 Pin description
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LPC81xM
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NXP Semiconductors
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Do not assign more than one output to any pin. However, more than one input can be
assigned to a pin.
Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up
from Deep power-down mode via an external pin, do not assign any movable function to
this pin.
The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to
PIO0_4 by hardware when the part is in boundary scan mode.
Table 3.
Pin description table (fixed pins)
TSSOP16
DIP8
Type Reset Description
state
SO20/
TSSOP20
Symbol
PIO0_0/ACMP_I1/
TDO
19
16
8
PIO0_1/ACMP_I2/
CLKIN/TDI
12
LPC81xM
Objective data sheet
[5]
I/O
I; PU
PIO0_0 — General purpose digital input/output port 0 pin 0.
In ISP mode, this is the USART0 receive pin U0_RXD.
In boundary scan mode: TDO (Test Data Out).
SWDIO/PIO0_2/TMS 7
SWCLK/PIO0_3/
TCK
[1]
6
9
6
5
5
[5]
4
[2]
3
[2]
AI
-
ACMP_I1 — Analog comparator input 1.
I/O
I; PU
PIO0_1 — General purpose digital input/output pin. ISP entry
pin. A LOW level on this pin during reset starts the ISP command
handler.
In boundary scan mode: TDI (Test Data In).
AI
-
ACMP_I2 — Analog comparator input 2.
I
-
CLKIN — External clock input.
I/O
I; PU
SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default
on this pin.
In boundary scan mode: TMS (Test Mode Select).
I/O
-
PIO0_2 — General purpose digital input/output pin.
I/O
I; PU
SWCLK — Serial Wire Clock. SWCLK is enabled by default on
this pin.
In boundary scan mode: TCK (Test Clock).
I/O
-
PIO0_3 — General purpose digital input/output pin.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
7 of 67
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For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and
PIO0_10.
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The following exceptions apply:
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Movable function for the I2C, USART, SPI, and SCT pin functions can be assigned
through the switch matrix to any pin that is not power or ground in place of the pin’s fixed
functions.
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I; PU
PIO0_4 — General purpose digital input/output pin.
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I/O
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DIP8
A
A
[6]
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In ISP mode, this is the USART0 transmit pin U0_TXD.
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In boundary scan mode: TRST (Test Reset).
This pin triggers a wake-up from Deep power-down mode. If you
need to wake up from Deep power-down mode via an external
pin, do not assign any movable function to this pin. Pull this pin
HIGH externally to enter Deep power-down mode. Pull this pin
LOW to exit Deep power-down mode. A LOW-going pulse as
short as 50 ns wakes up the part.
RESET/PIO0_5
4
3
1
[4]
PIO0_6/VDDCMP
18
15
-
[9]
I/O
I; PU
RESET — External reset input: A LOW-going pulse as short as
50 ns on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor
execution to begin at address 0.
I
-
PIO0_5 — General purpose digital input/output pin.
I/O
I; PU
PIO0_6 — General purpose digital input/output pin.
AI
-
VDDCMP — Alternate reference voltage for the analog
comparator.
PIO0_7
17
14
-
[2]
I/O
I; PU
PIO0_7 — General purpose digital input/output pin.
PIO0_8/XTALIN
14
11
-
[8]
I/O
I; PU
PIO0_8 — General purpose digital input/output pin.
I
-
XTALIN — Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed 1.95 V.
I/O
I; PU
PIO0_9 — General purpose digital input/output pin.
O
-
XTALOUT — Output from the oscillator circuit.
I
IA
PIO0_10 — General purpose digital input/output pin. Assign I2C
functions to this pin when true open-drain pins are needed for a
signal compliant with the full I2C specification.
PIO0_9/XTALOUT
13
10
-
[8]
PIO0_10
9
8
-
[3]
PIO0_11
8
7
-
[3]
I
IA
PIO0_11 — General purpose digital input/output pin. Assign I2C
functions to this pin when true open-drain pins are needed for a
signal compliant with the full I2C specification.
PIO0_12
3
2
-
[2]
I/O
I; PU
PIO0_12 — General purpose digital input/output pin.
PIO0_13
2
1
-
[2]
I/O
I; PU
PIO0_13 — General purpose digital input/output pin.
-
[7]
I/O
I; PU
PIO0_14 — General purpose digital input/output pin.
-
[7]
I/O
I; PU
PIO0_15 — General purpose digital input/output pin.
I/O
I; PU
PIO0_16 — General purpose digital input/output pin.
I/O
I; PU
PIO0_17 — General purpose digital input/output pin.
-
-
3.3 V supply voltage.
-
Ground.
PIO0_14
PIO0_15
20
11
-
PIO0_16
10
-
-
[7]
PIO0_17
1
-
-
[7]
VDD
15
12
6
VSS
16
13
7
[1]
Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD
level ); IA = inactive, no pull-up/down enabled.
[2]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
[3]
True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode
Plus. Do not use this pad for high-speed applications such as SPI or USART.
LPC81xM
Objective data sheet
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TSSOP16
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SO20/
TSSOP20
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PIO0_4/WAKEUP/
TRST
Type Reset Description
state
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Pin description table (fixed pins)
Symbol
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Table 3.
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NXP Semiconductors
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
8 of 67
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LPC81xM
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32-bit ARM Cortex-M0+ microcontroller
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See Figure 10 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
[5]
5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When
configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[6]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep
power-down mode, pulling this pin LOW wakes up the chip.
[7]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[8]
5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system
oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[9]
The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with
configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is
disabled .
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[4]
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Objective data sheet
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LPC81xM
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Table 4.
Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)
Function name
Type
Description
U0_TXD
O
Transmitter output for USART0.
U0_RXD
I
Receiver input for USART0.
U0_RTS
O
Request To Send output for USART0.
U0_CTS
I
Clear To Send input for USART0.
U0_SCLK
I/O
Serial clock input/output for USART0 in synchronous mode.
U1_TXD
O
Transmitter output for USART1.
U1_RXD
I
Receiver input for USART1.
U1_RTS
O
Request To Send output for USART1.
U1_CTS
I
Clear To Send input for USART1.
U1_SCLK
I/O
Serial clock input/output for USART1 in synchronous mode.
U2_TXD
O
Transmitter output for USART2.
U2_RXD
I
Receiver input for USART2.
U2_RTS
O
Request To Send output for USART2.
U2_CTS
I
Clear To Send input for USART2.
U2_SCLK
I/O
Serial clock input/output for USART2 in synchronous mode.
SPI0_SCK
I/O
Serial clock for SPI0.
SPI0_MOSI
I/O
Master Out Slave In for SPI0.
SPI0_MISO
I/O
Master In Slave Out for SPI0.
SPI0_SSEL
I/O
Slave select for SPI0.
SPI1_SCK
I/O
Serial clock for SPI1.
SPI1_MOSI
I/O
Master Out Slave In for SPI1.
SPI1_MISO
I/O
Master In Slave Out for SPI1.
SPI1_SSEL
I/O
Slave select for SPI1.
CTIN_0
I
SCT input 0.
CTIN_1
I
SCT input 1.
CTIN_2
I
SCT input 2.
CTIN_3
I
SCT input 3.
CTOUT_0
O
SCT output 0.
CTOUT_1
O
SCT output 1.
CTOUT_2
O
SCT output 2.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
9 of 67
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Description
CTOUT_3
O
SCT output 3.
I2C0_SCL
I/O
I2C-bus clock input/output (open-drain if assigned to pin PIO0_10).
High-current sink only if assigned to PIO0_10 and if I2C Fast-mode
Plus is selected in the I/O configuration register.
I2C0_SDA
I/O
I2C-bus data input/output (open-drain if assigned to pin PIO0_11).
High-current sink only if assigned to pin PIO0_11 and if I2C
Fast-mode Plus is selected in the I/O configuration register.
ACMP_O
O
Analog comparator output.
CLKOUT
O
Clock output.
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Type
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© NXP B.V. 2012. All rights reserved.
10 of 67
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Rev. 1.0 — 7 November 2012
R
All information provided in this document is subject to legal disclaimers.
D
Output of the pattern match engine.
FT
Objective data sheet
FT
FT
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FT
LPC81xM
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Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)
Function name
GPIO_INT_BMAT O
FT
FT
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Table 4.
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NXP Semiconductors
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D
D
32-bit ARM Cortex-M0+ microcontroller
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7.1 ARM Cortex-M0+ core
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7. Functional description
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LPC81xM
FT
NXP Semiconductors
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The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a
two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four
breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O
enabled port for fast GPIO access.
A
The LPC81xM contain a total of 1 kB, 2 kB, or 4 kB on-chip static RAM data memory.
7.4 On-chip ROM
The 8 kB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
• Power profiles for configuring power consumption and PLL settings
• USART driver API routines
• I2C-bus driver API routines
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC81xM, the NVIC supports 32 vectored interrupts including up to 8 external
interrupt inputs selectable from all GPIO pins.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the ARM exceptions SVCall and PendSV.
• Relocatable interrupt vector table.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
LPC81xM
Objective data sheet
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Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
11 of 67
A
7.3 On-chip SRAM
R
The LPC81xM contain up to 16 kB of on-chip flash program memory. The flash memory
supports a 64 Byte page size with page write and erase.
D
7.2 On-chip flash program memory
FT
The core includes a single-cycle multiplier and a system tick timer.
D
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FT
FT
FT
LPC81xM
FT
D
R
R
FT
FT
FT
FT
32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
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NXP Semiconductors
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D
Up to eight pins, regardless of the selected function, can be programmed to generate an
interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be
selected from all digital or mixed digital/analog pins. The pin interrupt/pattern match block
controls the edge or level detection mechanism.
D
FT
FT
A
A
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R
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D
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7.6 System tick timer
D
The LPC81xM incorporates several distinct memory regions. Figure 6 shows the overall
map of the entire address space from the user program viewpoint following reset. The
interrupt vector area supports address remapping.
The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,
the system tick timer (SysTick), and the reduced power modes.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
12 of 67
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7.7 Memory map
R
The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to
generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).
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A
UHVHUYHG
63,
63,
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FT
[
[$
N%RQFKLSIODVK /3&
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R
[(
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Fig 6.
LPC81xM Memory map
7.8 I/O configuration
The IOCON block controls the configuration of the I/O pins. Each digital or mixed
digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10
and PIO0_11) in Table 3 can be configured as follows:
• Enable or disable the weak internal pull-up and pull-down resistors.
• Select a pseudo open-drain mode. The input cannot be pulled up above VDD.
LPC81xM
Objective data sheet
F
D
D
[(
SULYDWHSHULSKHUDOEXV
N%RQFKLSIODVK /3&
A
FT
FT
A
A
R
R
D
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[
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FT
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FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
*%
A
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NXP Semiconductors
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
13 of 67
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LPC81xM
FT
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32-bit ARM Cortex-M0+ microcontroller
A
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NXP Semiconductors
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divided clock signals (IOCONCLKCDIV, see Figure 9 “LPC81xM clock generation”).
You can also bypass the glitch filter.
A
A
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R
D
D
• Program the input glitch filter with different filter constants using one of the IOCON
D
FT
FT
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A
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R
D
• Invert the input signal.
• Hysteresis can be enabled or disabled.
• For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard
D
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A
A
Remark: The functionality of each I/O pin is flexible and is determined entirely through the
switch matrix. See Section 7.9 for details.
7.8.1 Standard I/O pad configuration
Figure 7 shows the possible pin modes for standard I/O pins with analog input function:
Objective data sheet
Digital output driver with configurable open-drain output
Digital input: Weak pull-up resistor (PMOS device) enabled/disabled
Digital input: Weak pull-down resistor (NMOS device) enabled/disabled
Digital input: Repeater mode enabled/disabled
Digital input: Input glitch filter selectable on all pins
Analog input
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
R
mode disconnects the digital functionality.
LPC81xM
D
• On mixed digital/analog pins, enable the analog input mode. Enabling the analog
•
•
•
•
•
•
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digital operation, for I2C standard and fast modes, or for I2C Fast mode+.
© NXP B.V. 2012. All rights reserved.
14 of 67
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3,1
D
R
(6'
A
966
9''
ZHDN
SXOOXS
SXOOXSHQDEOH
UHSHDWHUPRGH
HQDEOH
SLQFRQILJXUHG
DVGLJLWDOLQSXW
GDWDLQSXW
VHOHFWGDWD
LQYHUWHU
VHOHFWJOLWFK
ILOWHU
SLQFRQILJXUHG
DVDQDORJLQSXW
ZHDN
SXOOGRZQ
SXOOGRZQHQDEOH
352*5$00$%/(
*/,7&+),/7(5
VHOHFWDQDORJLQSXW
DQDORJLQSXW
DDD
Fig 7.
Standard I/O pad configuration
7.9 Switch Matrix (SWM)
The switch matrix controls the function of each digital or mixed analog/digital pin in a
highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and
I2C functions to any pin that is not power or ground. These functions are called movable
functions and are listed in Table 4.
Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can
be enabled or disabled through the switch matrix. These functions are called fixed-pin
functions and cannot move to other pins. The fixed-pin functions are listed in Table 3. If a
fixed-pin function is disabled, any other movable function can be assigned to this pin.
7.10 Fast General-Purpose parallel I/O (GPIO)
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC81xM use accelerated GPIO functions:
• GPIO registers are located on the ARM Cortex M0+ IO bus for fastest possible
single-cycle I/O timing.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
F
D
D
(6'
GDWDRXWSXW
VWURQJ
SXOOGRZQ
A
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FT
A
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D
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VWURQJ
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RXWSXWHQDEOH
FT
FT
FT
FT
SLQFRQILJXUHG
DVGLJLWDORXWSXW
GULYHU
9''
A
A
A
A
R
R
D
D
D
9''
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
RSHQGUDLQHQDEOH
A
A
A
A
A
NXP Semiconductors
© NXP B.V. 2012. All rights reserved.
15 of 67
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A
A
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32-bit ARM Cortex-M0+ microcontroller
D
R
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A
FT
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FT
A
A
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• An entire port value can be written in one instruction.
• Mask, set, and clear operations are supported for the entire port.
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
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FT
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All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the
switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be
moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and
RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.
D
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A
7.10.1 Features
• Bit level port registers allow a single instruction to set and clear any number of bits in
one write operation.
• Direction control of individual bits.
• All I/O default to inputs with internal pull-up resistors enabled after reset - except for
the I2C-bus true open-drain pins PIO0_2 and PIO0_3.
• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON block for each GPIO pin (see Figure 7).
• Control of the digital output slew rate allowing to switch more outputs simultaneously
without degrading the power/ground distribution of the device.
7.11 Pin interrupt/pattern match engine
The pin interrupt block configures up to eight pins from all digital pins for providing eight
external interrupts connected to the NVIC.
The pattern match engine can be used, in conjunction with software, to create complex
state machines based on pin inputs.
Any digital pin, independently of the function selected through the switch matrix, can be
configured through the SYSCON block as input to the pin interrupt or pattern match
engine. The registers that control the pin interrupt or pattern match engine are located on
the IO+ bus for fast single-cycle access.
7.11.1 Features
• Pin interrupts
– Up to eight pins can be selected from all digital pins as edge- or level-sensitive
interrupt requests. Each request creates a separate interrupt in the NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH- or LOW-active.
– Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and
deep power-down mode.
• Pin interrupt pattern match engine
– Up to 8 pins can be selected from all digital pins to contribute to a boolean
expression. The boolean expression consists of specified levels and/or transitions
on various combinations of these pins.
– Each minters (product term) comprising the specified boolean expression can
generate its own, dedicated interrupt request.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
16 of 67
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LPC81xM
FT
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32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
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NXP Semiconductors
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– The pattern match engine does not facilitate wake-up.
R
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A
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D
– Any occurrence of a pattern match can be programmed to also generate an RXEV
notification to the ARM CPU. The RXEV signal can be connected to a pin.
D
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7.12 USART0/1/2
A
synchronous mode for USART functions connected to all digital pins except PIO0_10
and PIO0_11.
• 7, 8, or 9 data bits and 1 or 2 stop bits
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485
possible with software address detection and transceiver direction control.)
• Parity generation and checking: odd, even, or none.
• One transmit and one receive data buffer.
• RTS/CTS for hardware signaling for automatic flow control. Software flow control can
be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output.
•
•
•
•
•
•
Received data and status can optionally be read from a single register
Break generation and detection.
Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
Built-in Baud Rate Generator.
A fractional rate divider is shared among all UARTs.
Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in
receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS
detect, and receiver sample noise detected.
• Separate data and flow control loopback modes for testing.
• Baud rate clock can also be output in asynchronous mode.
• Supported by on-chip ROM API.
7.13 SPI0/1
Remark: SPI0 is available on all LPC800 parts. SPI1 is available on parts
LPC812M101FDH16 and LPC812M101FDH20 only.
All SPI functions are movable functions and are assigned to pins through the switch
matrix.
LPC81xM
Objective data sheet
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Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
17 of 67
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• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 30 Mbit/s in
R
7.12.1 Features
D
All USART functions are movable functions and are assigned to pins through the switch
matrix.
FT
Remark: USART0 and USART1 are available on all LPC800 parts. USART2 is available
on parts LPC812M101FDH16 and LPC812M101FDH20 only.
D
D
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32-bit ARM Cortex-M0+ microcontroller
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• Maximum data rates of 30 Mbit/s in slave and master mode for SPI functions
connected to all digital pins except PIO0_10 and PIO0_11.
A
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A
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7.13.1 Features
FT
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LPC81xM
FT
NXP Semiconductors
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• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
R
A
Remark: Texas Instruments SSI and National Microwire modes are not supported.
7.14 I2C-bus interface
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
The I2C-bus functions are movable functions and can be assigned through the switch
matrix to any pin. However, only the true open-drain PIO0_10 and PIO0_11 provide the
electrical characteristics to support the full I2C-bus specification (see Ref. 1).
7.14.1 Features
•
•
•
•
•
Supports standard and fast mode with data rates of up to 400 kbit/s.
•
•
•
•
10-bit addressing supported with software assist.
Independent Master, Slave, and Monitor functions.
Supports both Multi-master and Multi-master with Slave functions.
Multiple I2C slave addresses supported in hardware.
One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C bus addresses.
Supports SMBus.
Supported by on-chip ROM API.
If the I2C functions are connected to the true open-drain pins (PIO0_10 and
PIO0_11), the I2C supports the full I2C-bus specification:
– Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA
and SCL pins connected to the I2C-bus are floating and do not disturb the bus.
– Supports Fast-mode Plus with bit rates up to 1 Mbit/s.
LPC81xM
Objective data sheet
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Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
18 of 67
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• One Slave Select input/output with selectable polarity and flexible usage.
R
versatile operation, including “any length” frames.
D
• Control information can optionally be written along with data. This allows very
FT
be useful while setting up an SPI memory.
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32-bit ARM Cortex-M0+ microcontroller
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The state configurable timer can perform basic 16-bit and 32-bit timer/counter functions
with match outputs and external and internal capture inputs. In addition, the SCT can
employ up to two different programmable states, which can change under the control of
events, to provide complex timing patterns.
F
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7.15 State-Configurable Timer (SCT)
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LPC81xM
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NXP Semiconductors
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Two 16-bit counters or one 32-bit counter.
Counters clocked by bus clock or selected input.
Up counters or up-down counters.
State variable allows sequencing across multiple counter cycles.
The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state, and the count direction.
• Events control outputs, interrupts, and the SCT states.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• Selected events can limit, halt, start, or stop a counter.
• Supports:
– 4 inputs
– 4 outputs
– 5 match/capture registers
– 6 events
– 2 states
7.16 Multi-Rate Timer (MRT)
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval, and each channel
operates independently from the other channels.
7.16.1 Features
• 24-bit interrupt timer
• Four channels independently counting down from individually set values
• Repeat and one-shot interrupt modes
7.17 Windowed WatchDog Timer (WWDT)
The watchdog timer resets the controller if software fails to periodically service it within a
programmable time window.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
19 of 67
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•
•
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•
R
7.15.1 Features
D
All inputs and outputs of the SCT are movable functions and are assigned to pins through
the switch matrix.
D
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• Optional windowed operation requires reload to occur between a minimum and
FT
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R
R
D
period.
A
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maximum time period, both programmable.
D
• Optional warning interrupt can be generated at a programmable time prior to
R
A
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in
multiples of Tcy(WDCLK)  4.
• The Watchdog Clock (WDCLK) source can be selected from the internal RC oscillator
(IRC), or the dedicated watchdog oscillator (WDOsc). This gives a wide range of
potential timing choices of watchdog operation under different power conditions.
7.18 Self Wake-up Timer (WKT)
The self wake-up timer is a 32-bit, loadable down-counter. Writing any non-zero value to
this timer automatically enables the counter and launches a count-down sequence. When
the counter is used as a wake-up timer, this write can occur just prior to entering a
reduced power mode.
7.18.1 Features
• 32-bit loadable down-counter. Counter starts automatically when a count value is
loaded. Time-out generates an interrupt/wake up request.
• The WKT resides in a separate, always-on power domain.
• The WKT supports two clock sources. One clock source originates from the
always-on power domain.
• The WKT can be used for waking up the part from any reduced power mode,
including Deep power-down mode, or for general-purpose timing.
7.19 Analog comparator (ACMP)
The analog comparator with selectable hysteresis can compare voltage levels on external
pins and internal voltages.
After power-up and after switching the input channels of the comparator, the output of the
voltage ladder must be allowed to settle to its stable value before it can be used as a
comparator reference input. Settling times are given in Table 23.
The analog comparator output is a movable function and is assigned to a pin through the
switch matrix. The comparator inputs and the voltage reference are enabled or disabled
on pins PIO0_0 and PIO0_1 through the switch matrix.
Objective data sheet
FT
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• Internally resets chip if not periodically reloaded during the programmable time-out
LPC81xM
A
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7.17.1 Features
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
•
•
•
•
A
A
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NXP Semiconductors
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
20 of 67
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F
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
9''
A
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NXP Semiconductors
D
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R
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FT
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FRPSDUDWRU
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Fig 8.
Comparator block diagram
7.19.1 Features
• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input
hysteresis.
• Two selectable external voltages (VDD or VDDCMP on pin PIO0_6); fully configurable
on either positive or negative input channel.
• Internal voltage reference from band gap and temperature sensor selectable on either
positive or negative input channel.
• 32-stage voltage ladder with the internal reference voltage selectable on either the
positive or the negative input channel.
• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V
supply voltage rail.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Interrupt output is connected to NVIC.
• Comparator level output is connected to output pin ACMP_O.
• The comparator output can be routed internally to the SCT input through the switch
matrix.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
21 of 67
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D
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32-bit ARM Cortex-M0+ microcontroller
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7.20 Clocking and power control
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LPC81xM
FT
NXP Semiconductors
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A
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Fig 9.
LPC81xM clock generation
7.20.1 Crystal and internal oscillators
The LPC81xM include four independent oscillators:
1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz.
2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1%
accuracy.
3. The internal low-power, low-frequency Oscillator with a nominal frequency of 10 kHz
with 40% accuracy for use with the self wake-up timer.
4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal
frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
22 of 67
A
PHPRULHV
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LPC81xM
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R
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32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
R
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D
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NXP Semiconductors
D
R
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A
FT
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A
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F
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D
Each oscillator, except the low-frequency oscillator, can be used for more than one
purpose as required in a particular application.
D
FT
FT
A
A
R
R
D
Following reset, the LPC81xM will operate from the IRC until switched by software. This
allows systems to operate without any external crystal and the bootloader code to operate
at a known frequency.
D
D
R
A
D
R
A
7.20.1.1
Internal RC Oscillator (IRC)
The IRC may be used as the clock source for the WWDT, and/or as the clock that drives
the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
The IRC can be used as a clock source for the CPU with or without using the PLL. The
IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating
frequency, by the system PLL.
Upon power-up or any chip reset, the LPC81xM use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.20.1.2
Crystal Oscillator (SysOsc)
The crystal oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted
to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.
7.20.1.3
Internal Low-power Oscillator and Watchdog Oscillator (WDOsc)
The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz.
The frequency spread over silicon process variations is  40%.
The WDOsc is a dedicated oscillator for the windowed WWDT.
The internal low-power 10 kHz (  40% accuracy) oscillator serves a the clock input to the
WKT. This oscillator can be configured to run in all low power modes.
7.20.2 Clock input
A 3.3 V external clock source (25 MHz typical) can be supplied on the selected CLKIN pin
or a 1.8 V external clock source can be supplied on the XTALIN pin (see Section 13.1).
7.20.3 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the
minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.
The PLL is turned off and bypassed following a chip reset and may be enabled by
software. The program must configure and activate the PLL, wait for the PLL to lock, and
then connect to the PLL as a clock source. The PLL settling time is nominally 100 s.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
FT
See Figure 9 for an overview of the LPC81xM clock generation.
© NXP B.V. 2012. All rights reserved.
23 of 67
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32-bit ARM Cortex-M0+ microcontroller
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The LPC81xM features a clock output function that routes the IRC, the SysOsc, the
watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can
be connected to any digital pin through the switch matrix.
F
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7.20.4 Clock output
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NXP Semiconductors
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7.20.5 Wake-up process
D
The LPC81xM supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also
be controlled as needed by changing clock sources, reconfiguring PLL values, and/or
altering the CPU clock divider value. This allows a trade-off of power versus processing
speed based on application requirements. In addition, a register is provided for shutting
down the clocks to individual on-chip peripherals, allowing to fine-tune power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. Selected peripherals have their own clock divider which provides even
better power control.
7.20.6.1
Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile API. The API is accessible through the on-chip
ROM.
The power configuration routine configures the LPC81xM for one of the following power
modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.20.6.2
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
LPC81xM
Objective data sheet
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Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
24 of 67
A
7.20.6 Power control
R
The LPC81xM begin operation at power-up by using the IRC as the clock source. This
allows chip operation to resume quickly. If the SysOsc, the external clock source, or the
PLL is needed by the application, software must enable these features and wait for them
to stabilize before they are used as a clock source.
D
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In Deep-sleep mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all
clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if
selected. The IRC output is disabled. In addition all analog blocks are shut down and the
flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog
oscillator and the BOD circuit running for self-timed wake-up and BOD protection.
F
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Deep-sleep mode
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
7.20.6.3
A
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NXP Semiconductors
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Deep-sleep mode saves power and allows for short wake-up times.
7.20.6.4
Power-down mode
In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all
clock sources are off except for watchdog oscillator or low-power oscillator if selected. In
addition all analog blocks and the flash are shut down. In Power-down mode, the
application can keep the watchdog oscillator and the BOD circuit running for self-timed
wake-up and BOD protection.
The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as
inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the
USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C
blocks (in slave mode).
Any interrupt used for waking up from Power-down mode must be enabled in one of the
SYSCON wake-up enable registers and the NVIC.
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
7.20.6.5
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pin and the self wake-up timer if enabled. The LPC81xM can wake up from Deep
power-down mode via the WAKEUP pin, or without an external signal by using the
time-out of the self wake-up timer (see Section 7.18).
The LPC81xM can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU block. Locking out Deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in
Deep power-down mode.
LPC81xM
Objective data sheet
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Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
25 of 67
A
Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the
SYSCON wake-up enable registers and the NVIC.
R
The LPC81xM can wake up from Deep-sleep mode via a reset, digital pins selected as
inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the
USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C
blocks (in slave mode).
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32-bit ARM Cortex-M0+ microcontroller
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7.21.1 Reset
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7.21 System control
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LPC81xM
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NXP Semiconductors
D
D
Reset has four sources on the LPC81xM: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
R
A
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7.21.2 Brownout detection
The LPC81xM includes up to four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC
to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a
dedicated status register. Four threshold levels can be selected to cause a forced reset of
the chip.
7.21.3 Code security (Code Read Protection - CRP)
CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details, see the LPC800 user manual.
There are three levels of Code Read Protection:
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
26 of 67
A
9''
R
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
D
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
FT
A LOW-going pulse as short as 50 ns resets the part.
D
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LPC81xM
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32-bit ARM Cortex-M0+ microcontroller
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1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
D
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A
A
R
R
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A
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC800 user manual.
7.21.4 APB interface
The APB peripherals are located on one APB bus.
7.21.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the
main static RAM, the CRC, and the ROM.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
27 of 67
A
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
R
CAUTION
D
3. Running an application with level CRP3 selected, fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin as well. If necessary, the application must provide a flash update
mechanism using IAP calls or using a call to the reinvoke ISP command to enable
flash update via the USART.
FT
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
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LPC81xM
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32-bit ARM Cortex-M0+ microcontroller
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Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is
configured to support up to four breakpoints and two watch points.
F
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7.22 Emulation and debugging
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NXP Semiconductors
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D
R
A
FT
The Micro Trace Buffer is implemented on the LPC81xM.
D
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
28 of 67
A
To perform boundary scan testing, follow these steps:
R
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC81xM
is in reset. The JTAG boundary scan pins are selected by hardware when the part is in
boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 3).
D
D
D
D
D
R
R
R
R
R
D
R
R
FT
R
FT
FT
A
A
R
+5.5
V
5 V open-drain pins
PIO0_10 and
PIO0_11
[4]
0.5
+5.5
V
3 V tolerant I/O pin
PIO0_6
[5]
0.5
+3.6
V
[6]
0.5 V
4.6
V
0.5
+2.5
V
D
V
0.5
FT
+4.6
[3]
A
0.5
5 V tolerant I/O
pins; only valid
when the VDD
supply voltage is
present
R
Unit
D
Max
D
R
A
[7]
[2]
Vi(xtal)
crystal input voltage
IDD
supply current
per supply pin
-
100
mA
ISS
ground current
per ground pin
-
100
mA
Ilatch
I/O latch-up current
(0.5VDD) < VI <
(1.5VDD);
-
100
mA
Tstg
storage temperature
non-operating
65
+150
C
Tj(max)
maximum junction temperature
-
150
C
Ptot(pack)
total power dissipation (per package)
based on package
heat transfer, not
device power
consumption
-
<tbd>
W
VESD
electrostatic discharge voltage
human body
model; all pins
-
<tbd>
V
Tj < 125 C
[1]
[8]
[9]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 9.
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 9) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3]
Including voltage on outputs in tri-state mode. Does not apply to pin PIO0_6.
[4]
VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[5]
VDD present or not present.
[6]
If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below
VDD without affecting the hysteresis range of the comparator function.
[7]
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
F
D
D
Min
[2]
analog input voltage
VIA
A
FT
FT
input voltage
R
A
A
supply voltage (core and external rail)
D
R
R
VDD
R
A
D
D
Conditions
VI
D
R
FT
FT
A
A
R
R
D
D
D
Parameter
FT
FT
FT
FT
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
A
A
A
A
R
R
D
D
D
8. Limiting values
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Symbol
A
A
A
A
A
NXP Semiconductors
© NXP B.V. 2012. All rights reserved.
29 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
LPC81xM
FT
D
R
R
FT
FT
FT
FT
32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[9]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
D
R
A
F
FT
FT
A
A
R
R
D
D
[8]
D
FT
FT
A
A
R
R
D
D
D
9. Thermal characteristics
R
A
FT
R
A
T j = T amb +  P D  R th  j – a  
D
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 6.
Thermal characteristics
Symbol
Parameter
Tj(max)
maximum junction
temperature
Table 7.
Conditions
Min
Typ
Max
Unit
-
-
125
C
Thermal resistance (TSSOP packages)
Symbol Parameter
Conditions
Thermal resistance in C/W
±15 %
TSSOP16
Rth(j-a)
Rth(j-c)
thermal resistance from JEDEC (4.5 in  4 in); still <tbd>
junction to ambient
air
<tbd>
Single-layer (4.5 in  3 in); <tbd>
still air
<tbd>
<tbd>
<tbd>
thermal resistance from
junction to case
Table 8.
Thermal resistance value (SO/DIP packages)
Symbol
Parameter
Rth(j-a)
thermal resistance from JEDEC (4.5 in  4 in); <tbd>
junction to ambient
still air
Conditions
Thermal resistance in C/W ±15 %
SO20
8-layer (4.5 in  3 in);
still air
Rth(j-c)
LPC81xM
Objective data sheet
TSSOP20
thermal resistance from
junction to case
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
DIP8
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
© NXP B.V. 2012. All rights reserved.
30 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
FT
D
D
FT
FT
A
A
R
R
D
D
D
Typ[1]
Max
Unit
1.8
3.3
3.6
V
-
1.4
-
mA
-
<tbd>
-
mA
-
5.5
-
mA
-
<tbd>
-
mA
-
0.8
-
mA
-
<tbd>
-
mA
-
2.6
-
mA
-
<tbd>
-
mA
R
Min
A
FT
D
R
A
Active mode; code
while(1){}
system clock = 12 MHz; default
mode; VDD = 3.3 V
[2][3][4]
system clock = 12 MHz;
low-current mode; VDD = 3.3 V
[2][3][4]
system clock = 30 MHz; default
mode; VDD = 3.3 V
[2][3][6]
system clock = 30 MHz;
low-current mode; VDD = 3.3 V
[2][3][6]
Sleep mode;
[6][7]
[6][7]
[7][8]
[7][8]
[2][3][4]
[6][7]
system clock = 12 MHz; default
mode; VDD = 3.3 V
system clock = 12 MHz;
low-current mode; VDD = 3.3 V
[2][3][4]
system clock = 30 MHz; default
mode; VDD = 3.3 V
[2][3][4]
system clock = 30 MHz;
low-current mode; VDD = 3.3 V
[2][3][4]
[6][7]
[6][7]
[6][7]
Deep-sleep mode;
VDD = 3.3 V
[2][3][9]
-
170
-
A
Power-down mode;
VDD = 3.3 V
[2][3][9]
-
2
-
A
[2][10]
-
220
-
nA
<tbd>
-
nA
Deep power-down mode; VDD =
3.3 V
Low-power oscillator off
Low-power oscillator on/WKT
wake-up enabled
Standard port pins configured as digital pins, RESET, see Figure 11
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
<tbd>
<tbd>
nA
IIH
HIGH-level input
current
VI = VDD; on-chip pull-down
resistor disabled
-
<tbd>
<tbd>
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
<tbd>
<tbd>
nA
VI
input voltage
VDD  1.8 V; 5 V tolerant pins
except PIO0_6
0
-
5
V
VDD  1.8 V; on 3 V tolerant pin
PIO0_6
0
-
3.6
VDD = 0 V
0
-
3.6
Objective data sheet
F
FT
FT
Conditions
executed from flash
LPC81xM
A
A
A
supply current
R
R
R
IDD
R
A
D
D
supply voltage (core
and external rail)
D
R
FT
FT
A
A
R
R
D
D
D
VDD
FT
FT
FT
FT
Table 9.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Parameter
A
A
A
A
R
R
D
D
D
10. Static characteristics
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Symbol
A
A
A
A
A
NXP Semiconductors
[12]
[14]
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
V
© NXP B.V. 2012. All rights reserved.
31 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
R
A
FT
R
output voltage
output active
0
-
<tbd>
VIH
HIGH-level input
voltage
<tbd>
-
-
V
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
<tbd>
-
-
V
VOH
HIGH-level output
voltage
A
A
R
FT
FT
V
D
D
R
A
FT
-
V
-
V
LOW-level output
voltage
2.5 V  VDD  3.6 V; IOL = 4 mA
-
-
<tbd>
V
1.8 V  VDD < 2.5 V; IOL = 3 mA
-
-
<tbd>
V
HIGH-level output
current
VOH = VDD  0.4 V;
<tbd>
-
-
mA
<tbd>
-
-
mA
<tbd>
-
-
mA
2.5 V  VDD  3.6 V
1.8 V  VDD < 2.5 V
VOL = 0.4 V
2.5 V  VDD  3.6 V
1.8 V  VDD < 2.5 V
<tbd>
-
-
mA
-
-
<tbd>
mA
-
-
<tbd>
mA
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[15]
IOLS
LOW-level short-circuit
output current
[15]
Ipd
pull-down current
VI = 5 V
<tbd>
<tbd>
<tbd>
A
Ipu
pull-up current
VI = 0 V;
<tbd>
<tbd>
<tbd>
A
<tbd>
<tbd>
<tbd>
A
<tbd>
<tbd>
<tbd>
A
VOL = VDD
2.0 V  VDD  3.6 V
1.8 V  VDD < 2.0 V
VDD < VI < 5 V
High-drive output pins configured as digital pins (PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13) see Figure 11
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
<tbd>
<tbd>
nA
IIH
HIGH-level input
current
VI = VDD; on-chip pull-down
resistor disabled
-
<tbd>
<tbd>
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
<tbd>
<tbd>
nA
VI
input voltage
VDD  1.8 V
0
-
5
V
VDD = 0 V
0
-
3.6
V
output active
[12]
[14]
VO
output voltage
<tbd>
-
<tbd>
V
VIH
HIGH-level input
voltage
<tbd>
-
-
V
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
VOH
HIGH-level output
voltage
<tbd>
-
-
V
2.5 V VDD 3.6 V; IOH = 20 mA
<tbd>
-
-
V
1.8 V VDD < 2.5 V; IOH = 12 mA
<tbd>
-
-
V
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
32 of 67
A
-
R
<tbd>
<tbd>
D
2.5 V  VDD  3.6 V; IOH = 4 mA
1.8 V  VDD < 2.5 V; IOH = 3 mA
Objective data sheet
F
VO
Unit
R
Max
D
Typ[1]
D
Min
LPC81xM
A
FT
FT
A
A
R
R
D
D
D
Conditions
LOW-level output
current
D
R
FT
FT
A
A
R
R
D
D
D
Parameter
IOL
FT
FT
FT
FT
Symbol
IOH
A
A
A
A
R
R
D
D
D
Table 9.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
VOL
A
A
A
A
A
NXP Semiconductors
D
D
D
D
D
R
R
R
R
R
D
R
R
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
V
-
mA
1.8 V  VDD < 2.5 V
<tbd>
-
-
mA
VOL = 0.4 V
<tbd>
-
-
mA
<tbd>
-
-
mA
-
-
<tbd>
mA
R
<tbd>
-
A
2.5 V  VDD  3.6 V
[15]
LOW-level short-circuit
output current
VOL = VDD
Ipd
pull-down current
VI = 5 V
<tbd>
<tbd>
<tbd>
A
Ipu
pull-up current
VI = 0 V
<tbd>
<tbd>
<tbd>
A
<tbd>
<tbd>
<tbd>
A
<tbd>
<tbd>
<tbd>
A
2.0 V  VDD  3.6 V
1.8 V  VDD < 2.0 V
VDD < VI < 5 V
pins (PIO0_10 and PIO0_11) see Figure 11
VIH
HIGH-level input
voltage
<tbd>
-
-
V
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
-
<tbd>
-
V
IOL
LOW-level output
current
<tbd>
-
-
mA
<tbd>
-
-
<tbd>
-
-
<tbd>
-
-
VOL = 0.4 V; I2C-bus pins
configured as standard mode pins
2.5 V  VDD  3.6 V
1.8 V  VDD < 2.5 V
I2C-bus
VOL = 0.4 V;
pins
configured as Fast-mode Plus
pins
mA
2.5 V  VDD  3.6 V
1.8 V  VDD < 2.5 V
input leakage current
ILI
[16]
VI = VDD
VI = 5 V
-
<tbd>
<tbd>
A
-
<tbd>
<tbd>
A
Oscillator input pins (PIO0_8 and PIO0_9)
Vi(xtal)
crystal input voltage
<tbd>
<tbd>
<tbd>
V
Vo(xtal)
crystal output voltage
<tbd>
<tbd>
<tbd>
V
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2]
Tamb = 25 C.
[3]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4]
IRC enabled; system oscillator disabled; system PLL disabled.
[5]
System oscillator enabled; IRC disabled; system PLL disabled.
[6]
BOD disabled.
[7]
All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system
configuration block.
[8]
IRC disabled; system oscillator enabled; system PLL enabled.
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
D
-
<tbd>
IOLS
LOW-level output
current
F
-
VOH = VDD  0.4 V;
2.5 V  VDD  3.6 V
1.8 V  VDD < 2.5 V
IOL
A
1.8 V VDD < 2.5 V; IOL = 3 mA
FT
HIGH-level output
current
FT
IOH
V
A
<tbd>
A
-
R
-
R
2.5 V VDD 3.6 V; IOL = 4 mA
D
LOW-level output
voltage
D
VOL
Unit
FT
Max
A
Typ[1]
R
Min
D
Conditions
R
FT
FT
A
A
R
R
D
D
D
Parameter
I2C-bus
FT
FT
FT
FT
Symbol
LOW-level output
current
A
A
A
A
R
R
D
D
D
Table 9.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
IOL
A
A
A
A
A
NXP Semiconductors
© NXP B.V. 2012. All rights reserved.
33 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
[12] Including voltage on outputs in 3-state mode.
FT
A
A
R
R
D
[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
FT
FT
FT
FT
[10] WAKEUP pin pulled HIGH externally.
A
A
A
A
R
R
D
D
D
All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
[9]
A
A
A
A
A
NXP Semiconductors
D
D
R
[13] VDD supply voltage must be present.
A
FT
[14] 3-state outputs go into 3-state mode in Deep power-down mode.
D
R
A
[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To VSS.
/3&
SLQ3,2BQ
9''
,2/
,SG
$
,2+
,SX
SLQ3,2BQ
$
DDD
Fig 11. Pin input/output current measurement
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
34 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
FT
A
A
R
R
D
D
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions):
F
FT
FT
A
A
R
R
D
D
D
10.1 Power consumption
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
R
A
FT
D
R
A
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIO DIR register.
• Write 0 to all GPIO DATA register to drive the outputs LOW.
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals
disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz - 30 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 12. Active mode: Typical supply current IDD versus supply voltage VDD
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
35 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
X
(X)
A
FT
FT
A
A
R
R
D
D
D
001aac984
X
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
X
R
A
FT
D
R
X
A
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals
disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz - 30 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 13. Active mode: Typical supply current IDD versus temperature
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz - 30 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 14. Sleep mode: Typical supply current IDD versus temperature for different system
clock frequencies
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
36 of 67
D
D
D
D
D
R
R
R
R
R
FT
FT
FT
FT
FT
LPC81xM
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
X
(X)
A
FT
FT
A
A
R
R
D
D
D
001aac984
X
A
A
A
A
A
NXP Semiconductors
D
D
X
R
A
FT
D
R
X
A
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 15. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 16. Power-down mode: Typical supply current IDD versus temperature for different
supply voltages VDD
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
37 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
X
(X)
A
FT
FT
A
A
R
R
D
D
D
001aac984
X
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
X
R
A
FT
D
R
X
A
<tbd>
X
X
X
X
X
X
X
X
X (X)
(1) WKT running.
(1) WKT not running.
Fig 17. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD
10.2 CoreMark data
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
External signal generator providing 1 MHz to 20 MHz signal drives the XTALIN input; when testing
1 MHz to 19 MHz the system PLL is OFF, SYSAHBCLKDIV = 1; when testing 20 MHz to 30 MHz
the system PLL is configured so that SYSAHBCLKDIV = 1.
Fig 18. CoreMark current consumption for power modes 0, 1, 2, and 3
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
38 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
FT
FT
A
A
R
R
D
D
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
F
FT
FT
A
A
R
R
D
D
D
10.3 Peripheral power consumption
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
R
A
FT
D
R
Table 10.
Power consumption for individual analog and digital blocks
Peripheral
Typical supply current in
mA
n/a
12 MHz
30 MHz
IRC
<tbd>
-
-
System oscillator running; PLL off; independent
of main clock frequency.
System oscillator
at 12 MHz
<tbd>
-
-
IRC running; PLL off; independent of main clock
frequency.
Watchdog
oscillator at
500 kHz/2
<tbd>
-
-
System oscillator running; PLL off; independent
of main clock frequency.
BOD
<tbd>
-
-
Independent of main clock frequency.
Main PLL
-
<tbd>
-
-
CLKOUT
-
<tbd>
<tbd>
Main clock divided by 4 in the CLKOUTDIV
register.
SCT
-
<tbd>
<tbd>
-
MRT
-
<tbd>
<tbd>
-
WKT
-
<tbd>
<tbd>
-
GPIO
-
<tbd>
<tbd>
GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
<tbd>
<tbd>
-
Pin
interrupt/pattern
match
LPC81xM
Objective data sheet
Notes
IOCON
-
<tbd>
<tbd>
-
I2C
-
<tbd>
<tbd>
-
ROM
-
<tbd>
<tbd>
-
SPI0
-
<tbd>
<tbd>
-
SPI1
-
<tbd>
<tbd>
-
USART0
-
<tbd>
<tbd>
-
USART1
-
<tbd>
<tbd>
-
USART2
-
<tbd>
<tbd>
-
WWDT
-
<tbd>
<tbd>
Main clock selected as clock source for the
WDT.
Comparator
-
<tbd>
<tbd>
-
CRC
-
<tbd>
<tbd>
-
SWM
-
<tbd>
<tbd>
-
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
39 of 67
A
The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz.
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
001aac984
X
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
10.4 Electrical pin characteristics
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
X
(X)
R
A
FT
D
X
R
A
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V and VDD = 1.8 V; on pin <tbd>.
Fig 19. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_10 and PIO0_11.
Fig 20. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
40 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
X
(X)
A
FT
FT
A
A
R
R
D
D
D
001aac984
X
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
X
R
A
FT
D
R
X
A
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins and <tbd>.
Fig 21. Typical LOW-level output current IOL versus LOW-level output voltage VOL
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins.
Fig 22. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
41 of 67
D
D
D
D
D
R
R
R
R
R
FT
FT
FT
FT
FT
LPC81xM
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
X
(X)
A
FT
FT
A
A
R
R
D
D
D
001aac984
X
A
A
A
A
A
NXP Semiconductors
D
D
X
R
A
FT
D
R
X
A
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins.
Fig 23. Typical pull-up current Ipu versus input voltage VI
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins.
Fig 24. Typical pull-down current Ipd versus input voltage VI
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
42 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
11.1 Power-up ramp conditions
A
FT
FT
A
A
R
R
D
D
D
11. Dynamic characteristics
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
R
<tbd>
A
FT
D
R
11.2 Flash memory
A
Table 11. Flash characteristics
Tamb = 40 C to +85 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as
specified below.
Symbol
Parameter
Nendu
endurance
tret
retention time
ter
erase time
tprog
programming
time
Conditions
[2][1]
Min
Typ
Max
Unit
10000
100000
-
cycles
powered
[2]
10
20
-
years
unpowered
[2]
20
40
-
years
sector or multiple
consecutive
sectors
[2]
95
100
105
ms
0.95
1
1.05
ms
[2][3]
[1]
Number of program/erase cycles.
[2]
Min and max values are valid for Tamb = 40 C to +85 C only.
[3]
Programming times are given for writing <tbd> bytes to the flash. Tamb < +85 C. Data must be written to
the flash in blocks of 256 bytes. Flash programming is accomplished via IAP calls (see LPC800 user
manual). Execution time of IAP calls depends on the system clock and is typically between 1.5 and 2 ms
per 256 bytes.
11.3 External clock for the oscillator in slave mode and CLKIN
Remark: The input voltage on the XTAL1/2 pins must be  1.95 V (see Table 9). For
connecting the oscillator to the XTAL pins, also see Section 13.1.
Table 12. Dynamic characteristic: external clock (XTALIN or CLKIN inputs)
Tamb = 40 C to +85 C; VDD over specified ranges.[1]
LPC81xM
Objective data sheet
Min
Typ[2]
Max
Unit
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
Symbol
Parameter
fosc
Conditions
tCHCX
clock HIGH time
Tcy(clk)  0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk)  0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
43 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
W&+&;
W&/&+
D
D
R
7F\ FON
A
A
A
A
R
R
D
D
D
W&/&;
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
W&+&/
A
A
A
A
A
NXP Semiconductors
A
FT
D
R
DDD
A
Fig 25. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
11.4 Internal oscillators
Table 13. Dynamic characteristic: internal oscillators
Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V.[1]
Symbol
Parameter
Conditions
fosc(RC)
internal RC oscillator frequency -
Min
Typ[2]
Max
Unit
11.88
12
12.12
MHz
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: Frequency values are typical values. <tbd>.
Fig 26. Internal RC oscillator frequency versus temperature
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
44 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
D
R
A
FT
FT
FT
A
A
R
R
R
-
2300
-
F
[2][3]
A
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
R
-
Unit
D
D
R
kHz
FT
FT
A
A
9.4
Max
R
-
FT
internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1
frequency
in the WDTOSCCTRL register;
[2][3]
FT
A
A
R
R
D
D
D
fosc(int)
D
D
D
Typ[1]
Conditions
FT
FT
FT
FT
Min
Symbol Parameter
A
A
A
A
R
R
D
D
D
Dynamic characteristics: Watchdog oscillator
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Table 14.
A
A
A
A
A
NXP Semiconductors
D
D
R
A
kHz
FT
D
[2]
The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3]
See the LPC800 user manual.
Table 15.
Dynamic characteristics: Low-power oscillator
Symbol Parameter
fosc(int)
Conditions
[2][3]
internal oscillator
frequency
Min
Typ[1]
Max
Unit
-
9.4
-
kHz
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2]
The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3]
See the LPC800 user manual.
11.5 I/O pins
Table 16. Dynamic characteristics: I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin configured as output
3.0
-
5.0
ns
tf
fall time
pin configured as output
2.5
-
5.0
ns
[1]
LPC81xM
Objective data sheet
Applies to standard port pins and RESET pin.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
45 of 67
A
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
R
[1]
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
Table 17. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
11.6 I2C-bus
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
Conditions
Min
Max
Unit
fSCL
SCL clock
frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus; on
pins PIO0_10 and
PIO0_11
0
1
MHz
of both SDA and
SCL signals
-
300
ns
Fast-mode
20 + 0.1  Cb
300
ns
Fast-mode Plus;
on pins PIO0_10
and PIO0_11
-
120
ns
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus; on
pins PIO0_10 and
PIO0_11
0.5
-
s
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus; on
pins PIO0_10 and
PIO0_11
0.26
-
s
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus; on
pins PIO0_10 and
PIO0_11
0
-
s
D
Parameter
D
Symbol
R
A
FT
D
R
A
[4][5][6][7]
fall time
tf
Standard-mode
tLOW
tHIGH
tHD;DAT
tSU;DAT
[1]
LPC81xM
Objective data sheet
LOW period of
the SCL clock
HIGH period of
the SCL clock
data hold time
data set-up
time
[3][4][8]
[9][10]
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus; on
pins PIO0_10 and
PIO0_11
50
-
ns
See the I2C-bus specification UM10204 for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF.
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
46 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
LPC81xM
FT
D
R
R
FT
FT
FT
FT
32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
D
R
A
F
FT
FT
A
A
R
R
D
D
[8]
D
FT
FT
A
A
R
R
D
D
D
R
W+''$7
WI
6&/
W9''$7
W+,*+
W/2:
I6&/
6
DDD
Fig 27. I2C-bus pins clock timing
11.7 SPI interfaces
The maximum data bit rate is 30 Mbit/s in slave and master modes.
Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for
all digital pins except the open-drain pins PIO0_10 and PIO0_11.
Table 18. Dynamic characteristics of SPI pins
Tamb = 40 C to 85 C; CL = <tbd>; 1.8 V <= VDD <= 3.6 V. Simulated parameters; values guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
ns
SPI master (in SPI mode)
Tcy(clk)
tDS
clock cycle time
data set-up time
full-duplex mode
[1]
<tbd>
when only transmitting
[1]
<tbd>
in SPI mode
<tbd>
ns
-
-
ns
2.4 V  VDD  3.6 V
2.0 V  VDD < 2.4 V
<tbd>
1.8 V  VDD < 2.0 V
<tbd>
-
-
ns
tDH
data hold time
<tbd>
-
-
ns
tv(Q)
data output valid time in SPI mode
-
-
<tbd>
ns
th(Q)
data output hold time in SPI mode
<tbd>
-
-
ns
LPC81xM
Objective data sheet
in SPI mode
ns
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
47 of 67
A
R
D
6'$
W68'$7
FT
WI
A
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement
tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must
meet this set-up time.
D
D
D
D
D
R
R
R
R
R
D
R
R
FT
D
A
FT
FT
A
ns
tDH
data hold time
in SPI mode
[2]
<tbd>
-
-
ns
2.4 V  VDD  3.6 V
2.0 V  VDD < 2.4 V
<tbd>
1.8 V  VDD < 2.0 V
ns
<tbd>
-
-
ns
data output valid time in SPI mode
[2]
-
-
<tbd>
ns
data output hold time in SPI mode
[2]
-
-
<tbd>
ns
[1]
Tcy(clk) = <tbd>.
[2]
Tcy(clk) = 12  Tcy(PCLK).
7F\ FON
WFON +
WFON /
6&. &32/ 6&. &32/ WY 4
WK 4
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026,
'$7$9$/,'
W'6
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0,62
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026,
'$7$9$/,'
'$7$9$/,'
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0,62
&3+$ '$7$9$/,'
W'+
&3+$ '$7$9$/,'
DDD
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 28. SPI master timing in SPI mode
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
48 of 67
A
-
R
-
D
ns
<tbd>
D
-
[2]
FT
-
in SPI mode
A
<tbd>
data set-up time
R
PCLK cycle time
D
Tcy(PCLK)
tDS
th(Q)
F
R
R
Unit
D
D
SPI slave (in SPI mode)
tv(Q)
A
FT
FT
A
A
R
R
R
Max
R
A
D
D
Typ
D
R
FT
FT
A
A
R
R
D
D
D
Min
FT
FT
FT
FT
Conditions
A
A
A
A
R
R
D
D
D
Table 18. Dynamic characteristics of SPI pins
Tamb = 40 C to 85 C; CL = <tbd>; 1.8 V <= VDD <= 3.6 V. Simulated parameters; values guaranteed by design.
Parameter
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Symbol
A
A
A
A
A
NXP Semiconductors
D
D
D
D
D
R
R
R
R
R
D
R
R
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
WFON /
A
A
A
A
R
R
D
D
D
WFON +
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
7F\ FON
A
A
A
A
A
NXP Semiconductors
D
FT
FT
A
A
R
R
D
6&. &32/ D
D
R
A
FT
D
6&. &32/ '$7$9$/,'
W'+
A
026,
R
W'6
'$7$9$/,'
WY 4
0,62
WK 4
'$7$9$/,'
W'6
026,
'$7$9$/,'
W'+
'$7$9$/,'
WY 4
0,62
'$7$9$/,'
&3+$ '$7$9$/,'
WK 4
&3+$ '$7$9$/,'
DDD
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 29. SPI slave timing in SPI mode
11.8 USART interface
The maximum USART bit rate is 1.875 Mbit/s in asynchronous mode and 30 Mbit/s in
synchronous mode slave and master mode.
Remark: USART functions can be assigned to all digital pins. The characteristics are valid
for all digital pins except the open-drain pins PIO0_10 and PIO0_11.
Table 19. Dynamic characteristics: USART interface in synchronous master mode
Tamb = 40 C to 85 C; 1.8 V  VDD  3.6 V; CL = <tbd> pF. Simulated values.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tcy(clk)
clock cycle time
on pins Ux_SCLK
-
<tbd>
-
s
data output valid time
on pin Ux_TXD
-
<tbd>
-
ns
output
tv(Q)
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
49 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
12.1 BOD
A
FT
FT
A
A
R
R
D
D
D
12. Analog characteristics
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
R
Table 20. BOD static characteristics[1]
Tamb = 25 C.
A
FT
D
Conditions
threshold voltage
interrupt level 1
Min
Typ
Max
Unit
assertion
-
<tbd>
-
V
de-assertion
-
<tbd>
-
V
assertion
-
<tbd>
-
V
de-assertion
-
<tbd>
-
V
assertion
-
<tbd>
-
V
de-assertion
-
<tbd>
-
V
assertion
-
<tbd>
-
V
de-assertion
-
<tbd>
-
V
assertion
-
<tbd>
-
V
de-assertion
-
<tbd>
-
V
assertion
-
<tbd>
-
V
de-assertion
-
<tbd>
-
V
assertion
-
<tbd>
-
V
de-assertion
-
<tbd>
-
V
interrupt level 2
interrupt level 3
reset level 0
reset level 1
reset level 2
reset level 3
[1]
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL.
12.2 POR
Table 21. POR static characteristics
Tamb = 25 C.
Symbol
Vth
Parameter
Conditions
VDD falling<tbd>
LPC81xM
Objective data sheet
Min
Typ
Max
Unit
-
<tbd>
-
V
VDD rising<tbd>
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Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
50 of 67
A
Parameter
R
Symbol
Vth
D
D
D
D
D
R
R
R
R
R
D
R
R
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
Max
Unit
D
Typ
D
Min
FT
Conditions
FT
A
A
R
R
D
Parameter
FT
FT
FT
FT
Table 22. Comparator characteristics
VDD(3V3)= 3.0 V and Tamb = 25 C unless noted otherwise.
A
A
A
A
R
R
D
D
D
12.3 Comparator
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Symbol
A
A
A
A
A
NXP Semiconductors
R
A
<tbd>
-
A
VIC
common-mode input voltage
0
-
VDD
V
DVO
output voltage variation
0
-
VDD
V
Voffset
offset voltage
VIC = 0.1 V
-
<tbd>
-
mV
VIC = 1.5 V
-
<tbd>
-
mV
VIC = 2.8 V
-
<tbd>
A
-
R
supply current
D
IDD
FT
Static characteristics
mV
Dynamic characteristics
tstartup
start-up time
nominal process
-
<tbd>
-
tPD
propagation delay
HIGH to LOW; VDD(3V3) = 3.0 V;
-
<tbd>
<tbd>
propagation delay
tPD
s
VIC = 0.1 V; 50 mV overdrive input
[1]
VIC = 0.1 V; rail-to-rail input
[1]
-
<tbd>
<tbd>
ns
VIC = 1.5 V; 50 mV overdrive input
[1]
-
<tbd>
<tbd>
ns
VIC = 1.5 V; rail-to-rail input
[1]
-
<tbd>
<tbd>
ns
VIC = 2.9 V; 50 mV overdrive input
[1]
-
<tbd>
<tbd>
ns
VIC = 2.9 V; rail-to-rail input
[1]
-
<tbd>
<tbd>
ns
-
<tbd>
<tbd>
LOW to HIGH; VDD(3V3) = 3.0 V;
ns
VIC = 0.1 V; 50 mV overdrive input
[1]
VIC = 0.1 V; rail-to-rail input
[1]
-
<tbd>
<tbd>
ns
VIC = 1.5 V; 50 mV overdrive input
[1]
-
<tbd>
<tbd>
ns
VIC = 1.5 V; rail-to-rail input
[1]
-
<tbd>
<tbd>
ns
VIC = 2.9 V; 50 mV overdrive input
[1]
-
<tbd>
<tbd>
ns
VIC = 2.9 V; rail-to-rail input
[1]
ns
-
<tbd>
<tbd>
ns
Vhys
hysteresis voltage
positive hysteresis; VDD(3V3) = 3.0 V;
VIC = 1.5 V
[2]
-
<tbd>
-
mV
Vhys
hysteresis voltage
negative hysteresis; VDD(3V3) = 3.0 V;
VIC = 1.5 V
[2]
-
<tbd>
-
mV
Rlad
ladder resistance
-
-
<tbd>
-
M
[1]
CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to
+85 C.
[2]
Input hysteresis is relative to the reference input channel and is software programmable.
Table 23.
Symbol
LPC81xM
Objective data sheet
Comparator voltage ladder dynamic characteristics
Parameter
Conditions
ts(pu)
power-up settling
time
to 99% of voltage
ladder output
value
[1]
ts(sw)
switching settling
time
to 99% of voltage
ladder output
value
[1]
Typ
Max
Unit
-
-
<tbd>
s
-
-
<tbd>
s
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
Min
© NXP B.V. 2012. All rights reserved.
51 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
Settling time applies to switching between comparator channels<tbd>.
Unit
D
R
A
%
-
<tbd>
<tbd>
%
decimal code = 16
-
<tbd>
<tbd>
%
decimal code = 24
-
<tbd>
<tbd>
%
decimal code = 30
-
<tbd>
<tbd>
%
decimal code = 31
-
<tbd>
<tbd>
%
<tbd>
<tbd>
decimal code = 00
-
decimal code = 08
-
<tbd>
<tbd>
%
decimal code = 16
-
<tbd>
<tbd>
%
decimal code = 24
-
<tbd>
<tbd>
%
decimal code = 30
-
<tbd>
<tbd>
%
decimal code = 31
-
<tbd>
<tbd>
%
Measured <tbd> with a 2 kHz input signal and overdrive < 100 V.
[2]
All peripherals except comparator, temperature sensor, and IRC turned off.
D
<tbd>
decimal code = 08
[1]
%
13. Application information
13.1 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
/3&
;7$/,1
&L
S)
&J
DDD
Fig 30. Slave mode operation of the on-chip oscillator
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
F
<tbd>
FT
Max[1]
A
Typ
-
External VDDCMP
supply
FT
R
output voltage error
D
EV(O)
[2]
FT
decimal code = 00
A
A
Internal VDD(3V3) supply
A
R
R
output voltage error
R
D
D
Table 24. Comparator voltage ladder reference static characteristics
VDD(3V3) = 3.3 V; Tamb = -40 C to + 85C.
EV(O)
D
FT
FT
A
A
R
R
D
D
[2]
Min
FT
FT
FT
FT
Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 85 C; slow process models).
Conditions
A
A
A
A
R
R
D
D
D
[1]
Parameter
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Symbol
A
A
A
A
A
NXP Semiconductors
© NXP B.V. 2012. All rights reserved.
52 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
LPC81xM
FT
D
R
R
FT
FT
FT
FT
32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 30), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
D
FT
FT
A
A
R
R
D
D
D
R
A
External components and models used in oscillation mode are shown in Figure 31 and in
Table 25 and Table 26. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 31 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer (see Table 25).
&3
56
&;
&;
DDD
Fig 31. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 25.
Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
1 MHz - 5 MHz
10 pF
< 300 
18 pF, 18 pF
20 pF
< 300 
39 pF, 39 pF
30 pF
< 300 
57 pF, 57 pF
10 pF
< 300 
18 pF, 18 pF
20 pF
< 200 
39 pF, 39 pF
30 pF
< 100 
57 pF, 57 pF
10 pF
< 160 
18 pF, 18 pF
20 pF
< 60 
39 pF, 39 pF
10 pF
< 80 
18 pF, 18 pF
5 MHz - 10 MHz
10 MHz - 15 MHz
15 MHz - 20 MHz
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
53 of 67
A
&/
;7$/
R
;7$/287
D
/
;7$/,1
FT
/3&
D
D
D
D
D
R
R
R
R
R
D
R
R
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
10 pF
< 180 
18 pF, 18 pF
20 pF
< 100 
39 pF, 39 pF
10 pF
< 160 
18 pF, 18 pF
20 pF
< 80 
39 pF, 39 pF
R
15 MHz - 20 MHz
FT
FT
A
A
R
External load
capacitors CX1, CX2
D
D
R
A
FT
D
R
A
13.2 XTAL Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
13.3 ElectroMagnetic Compatibility (EMC)
Radiated emission measurements according to the IEC61967-2 standard using the
TEM-cell method are shown for the LPC800<tbd> in Table 27.
Table 27. ElectroMagnetic Compatibility (EMC) for part LPC800<tbd> (TEM-cell method)
VDD = 3.3 V; Tamb = 25 C.
System clock =
Unit
12 MHz
24 MHz
48 MHz
150 kHz to 30 MHz
<tbd>
<tbd>
<tbd>
dBV
30 MHz to 150 MHz
<tbd>
<tbd>
<tbd>
dBV
150 MHz to 1 GHz
<tbd>
<tbd>
<tbd>
dBV
-
<tbd>
<tbd>
<tbd>
-
Input clock: IRC (12 MHz)
IEC
level[1]
Input clock: crystal oscillator (12 MHz)
maximum
peak level
IEC level[1]
[1]
LPC81xM
Objective data sheet
150 kHz to 30 MHz
<tbd>
<tbd>
<tbd>
dBV
30 MHz to 150 MHz
<tbd>
<tbd>
<tbd>
dBV
150 MHz to 1 GHz
<tbd>
<tbd>
<tbd>
dBV
-
<tbd>
<tbd>
<tbd>
-
IEC levels refer to Appendix D in the IEC61967-2 Specification.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
F
D
D
Maximum crystal
series resistance RS
maximum
peak level
A
FT
FT
A
A
R
R
D
D
D
Crystal load
capacitance CL
Frequency band
FT
FT
FT
FT
Fundamental oscillation
frequency FOSC
Parameter
A
A
A
A
R
R
D
D
D
Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
20 MHz - 25 MHz
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Table 26.
A
A
A
A
A
NXP Semiconductors
© NXP B.V. 2012. All rights reserved.
54 of 67
D
D
D
D
D
R
R
R
R
R
FT
FT
FT
FT
FT
LPC81xM
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
14. Package outline
A
A
A
A
A
NXP Semiconductors
D
A
A
R
R
D
FT
SOT97-2
FT
DIP8: plastic dual in-line package; 8 leads (300 mil)
D
D
R
A
FT
D
R
seating plane
ME
A2
A
D
A
A1
L
c
e
Z
w
b1
(e1)
b
MH
b2
8
5
pin 1 index
E
1
4
0
2.5
5 mm
scale
Dimensions (inch dimensions are derived from the original dimensions)
Unit(1)
mm
max
nom
min
A
A1
4.2
A2
b
3.43 1.73
b1
b2
c
D(1)
E(1)
0.53
1.07
0.38
9.8
6.48
e
e1
L
ME
MH
3.60 7.88 9.40
2.54 7.62
0.51
1.14
0.38
0.89
0.20
9.2
Z(1)
1.15
0.254
3.05 7.62 7.88
6.20
0.14 0.068 0.021 0.042 0.015 0.39 0.26
max 0.17
inches nom
0.045 0.015 0.035 0.008 0.36 0.24
min
0.02
w
0.14 0.31 0.37
0.1
0.045
0.01
0.3
0.12 0.30 0.31
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included
References
Outline
version
IEC
JEDEC
JEITA
SOT97-2
---
MO-001
---
sot097-2_po
European
projection
Issue date
10-10-15
10-10-18
Fig 32. Package outline SOT097-2 (DIP8)
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
55 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
LPC81xM
FT
D
R
R
FT
FT
FT
FT
32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
A
A
R
R
D
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
FT
SOT403-1
D
D
R
A
FT
D
R
A
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 33. Package outline SOT403-1 (TSSOP16)
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
56 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
LPC81xM
FT
D
R
R
FT
FT
FT
FT
32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
A
A
R
R
D
SO20: plastic small outline package; 20 leads; body width 7.5 mm
FT
SOT163-1
D
D
R
A
FT
D
R
A
D
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
10
1
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 34. Package outline SOT163-1 (SO20)
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
57 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
FT
FT
FT
FT
LPC81xM
FT
D
R
R
FT
FT
FT
FT
32-bit ARM Cortex-M0+ microcontroller
A
A
A
A
R
R
D
D
D
NXP Semiconductors
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
A
A
R
R
D
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
FT
SOT360-1
D
D
R
A
FT
D
R
A
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 35. Package outline SOT360-1 (TSSOP20)
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
58 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
15. Soldering
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
FT
FT
A
A
R
R
D
Footprint information for reflow soldering of TSSOP20 package
D
D
SOT360-1
R
A
FT
D
R
A
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
6.900
5.300
7.300
7.450
sot360-1_fr
Fig 36. Reflow soldering of the TSSOP16 package
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
59 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
FT
FT
A
A
R
R
D
0.60 (20×)
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
13.40
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
D
D
R
A
1.50
FT
D
R
A
8.00
11.00 11.40
1.27 (18×)
solder lands
occupied area
placement accuracy ± 0.25
Dimensions in mm
sot163-1_fr
Fig 37. Reflow soldering of the SO20 package
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
60 of 67
D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
Footprint information for reflow soldering of TSSOP20 package
FT
FT
FT
FT
LPC81xM
FT
NXP Semiconductors
SOT360-1
D
FT
FT
A
A
R
R
D
D
D
R
A
FT
D
R
A
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
6.900
5.300
7.300
7.450
sot360-1_fr
Fig 38. Reflow soldering of the TSSOP20 package
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
61 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
FT
D
R
A
Universal Asynchronous Receiver/Transmitter
D
UART
17. References
[1]
LPC81xM
Objective data sheet
I2C-bus specification UM10204.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
F
Transverse ElectroMagnetic
FT
TEM
FT
System Management Bus
A
SMBus
A
Serial Peripheral Interface
R
Resistor-Capacitor
SPI
R
RC
D
Phase-Locked Loop
D
PLL
FT
General-Purpose Input/Output
A
GPIO
R
BrownOut Detection
D
Advanced Peripheral Bus
BOD
A
FT
FT
APB
R
A
A
Advanced High-performance Bus
D
R
R
AHB
R
A
D
D
Description
D
R
FT
FT
A
A
R
R
D
D
D
Acronym
FT
FT
FT
FT
Abbreviations
A
A
A
A
R
R
D
D
D
Table 28.
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
16. Abbreviations
A
A
A
A
A
NXP Semiconductors
© NXP B.V. 2012. All rights reserved.
62 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
FT
FT
FT
FT
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
FT
FT
A
A
R
R
D
D
D
D
LPC81xM v.1
<tbd>
Objective data sheet
-
A
FT
-
D
Change notice Supersedes
R
Data sheet status
D
Release date
FT
Document ID
FT
A
A
R
R
D
Revision history
A
A
A
A
R
R
D
D
D
18. Revision history
FT
FT
FT
FT
FT
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Table 29.
A
A
A
A
A
NXP Semiconductors
D
R
A
LPC81xM
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
63 of 67
D
D
D
D
D
R
R
R
R
R
FT
FT
FT
FT
FT
LPC81xM
D
R
R
FT
FT
FT
FT
A
A
A
A
R
R
D
D
D
32-bit ARM Cortex-M0+ microcontroller
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
F
D
FT
FT
A
A
R
R
D
19.1 Data sheet status
A
FT
FT
A
A
R
R
D
D
D
19. Legal information
A
A
A
A
A
NXP Semiconductors
D
D
R
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
A
Document status[1][2]
FT
D
R
A
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
LPC81xM
Objective data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
64 of 67
D
D
D
D
D
R
R
R
R
R
D
R
R
D
R
R
A
FT
FT
FT
A
A
R
R
D
D
D
R
A
F
D
FT
FT
A
A
R
R
D
D
D
R
A
FT
D
19.4 Trademarks
For sales office addresses, please send an email to: [email protected]
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
65 of 67
A
I2C-bus — logo is a trademark of NXP B.V.
R
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
For more information, please visit: http://www.nxp.com
Objective data sheet
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whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
20. Contact information
LPC81xM
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In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
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Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
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NXP Semiconductors
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© NXP B.V. 2012. All rights reserved.
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Rev. 1.0 — 7 November 2012
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All information provided in this document is subject to legal disclaimers.
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Internal Low-Frequency Oscillator (LFOsc) and
Watchdog Oscillator (WDOsc) . . . . . . . . . . . . 23
7.20.2
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.20.3
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.20.4
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.20.5
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 24
7.20.6
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.20.6.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 24
7.20.6.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.20.6.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 25
7.20.6.4 Power-down mode . . . . . . . . . . . . . . . . . . . . . 25
7.20.6.5 Deep power-down mode . . . . . . . . . . . . . . . . 25
7.21
System control . . . . . . . . . . . . . . . . . . . . . . . . 26
7.21.1
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.21.2
Brownout detection . . . . . . . . . . . . . . . . . . . . 26
7.21.3
Code security (Code Read Protection - CRP) 26
7.21.4
APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.21.5
AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.22
Emulation and debugging . . . . . . . . . . . . . . . 28
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29
9
Thermal characteristics . . . . . . . . . . . . . . . . . 30
10
Static characteristics . . . . . . . . . . . . . . . . . . . 31
10.1
Power consumption . . . . . . . . . . . . . . . . . . . . 35
10.2
CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 38
10.3
Peripheral power consumption . . . . . . . . . . . 39
10.4
Electrical pin characteristics. . . . . . . . . . . . . . 40
11
Dynamic characteristics. . . . . . . . . . . . . . . . . 43
11.1
Power-up ramp conditions . . . . . . . . . . . . . . . 43
11.2
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 43
11.3
External clock for the oscillator in slave mode and
CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11.4
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 44
11.5
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.6
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.7
SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 47
11.8
USART interface . . . . . . . . . . . . . . . . . . . . . . 49
12
Analog characteristics . . . . . . . . . . . . . . . . . . 50
12.1
BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.2
POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.3
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13
Application information . . . . . . . . . . . . . . . . . 52
13.1
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2
XTAL Printed Circuit Board (PCB) layout
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3
ElectroMagnetic Compatibility (EMC) . . . . . . 54
14
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 55
continued >>
LPC81xM
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7.20.1.3
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General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7
Functional description . . . . . . . . . . . . . . . . . . 11
7.1
ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . 11
7.2
On-chip flash program memory . . . . . . . . . . . 11
7.3
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 11
7.4
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.5
Nested Vectored Interrupt Controller (NVIC) . 11
7.5.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.5.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 11
7.6
System tick timer . . . . . . . . . . . . . . . . . . . . . . 12
7.7
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.8
I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 13
7.8.1
Standard I/O pad configuration . . . . . . . . . . . . 14
7.9
Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 15
7.10
Fast General-Purpose parallel I/O (GPIO) . . . 15
7.10.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.11
Pin interrupt/pattern match engine . . . . . . . . . 16
7.11.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.12
USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.12.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.13
SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.13.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.14
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 18
7.14.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.15
State-Configurable Timer (SCT) . . . . . . . . . . . 19
7.15.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.16
Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 19
7.16.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.17
Windowed WatchDog Timer (WWDT) . . . . . . 19
7.17.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.18
Self Wake-up Timer (WKT). . . . . . . . . . . . . . . 20
7.18.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.19
Analog comparator (ACMP) . . . . . . . . . . . . . . 20
7.19.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.20
Clocking and power control . . . . . . . . . . . . . . 22
7.20.1
Crystal and internal oscillators . . . . . . . . . . . . 22
7.20.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 23
7.20.1.2 Crystal Oscillator (SysOsc). . . . . . . . . . . . . . . 23
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32-bit ARM Cortex-M0+ microcontroller
21. Contents
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Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller
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19.1
19.2
19.3
19.4
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NXP Semiconductors
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 7 November 2012
Document identifier: LPC81xM