MPS MP8049S 24v, 5.5a quad channel power half-bridge Datasheet

MP8049S
The Future of Analog IC Technology
24V, 5.5A
Quad Channel Power Half-Bridge
DESCRIPTION
FEATURES
The MP8049S is a configurable dual channel
full-bridge or quad channel half-bridge that can
be configured as the output stage of a Class-D
audio amplifier. Each full-bridge can be driven
independently as stereo single ended audio
amplifiers or driven complementary in a bridge
tied load (BTL) audio amplifier configuration.
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The MP8049S features a low current shutdown
mode, standby mode, input under voltage
protection, current limit, thermal shutdown and
fault flag signal output. All channels of drivers
interface with standard logic signals.
The MP8049S is available in a 40 lead QFN
5X5 package.
5V to 26V VDD
±5.5A Peak Current Output
Up to 1MHz Switching Frequency
Protected Integrated Power 0.14Ω Switches
10ns Switch Dead Time
All Switches Current Limited
Internal Under Voltage Protection
Internal Thermal Protection
Short-circuit Protection
Fault Output Flag
Bridge Tied Load Output Power:
37W/Channel at 24V, 8Ω
APPLICATIONS
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Flat TV
Home Theaters
DVD Receivers
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
1
MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP8049SDU
QFN40 (5x5mm)
MP8049S
* For Tape & Reel, add suffix –Z (e.g. MP8049SDU–Z).
For RoHS Compliant Packaging, add suffix –LF (e.g. MP8049SDU–LF–Z)
PACKAGE REFERENCE
VDR2
34
PGND2A
AGND
35
PGND2A
AGND
36
31
VDR1
37
32
BST1B
38
BST2A
PGND1B
39
33
PGND1B
40
TOP VIEW
28
VSP2
VSP1
4
27
VSP2
VSP1
5
26
VSP2
SW1A
6
25
SW2B
SW1A
7
24
SW2B
PGND1A
8
23
PGND2B
PGND1A
9
22
PGND2B
BST1A
10
21
BST2B
ABSOLUTE MAXIMUM RATINGS (1)
VSP Supply Voltage .................................... 28V
SW1/2 Pin Voltage ............... -0.3V to VDD + 0.3V
SW1/2 to BST1/2 ............................-0.3V to +6V
Voltage at All Other Pins .................-0.3V to +6V
(2)
Continuous Power Dissipation.. (TA = +25°C)
………………………………………….… ...4.2W
Storage Temperature ............... -55C to +150C
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Recommended Operating Conditions
(3)
FLT2B 20
3
FLT3B 19
VSP1
PWM2B 18
SW2A
STBYB 17
29
PWM2A 16
2
SHDNB 15
SW1B
FAULTB 14
SW2A
PWM1B 13
30
PWM1A 12
1
N/C 11
SW1B
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of
the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
VSP Supply Voltage ........................... 5V to 26V
Operating Junction Temp. (TJ) . -40°C to +125°C
Thermal Resistance
(4)
θJA
θJC
QFN40 (5 x 5mm) ................... 36 ....... 8 .... C/W
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
ELECTRICAL CHARACTERISTICS
VSP = 12V, VSHDNB = 5V, TA = +25C, unless otherwise specified.
Parameters
Symbol Condition
Min
Typ
Max
Units
VSP Operating Current
ILOAD = 0A，PWM1,2=0
2.2
3.5
mA
VSP Shutdown Current
Operating VSP Threshold Low
VSHDN = 0V
24
4
30
uA
V
4.4
4.8
V
3.7
Operating VSP Threshold High
STBYB Threshold Low
STBYB Threshold High
PWM Input Bias Current
SHDNB Threshold Low
SHDNB Threshold High
PWM1,2 Threshold Low
PWM1,2 Threshold High
SW1/2 On Resistance
(5)
SW1/2 Current Limit (5)
SW1/2 Switching Frequency
BST Voltage UVLO
BST Current
SW1/2 Rise/Fall Time (5)
Minimum PWM Pulse Width
(5)
Dead Time
PWM1,2 to SW1,2 Delay Time
Rising
PWM1,2 to SW1,2 Delay Time
Falling
Thermal Shutdown Temperature (5)
Thermal Shutdown Hysteresis
0.8
0.8
0.8
VSP = 7V, High-Side and LowSide
VPWM = 0V, Sinking
VPWM = 5V, Sourcing
VPWM = 0 to 5V, 50% Duty Cycle
falling value
High-Side MOSFET on, VBSTVSW=5.5V
VPWM = 0V to 5V
VPWM = 0V to 5V, High or Low
Pulse
IOUT= ±100mA
1.0
1.6
0.1
1.0
1.6
1
1.6
1.8
1.0
1.8
1.8
V
V
µA
V
V
V
V
0.14
Ω
5.5
5.5
2.2
A
A
MHz
V
30
µA
5
ns
30
ns
10
ns
VPWM = 0V to 5V
30
ns
VPWM = 5V to 0V
30
ns
TJ Rising
150
C
25
C
1
Notes:
5) Not production tested.
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
OPERATING SPECIFICATIONS (6)
VSP = 18V, VSHDNB = 5V, VSTBYB = 5V, Bridge-tied-load output configuration, TA = +25C, unless
otherwise specified.
Parameters
Symbol Condition
VSP=18V, f = 1kHz, THD+N < 1%,
RL = 6Ω
PO
VSP=24V, f = 1kHz, THD+N < 1%,
RL = 8Ω
VSP=18V/24V, f = 1kHz, PO = 1W,
RL = 8Ω/6Ω
VSP=24V, f = 1kHz, PO = 35W, 8Ω
Load
PO =15W, RL = 8Ω/6Ω, A-Weighted
A-Weighted
Power Output
THD+ Noise
Efficiency
SNR
Noise Floor
Cross Talk
Power Supply Rejection
VRIPPLE=200mVPP
CSP=1μF
Min
Typ
Max
Units
20
W
30
W
0.1
%
92
%
100
100
-80
dB
μV
dB
f = 1k Hz
-70
dB
f = 217 Hz
-70
dB
Note:
6) Operating Specifications are for the IC in Typical Application circuit.
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
PIN FUNCTIONS
Pin #
1,2
3,4,5
6,7
8,9
10
11
12
13
14
15
16
17
18
Name
Description
Switched Output 1B. Connect the output LC filter to SW1B. SW1B is valid approximately
SW1B
100µs after VSP goes high.
Power Supply Input. Connect VSP1 to the positive side of the input power supply. Bypass
VSP1
VSP1 to PGND as close to the IC as possible.
Switched Output 1A. Connect the output LC filter to SW1A. SW1A is valid approximately
SW1A
100µs after VSP goes high.
Power Ground of channel 1A. Connect the exposed pad on bottom side to the ground
PGND1A
plane.
Bootstrap Supply. BST1A powers the high-side gate of the SW1A stage. Connect a 0.1μF
BST1A
or greater capacitor between BST1A and SW1A.
N/C
No connect.
Driver Logic Input 1A. Drive PWM1 with the signal that controls the MP8049S SW1A. Drive
PWM1A
PWM high to turn on the high side switch; drive PWM low to turn on the low-side switch.
Driver Logic Input 1B. Drive PWM1 with the signal that controls the MP8049S SW1B. Drive
PWM1B
PWM high to turn on the high side switch; drive PWM low to turn on the low-side switch.
FAULTB Fault Output. A low output at FAULT indicates that the MP8049S has detected an over
temperature or over current or under voltage condition. This output is open drain.
SHDNB Shutdown Input. When low, the IC will be shut off.
Driver Logic Input 2A. Drive PWM2 with the signal that controls the MP8049S SW2A. Drive
PWM2A
PWM high to turn on the high side switch; drive PWM low to turn on the low-side switch.
Standby Input. Default low (internal pull-down). If driven high, the output of the drivers is
STBYB determined by the PWM1A/1B/2A/2B. If driven low, the output of both drivers is high
impedance.
Driver Logic Input 2B. Drive PWM2 with the signal that controls the MP8049S SW2B. Drive
PWM2B
PWM high to turn on the high side switch; drive PWM low to turn on the low-side switch.
19
FLT3B
Fault monitor pin. Detailed please see the Fault Output section. This output is open drain.
20
FLT2B
Fault monitor pin. Detailed please see the Fault Output section. This output is open drain.
21
22, 23
24, 25
26,27,
28
29, 30
Bootstrap Supply. BST2B powers the high-side gate of the SW2B stage. Connect a 0.1μF
or greater capacitor between BST2B and SW2B.
Power Ground of Channel 2B. Connect the exposed pad on the bottom side to the ground
PGND2B
plane.
Switched Output 2B. Connect the output LC filter to SW2B. SW2B is valid approximately
SW2B
100µs after VSP goes high.
Power Supply Input. Connect VSP2 to the positive side of the input power supply. Bypass
VSP2
VSP2 to PGND as close to the IC as possible.
Switched Output 2A. Connect the output LC filter to SW2A. SW2A is valid approximately
SW2A
100µs after VSP goes high.
BST2B
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
PIN FUNCTIONS (continued)
Pin #
31, 32
33
34
35, 36
37
38
39,40
Name
Description
Power Ground of channel 2A. Connect the exposed pad on bottom side to the ground
PGND2A
plane.
Bootstrap Supply. BST2A powers the high-side gate of the SW2A stage. Connect a 0.1μF
BST2A
or greater capacitor between BST2A and SW2A.
Gate Drive Supply Bypass. The voltage at VDR2 is supplied from an internal regulator from
VDR2 its respective VSP. VDR2 powers the internal circuitry and internal MOSFET gate drive for
its respective SW2 stage. Bypass VDR2 to PGND with a 0.1μF to 10μF capacitor.
AGND Analog Ground.
Gate Drive Supply Bypass. The voltage at VDR1 is supplied from an internal regulator from
VDR1 its respective VSP. VDR1 powers the internal circuitry and internal MOSFET gate drive for
its respective SW1 stage. Bypass VDR1 to PGND with a 0.1μF to 10μF capacitor.
Bootstrap Supply. BST1B powers the high-side gate of the SW1B stage. Connect a 0.1μF
BST1B
or greater capacitor between BST1B and SW1B.
Power Ground of Channel 1B. Connect the exposed pad on bottom side to the ground
PGND1B
plane.
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
TYPICAL PERFORMANCE CHARACTERISTICS
VSP = 24V, VSHDNB = 5V, RLOAD = 8Ω, Bridge-tied-load output configuration, TA = +25ºC, unless
otherwise noted.
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VSP = 18V, VSHDNB = 5V, RLOAD = 6Ω, Bridge-tied-load output configuration, TA = +25ºC, unless
otherwise noted.
M8049S Rev. 1.0
9/28/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VSP = 24V, VSHDNB = 5V, RLOAD = 8Ω, Bridge-tied-load output configuration, TA = +25ºC, unless
otherwise noted.
M8049S Rev. 1.0
9/28/2012
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
OPERATION
5V
The MP8049S is a quad channel power halfbridge driver that can be configured as the output
of a Class D amplifier. The output is in phase
with the input and the dead time is optimized for
symmetrical performance, regardless of load
conditions.
When the shutdown (SHDN) pin is low, all
channels will be off. When the standby (STBYB)
is pulled low, it causes the outputs of all channels
to go into high impedance. However, when the
voltage across the BST1A/1B/2A/2B and
SW1A/1B/2A/2B pins drops sufficiently low, the
bottom MOSFET will be turned on to refresh the
external bootstrap capacitor. Suggest connect a
0.1μF or greater capacitor between BST and SW
pins as the bootstrap capacitor.
In order to prevent erratic operation, two under
voltage lockout (UVLO) circuits are used. One of
them is to ensure that the supply for the bottom
gate drive circuit is sufficiently high and the other
is for the top gate driver.
Fault Protection
To protect the power MOSFETs, an internal
current limit of 5.5A is set for all MOSFETs.
When this limit is reached, all four MOSFETs of
the over current full bridge channel will go into
high impedance for a fixed duration of
approximately 30us before resuming normal
operation.
Thermal monitoring is also integrated into the
MP8049S. If the die temperature rises above
150ºC, all switches are turned off. The
temperature must fall below 125ºC before normal
operation resumes.
To enhance the robustness of the device under
short circuit condition, a capacitor can be
connected to the FaultB pin, as shown in figure 1.
The time constant of the RC is selected to be
greater than 50ms for the FaultB node to reach
2V. Under short circuit condition, the FaultB node
will be reset to zero and the part will be place in
standby mode until the voltage at the STBYB pin
is above 2V.
M8049S Rev. 1.0
9/28/2012
MP8049S
R
FAULTB
C
STBYB
Figure 1—Fault Protection Enhancement
Circuit
Fault Output
The MP8049S includes an open drain, active low
fault indicator output (FAULTB). A fault will be
indicated if one of the following conditions is
detected: the current limit is tripped, or the
thermal shutdown is tripped.
A fault on any channel will cause the FAULTB pin
to be pulled low. When the fault goes away, the
MP8049S will resume normal operation.
Do not apply more than 6V to the FAULTB pin.
Error Reporting
The MP8049S also have two fault monitor pins
(FLT3B and FLT2B), which are active low and
open-drain outputs. Their function is for
protection-mode signaling to a PWM controller or
other system control device, as shown in the
below table.
OCP
0
0
0
1
OTP
0
0
1
0
UVP
0
1
0
0
FLTB2
1
0
1
0
FLTB3
1
1
0
0
Table 1- Fault Boolean
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
BLOCK DIAGRAM
VSP1
BST1A
VSP1
VDR1
REGULATOR
HIGH-SIDE
DRIVER
AGND
OVER
CURRENT
SENSE
SW1A
LOW -SIDE
DRIVER
PWM1A
LOGIC
CONTROL
PWM1B
BST1B
VSP1
SHDNB
STBYB
FAULT
HANDLING
AND
CONTROL
FAULTB
HIGH-SIDE
DRIVER
OVER
CURRENT
SENSE
FLT3B
SW1B
FLT2B
THERMAL
SHUTDOWN
LOW-SIDE
DRIVER
Figure 2—Function Block Diagram (1 full bridge channel only)
M8049S Rev. 1.0
9/28/2012
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© 2012 MPS. All Rights Reserved.
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MP8049S - 24V, 5.5A QUAD CHANNEL POWER HALF-BRIDGE
PACKAGE INFORMATION
QFN 40 (5x5mm)
3.50
3.80
4.90
5.10
PIN 1 ID
MARKING
31
PIN 1 ID
SEE DETAIL A
40
1
30
0.40
BSC
4.90
5.10
PIN 1 ID
INDEX AREA
3.50
3.80
0.15
0.25
21
0.35
0.45
TOP VIEW
10
20
11
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.25 TYP.
0.80
1.00
0.20
REF
0.00
0.05
DETAIL A
SIDE VIEW
4.90
3.70
0.70
0.20
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE0.10 MILLIMETER MAX.
4) DRAWING CONFIRMS TO JEDEC MO-220, VARIATION VHHE-1.
5) DRAWING IS NOT TO SCALE.
0.40
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
M8049S Rev. 01.0
www.MonolithicPower.com
9/28/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
12