ATMEL AT45DB011 1-megabit 2.7-volt only serial dataflash Datasheet

Features
• Single 2.7V - 3.6V Supply
• Serial Interface Architecture
• Page Program Operation
•
•
•
•
•
•
•
•
•
•
•
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
Optional Page and Block Erase Operations
One 264-byte SRAM Data Buffer
Internal Program and Control Timer
Fast Page Program Time – 7 ms Typical
120 µs Typical Page to Buffer Transfer Time
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
13 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
1-megabit
2.7-volt Only
Serial
DataFlash®
Description
AT45DB011
The AT45DB011 is a 2.7-volt only, serial interface Flash memory suitable for
in-system reprogramming. Its 1,081,344 bits of memory are organized as 512 pages
of 264 bytes each. In addition to the main memory, the AT45DB011 also contains one
SRAM data buffer of 264 bytes. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
Recommend using
AT45DB011B for new
designs.
(continued)
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Clock
SI
Serial Input
SO
Serial Output
WP
Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY
Ready/Busy
SOIC
SI
SCK
RESET
CS
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
DC
DC
NC
NC
NC
SCK
SI
SO
NC
NC
NC
NC
NC
NC
8
7
6
5
SO
GND
VCC
WP
TSSOP Top View
Type 1
CS
NC
NC
GND
VCC
NC
NC
PLCC
1
2
3
4
RDY/BUSY
RESET
WP
VCC
GND
SCK
SO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CS
NC
NC
NC
NC
NC
SI
AT45DB011
Preliminary 16Megabit 2.7-volt
Only Serial
DataFlash
Rev. 1103E–01/01
Note: PLCC package pins 16 and
17 are DON’T CONNECT
1
uses a serial interface to sequentially access its data. The
simple serial interface facilitates hardware layout,
increases system reliability, minimizes switching noise, and
reduces package size and active pin count. The device is
optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and
low power are essential. Typical applications for the
DataFlash are digital voice storage, image storage, and
data storage. The device operates at clock frequencies up
to 13 MHz with a typical active read current consumption of
4 mA.
To allow for simple in-system reprogrammability, the
AT45DB011 does not require high input voltages for programming. The device operates from a single power
supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB011 is enabled through the chip select
pin (CS) and accessed via a three-wire interface consisting
of the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
FLASH MEMORY ARRAY
WP
PAGE (264 BYTES)
BUFFER (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the
AT45DB011 is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory
Architecture Diagram illustrates the breakdown of each
2
AT45DB011
level and details the number of pages per sector and block.
All program operations to the DataFlash occur on a page
by page basis; however, the optional erase operations can
be performed at the block or page level.
AT45DB011
Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR ARCHITECTURE
SECTOR 0 = 2112 BYTES (2K + 64)
SECTOR 0
BLOCK 0
PAGE ARCHITECTURE
PAGE 0
8 Pages
PAGE 1
BLOCK 2
SECTOR 1 = 65,472 BYTES (62K + 1984)
SECTOR 1
BLOCK 3
BLOCK 0
BLOCK 1
PAGE 6
PAGE 7
PAGE 8
BLOCK 29
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 34
PAGE 9
BLOCK 1
BLOCK 30
PAGE 14
PAGE 15
PAGE 16
SECTOR 2
SECTOR 2 = 67,584 BYTES (64K + 2K)
PAGE 17
PAGE 18
BLOCK 61
PAGE 509
BLOCK 62
PAGE 510
BLOCK 63
PAGE 511
Block = 2112 bytes
(2K + 64)
Page = 264 bytes
(256 + 8)
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Tables 1 and 2. A valid instruction starts with the falling edge of CS followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
bits (BA8-BA0) specify the starting byte address within the
page. The 32 don’t care bits which follow the 24 address
bits are sent to initialize the read operation. Following the
32 don’t care bits, additional pulses on SCK result in serial
data being output on the SO (serial output) pin. The CS pin
must remain low during the loading of the opcode, the
address bits, and the reading of data. When the end of a
page in main memory is reached during a main memory
page read, the device will continue reading at the beginning
of the same page. A low-to-high transition on the CS pin
will terminate the read operation and tri-state the SO pin.
Read
BUFFER READ: Data can be read from the data buffer
using an opcode of 54H. To perform a buffer read, the eight
bits of the opcode must be followed by 15 don’t care bits,
nine address bits, and eight don’t care bits. Since the buffer
size is 264-bytes, nine address bits (BFA8-BFA0) are
required to specify the first byte of data to be read from the
buffer. The CS pin must remain low during the loading of
the opcode, the address bits, the don’t care bits, and the
reading of data. When the end of the buffer is reached, the
device will continue reading back at the beginning of the
buffer. A low-to-high transition on the CS pin will terminate
the read operation and tri-state the SO pin.
By specifying the appropriate opcode, data can be read
from the main memory or from the data buffer.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 512
pages in the main memory, bypassing the data buffer and
leaving the contents of the buffer unchanged. To start a
page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits. In the AT45DB011, the
first six address bits are reserved for larger density devices
(see Notes on page 9), the next nine address bits (PA8PA0) specify the page address, and the next nine address
3
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page
of data can be transferred from the main memory to buffer.
An 8-bit opcode of 53H is followed by the six reserved bits,
nine address bits (PA8-PA0) which specify the page in
main memory that is to be transferred, and nine don’t care
bits. The CS pin must be low while toggling the SCK pin to
load the opcode, the address bits, and the don’t care bits
from the SI pin. The transfer of the page of data from the
main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a
page of data (tXFR), the status register can be read to determine whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page
of data in main memory can be compared to the data in the
buffer. An 8-bit opcode of 60H is followed by 24 address
bits consisting of the six reserved bits, nine address bits
(PA8-PA0) which specify the page in the main memory that
is to be compared to the buffer, and nine don’t care bits.
The loading of the opcode and the address bits is the same
as described previously. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and
the don’t care bits from the SI pin. On the low-to-high transition of the CS pin, the 264 bytes in the selected main
memory page will be compared with the 264 bytes in the
buffer. During this time (tXFR), the status register will indicate that the part is busy. On completion of the compare
operation, bit 6 of the status register is updated with the
result of the compare.
Program
BUFFER WRITE: Data can be shifted in from the SI pin
into the data buffer. To load data into the buffer, an 8-bit
opcode of 84H is followed by 15 don’t care bits and nine
address bits (BFA8-BFA0). The nine address bits specify
the first byte in the buffer to be written. The data is entered
following the address bits. If the end of the data buffer is
reached, the device will wrap around back to the beginning
of the buffer. Data will continue to be loaded into the buffer
until a low-to-high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE: Data written into the buffer can be programmed into the main memory. An 8-bit opcode of 83H is
followed by the six reserved bits, nine address bits (PA8PA0) that specify the page in the main memory to be written, and nine additional don’t care bits. When a low-to-high
transition occurs on the CS pin, the part will first erase the
selected page in main memory to all 1s and then program
4
AT45DB011
the data stored in the buffer into the specified page in the
main memory. Both the erase and the programming of the
page are internally self-timed and should take place in a
maximum time of tEP. During this time, the status register
will indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously erased page within
main memory can be programmed with the contents of the
buffer. An 8-bit opcode of 88H is followed by the six
reserved bits, nine address bits (PA8-PA0) that specify the
page in the main memory to be written, and nine additional
don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will program the data stored in the buffer
into the specified page in the main memory. It is necessary
that the page in main memory that is being programmed
has been previously erased. The programming of the page
is internally self-timed and should take place in a maximum
time of tP. During this time, the status register will indicate
that the part is busy.
PAGE ERASE: The optional Page Erase command can be
used to individually erase any page in the main memory
array allowing the Buffer to Main Memory Page Program
without Built-in Erase command to be utilized at a later
time. To perform a Page Erase, an opcode of 81H must be
loaded into the device, followed by six reserved bits, nine
address bits (PA8-PA0), and nine don’t care bits. The nine
address bits are used to specify which page of the memory
array is to be erased. When a low-to-high transition occurs
on the CS pin, the part will erase the selected page to 1s.
The erase operation is internally self-timed and should take
place in a maximum time of tPE. During this time, the status
register will indicate that the part is busy.
BLOCK ERASE: A block of eight pages can be erased at
one time allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized to
reduce programming times when writing large amounts of
data to the device. To perform a Block Erase, an opcode of
50H must be loaded into the device, followed by six
reserved bits, six address bits (PA8-PA3), and 12 don’t
care bits. The six address bits are used to specify which
block of eight pages is to be erased. When a low-to-high
transition occurs on the CS pin, the part will erase the
selected block of eight pages to 1s. The erase operation is
internally self-timed and should take place in a maximum
time of tBE. During this time, the status register will indicate
that the part is busy.
AT45DB011
Block Erase Addressing
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Block
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
1
X
X
X
1
0
0
0
0
1
0
X
X
X
2
0
0
0
0
1
1
X
X
X
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
0
0
X
X
X
60
1
1
1
1
0
1
X
X
X
61
1
1
1
1
1
0
X
X
X
62
1
1
1
1
1
1
X
X
X
63
MAIN MEMORY PAGE PROGRAM: This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-in Erase operations. Data is first
shifted into the buffer from the SI pin and then programmed
into a specified page in the main memory. An 8-bit opcode
of 82H is followed by the six reserved bits and 18 address
bits. The nine most significant address bits (PA8-PA0)
select the page in the main memory where data is to be
written, and the next nine address bits (BFA8-BFA0) select
the first byte in the buffer to be written. After all address bits
are shifted in, the part will take data from the SI pin and
store it in the data buffer. If the end of the buffer is reached,
the device will wrap around back to the beginning of the
buffer. When there is a low-to-high transition on the CS pin,
the part will first erase the selected page in main memory to
all 1s and then program the data stored in the buffer into
the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and
should take place in a maximum of time tEP. During this
time, the status register will indicate that the part is busy.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or multiple pages of data are
modified in a random fashion. This mode is a combination
of two operations: Main Memory Page to Buffer Transfer
and Buffer to Main Memory Page Program with Built-in
Erase. A page of data is first transferred from the main
memory to the data buffer, and then the same data (from
the buffer) is programmed back into its original page of
main memory. An 8-bit opcode of 58H is followed by the six
reserved bits, nine address bits (PA8-PA0) that specify the
page in main memory to be rewritten, and nine additional
don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will first transfer data from the page in main
memory to the buffer and then program the data from the
buffer back into same page of main memory. The operation
is internally self-timed and should take place in a maximum
time of tEP. During this time, the status register will indicate
that the part is busy.
If a sector is programmed or reprogrammed sequentially
page by page, then the programming algorithm shown in
Figure 1 on page 16 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed
randomly in a sector, then the programming algorithm
shown in Figure 2 on page 17 is recommended.
STATUS REGISTER: The status register can be used to
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of
57H must be loaded into the device. After the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most significant bits of the status register will contain device
information, while the remaining three least significant bits
are reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itself (as long as CS remains low and
SCK is being toggled) starting again with bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
cause the device to be in a busy state: Main Memory Page
to Buffer Transfer, Main Memory Page to Buffer Compare,
5
Buffer to Main Memory Page Program with Built-in Erase,
Buffer to Main Memory Page Program without Built-in
Erase, Page Erase, Block Erase, Main Memory Page Program, and Auto Page Rewrite.
machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The result of the most recent Main Memory Page to Buffer
Compare operation is indicated using bit 6 of the status
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
least one bit of the data in the main memory page does not
match the data in the buffer.
The device incorporates an internal power-on reset circuit,
so there are no restrictions on the RESET pin during
power-on sequences. The RESET pin is also internally
pulled high; therefore, in low pin count applications, connection of the RESET pin is not necessary if this pin and
feature will not be utilized. However, it is recommended
that the RESET pin be driven high externally whenever
possible.
The device density is indicated using bits 5, 4, and 3 of the
status register. For the AT45DB011, the three bits are 0, 0,
and 1. The decimal value of these three binary bits does
not equate to the device density; the three bits represent a
combinational code relating to differing densities of Serial
DataFlash devices, allowing a total of eight different density
configurations.
HARDWARE PAGE WRITE PROTECT: If the WP pin is
held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256
pages is to first drive the protect pin high and then use the
program commands previously mentioned. The WP pin is
internally pulled high; therefore, in low pin count applications, connection of the WP pin is not necessary if this pin
and feature will not be utilized. However, it is recommended that the WP pin be driven high externally
whenever possible.
RESET: A low state on the reset pin (RESET) will terminate
the operation in progress and reset the internal state
READY/BUSY: This open drain output pin will be driven
low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an
external pull-up resistor), will be pulled low during programming operations, compare operations, and during page-tobuffer transfers.
The busy status indicates that the Flash memory array and
the buffer cannot be accessed.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI
Mode 3. In addition, the SO pin will be in a high-impedance
state, and a high-to-low transition on the CS pin will be
required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sampling the inactive clock state.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
COMP
0
0
1
X
X
X
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT45DB011
Com.
Operating Temperature (Case)
Ind.
VCC Power Supply(1)
Note:
6
0°C to 70°C
-40°C to 85°C
2.7V to 3.6V
1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started.
AT45DB011
AT45DB011
DC Characteristics
Symbol
Parameter
Condition
ISB
Standby Current
ICC1
Min
Typ
Max
Units
CS, RESET, WP = VIH, all inputs at
CMOS levels
2
10
µA
Active Current, Read Operation
f = 13 MHz; IOUT = 0 mA; VCC = 3.6V
4
10
mA
ICC2
Active Current, Program/Erase
Operation
VCC = 3.6V
10
25
mA
ILI
Input Load Current
VIN = CMOS levels
1
µA
ILO
Output Leakage Current
VI/O = CMOS levels
1
µA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA; VCC = 2.7V
VOH
Output High Voltage
IOH = -100 µA
2.0
V
0.4
VCC - 0.2V
V
V
AC Characteristics
Symbol
Parameter
Min
fSCK
SCK Frequency
tWH
SCK High Time
35
ns
tWL
SCK Low Time
35
ns
tCS
Minimum CS High Time
250
ns
tCSS
CS Setup Time
250
ns
tCSH
CS Hold Time
250
ns
tCSB
CS High to RDY/BUSY Low
tSU
Data In Setup Time
10
ns
tH
Data In Hold Time
20
ns
tHO
Output Hold Time
0
ns
tDIS
Output Disable Time
25
ns
tV
Output Valid
30
ns
tXFR
Page to Buffer Transfer/Compare Time
120
200
µs
tEP
Page Erase and Programming Time
10
20
ms
tP
Page Programming Time
7
15
ms
tPE
Page Erase Time
6
10
ms
tBE
Block Erase Time
7
15
ms
tRST
RESET Pulse Width
tREC
RESET Recovery Time
AC
DRIVING
LEVELS
0.45V
Max
Units
13
MHz
200
10
2.0
0.8
AC
MEASUREMENT
LEVEL
ns
µs
1
Input Test Waveforms and
Measurement Levels
2.4V
Typ
µs
Output Test Load
DEVICE
UNDER
TEST
30 pF
tR, tF < 5 ns (10% to 90%)
7
AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the SCK signal being low when CS makes a highto-low transition, and Waveform 2 shows the SCK signal
being high when CS makes a high-to-low transition. Both
waveforms show valid timing diagrams. The setup and hold
times for the SI signal are referenced to the low-to-high
transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI
Mode 0, and Waveform 2 shows timing that is compatible
with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low
tCS
CS
tWH
tCSS
tWL
tCSH
SCK
tHO
tV
SO
HIGH IMPEDANCE
VALID OUT
tSU
tDIS
HIGH IMPEDANCE
tH
VALID IN
SI
Waveform 2 – Inactive Clock Polarity High
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
tV
SO
tHO
HIGH Z
VALID OUT
tSU
SI
8
tH
VALID IN
AT45DB011
tDIS
HIGH IMPEDANCE
AT45DB011
Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC
tCSS
SCK
tRST
RESET
HIGH IMPEDANCE
HIGH IMPEDANCE
SO
SI
Command Sequence for Read/Write Operations (Except Status Register Read)
SI
MSB
r r r r
CMD
r r XX
Reserved for
larger densities
Notes:
8 bits
8 bits
XXXX XXXX
Page Address
(PA8-PA0)
8 bits
XXXX XXXX
LSB
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0”.
3. For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
9
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER TO
MAIN MEMORY
PAGE PROGRAM
BUFFER (264 BYTES)
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER
BUFFER
WRITE
I/O INTERFACE
SI
Main Memory Page Program through Buffer
· Completes writing into buffer
· Starts self-timed erase/program operation
CS
SI
r ···r , PA8-7
CMD
PA6-0, BFA8
BFA7-0
n
n+1
Last Byte
Buffer Write
· Completes writing into buffer
CS
SI
CMD
X
X···X, BFA8
BFA7-0
n
Last Byte
n+1
Buffer to Main Memory Page Program
(Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS
SI
CMD
Each transition represents
8 bits and 8 clock cycles
10
AT45DB011
r ···r , PA8-7
PA6-0, X
X
n = 1st byte written
n+1 = 2nd byte written
AT45DB011
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
MAIN MEMORY
PAGE TO
BUFFER
MAIN MEMORY
PAGE READ
BUFFER (264 BYTES)
BUFFER
READ
I/O INTERFACE
SO
Main Memory Page Read
CS
SI
CMD
r ···r , PA8-7
BA7-0
PA6-0, BA8
X
X
X
X
SO
n
n+1
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS
SI
CMD
r ···r , PA8-7
PA6-0, X
X
SO
Buffer Read
CS
SI
SO
Each transition represents
8 bits and 8 clock cycles
CMD
X
X···X, BFA8
BFA7-0
X
n
n+1
n = 1st byte read
n+1 = 2nd byte read
11
Detailed Bit-level Read Timing – Inactive Clock Polarity Low
Main Memory Page Read
CS
SCK
1
2
3
4
5
60
61
62
63
64
0
X
X
X
X
X
65
66
67
tSU
COMMAND OPCODE
SI
1
0
1
0
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
MSB
D6
42
43
D5
Buffer Read
CS
SCK
1
2
3
4
5
36
37
38
39
40
0
X
X
X
X
X
41
tSU
COMMAND OPCODE
SI
1
0
1
0
tV
HIGH-IMPEDANCE
SO
DATA OUT
D7
MSB
D6
D5
Status Register Read
CS
SCK
1
2
3
4
5
6
7
8
1
1
9
10
11
12
16
17
tSU
COMMAND OPCODE
SI
0
1
0
1
0
1
tV
SO
12
HIGH-IMPEDANCE
AT45DB011
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D1
D0
LSB
D7
MSB
AT45DB011
Detailed Bit-level Read Timing – Inactive Clock Polarity High
Main Memory Page Read
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
67
68
tSU
COMMAND OPCODE
SI
1
0
1
0
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
MSB
D6
D5
D4
Buffer Read
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
1
0
1
0
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D7
MSB
D6
D5
D4
Status Register Read
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
0
1
0
1
0
1
1
1
tV
SO
HIGH-IMPEDANCE
STATUS REGISTER OUTPUT
D7
MSB
D6
D5
D4
D0
LSB
D7
MSB
D6
13
Table 1.
Main Memory
Page Read
Buffer
Read
Main Memory Page
to Buffer Transfer
Main Memory Page
to Buffer Compare
Buffer
Write
Opcode
52H
54H
53H
60H
84H
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
1
0
0
r
X
r
r
X
r
X
r
r
X
r
X
r
r
X
r
X
r
r
X
r
X
r
r
X
r
X
r
r
X
PA8
X
PA8
PA8
X
PA7
X
PA7
PA7
X
PA6
X
PA6
PA6
X
PA5
X
PA5
PA5
X
PA4
X
PA4
PA4
X
PA3
X
PA3
PA3
X
PA2
X
PA2
PA2
X
PA1
X
PA1
PA1
X
PA0
X
PA0
PA0
X
BA8
BFA8
X
X
BFA8
BA7
BFA7
X
X
BFA7
BA6
BFA6
X
X
BFA6
BA5
BFA5
X
X
BFA5
BA4
BFA4
X
X
BFA4
BA3
BFA3
X
X
BFA3
BA2
BFA2
X
X
BFA2
BA1
BFA1
X
X
BFA1
BA0
BFA0
X
X
BFA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
•
•
•
X (64th bit)
14
AT45DB011
X (Don’t Care)
r (reserved bits)
AT45DB011
Table 2.
Buffer to
Main Memory
Page Program
with Built-in Erase
Buffer to
Main Memory
Page Program
without Built-in
Erase
Page
Erase
Block
Erase
Main Memory
Page Program
through Buffer
Auto Page
Rewrite
through Buffer
Status
Register
Opcode
83H
88H
81H
50H
82H
58H
57H
1
1
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
1
0
1
0
0
0
1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
PA8
PA8
PA8
PA8
PA8
PA8
PA7
PA7
PA7
PA7
PA7
PA7
PA6
PA6
PA6
PA6
PA6
PA6
PA5
PA5
PA5
PA5
PA5
PA5
PA4
PA4
PA4
PA4
PA4
PA4
PA3
PA3
PA3
PA3
PA3
PA3
PA2
PA2
PA2
X
PA2
PA2
PA1
PA1
PA1
X
PA1
PA1
PA0
PA0
PA0
X
PA0
PA0
X
X
X
X
BFA8
X
X
X
X
X
BFA7
X
X
X
X
X
BFA6
X
X
X
X
X
BFA5
X
X
X
X
X
BFA4
X
X
X
X
X
BFA3
X
X
X
X
X
BFA2
X
X
X
X
X
BFA1
X
X
X
X
X
BFA0
X
X (Don’t Care)
r (reserved bits)
15
Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array
START
provide address
and data
BUFFER WRITE
(84H)
MAIN MEMORY PAGE PROGRAM
(82H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)
END
Notes:
1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
16
AT45DB011
AT45DB011
Figure 2. Algorithm for Randomly Modifying Data
START
provide address of
page to modify
MAIN MEMORY PAGE
to BUFFER TRANSFER
(53H)
If planning to modify multiple
bytes currently stored within
a page of the Flash array
BUFFER WRITE
(84H)
MAIN MEMORY PAGE PROGRAM
(82H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)
(2)
Auto Page Rewrite
(58H)
INCREMENT PAGE
(2)
ADDRESS POINTER
END
Notes:
1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase/program operations within that sector.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Sector Addressing
PA8
PA7
PA6
PA5
PA4
PA3
PA2-PA0
Sector
0
0
0
0
0
0
X
0
0
X
X
X
X
X
X
1
1
X
X
X
X
X
X
2
17
Ordering Information
ICC (mA)
fSCK
(MHz)
Active
Standby
Ordering Code
Package
13
10
0.01
AT45DB011-JC
AT45DB011-SC
AT45DB011-XC
32J
8S2
14X
Commercial
(0°C to 70°C)
13
10
0.01
AT45DB011-JI
AT45DB011-SI
AT45DB011-XI
32J
8S2
14X
Industrial
(-40°C to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
8S2
8-lead, 0.210" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
14X
14-lead, 0.170" Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
18
AT45DB011
Operation Range
AT45DB011
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
.045(1.14) X 45˚
.025(.635) X 30˚ - 45˚
.012(.305)
.008(.203)
PIN NO. 1
IDENTIFY
.530(13.5)
.490(12.4)
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
8S2, 8-lead, 0.210" Wide, Plastic Gull Wing Small
Outline (EIAJ SOIC)
Dimensions in Inches and (Millimeters)
.021(.533)
.013(.330)
.020 (.508)
.012 (.305)
.213 (5.41)
.205 (5.21)
PIN 1
.330 (8.38)
.300 (7.62)
.050 (1.27) BSC
.050(1.27) TYP
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
.022(.559) X 45˚ MAX (3X)
0
REF
8
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
.010 (.254)
.007 (.178)
.035 (.889)
.020 (.508)
14X, 14-lead, 0.170" Wide, Thin Shrink Small Outline
Package (TSSOP)
Dimensions in Millimeters and (Inches)*
INDEX MARK
PIN
1
4.50 (.177)
4.30 (.169)
5.10 (.201)
4.90 (.193)
.650 (.026) BSC
1.20 (.047) MAX
0.15 (.006)
0.05 (.002)
0.30 (.012)
0.19 (.007)
6.50 (.256)
6.25 (.246)
SEATING
PLANE
0.20 (.008)
0.09 (.004)
0
REF
8
0.75 (.030)
0.45 (.018)
*Controlling dimension: millimeters
19
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© Atmel Corporation 2001.
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1103E–01/01/xM