Cypress CYRS1049DV33 4-mbit (512 k ã 8) static ram Datasheet

CYRS1049DV33
4-Mbit (512 K × 8) Static RAM
with RadStop™ Technology
4-Mbit (512 K × 8) Static RAM with RadStop™ Technology
Radiation Performance
Features
Radiation Data
❥
Temperature ranges
❥ Military/Space: –55 °C to 125 °C
❥
High speed
❥ tAA = 12 ns
❥
Low active power
❥ ICC = 95 mA at 12 ns (PMAX = 315 mW)
❥
Low CMOS standby power
❥ ISB2 = 15 mA
❥
2.0 V data retention
❥
Automatic power-down when deselected
❥
Transistor-transistor logic (TTL) compatible inputs and outputs
❥
Easy memory expansion with CE and OE features
❥
Available in Pb-free 36-pin ceramic flat package
❥
Total dose 300 Krad
❥
Soft error rate (both heavy ion and proton)
Heavy ions  1 × 10-10 upsets/bit-day with single-error
correction, double error detection error detection and
correction (SEC-DED EDAC)
❥
Neutron = 2.0 × 1014 N/cm2
9
❥
Dose rate > 2.0 × 10 (rad(Si)/s)
❥
Latch up immunity LET = 120 MeV.cm2/mg (125 C)
Processing Flows
❥
V grade - Class V flow in compliance with MIL-PRF 38535
Prototyping Options
❥
Non qualified manufacturers list (QML) V grade
CYPT1049DV33 devices with same functional and timing
characteristics in a 36-pin ceramic flat package
Logic Block Diagram
I/O0
IO
0
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
512K x 8
ARRAY
IO22
I/O
I/O
IO
33
I/O
IO
44
I/O
IO
55
I/O
IO
66
CE
COLUMN DECODER
WE
POWER
DOWN
IO
I/O
77
A11
A12
A13
A14
A15
A16
A17
A18
OE
Cypress Semiconductor Corporation
Document Number: 001-64292 Rev. *C
SENSE AMPS
ROW DECODER
IO
I/O
11
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 19, 2012
CYRS1049DV33
Contents
Functional Description ..................................................... 3
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
AC Switching Characteristics ......................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-64292 Rev. *C
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Glossary .......................................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
CYRS1049DV33
Functional Description
The CYRS1049DV33 is a high-performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
512 K words by 8 bits with RadStop™ technology. Cypress’s
state-of-the-art RadStop technology is radiation hardened
through proprietary design and process hardening techniques.
The 4-Mbit fast asynchronous SRAM with RadStop technology
is also QML V certified with Defense Logistics Agency Land and
Maritime (DLAM).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the I/O pins. See the
Truth Table on page 11 for a complete description of read and
write modes.
The eight input or output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW)
The CYRS1049DV33 is available in a ceramic 36-pin
Flatpackage with center power and ground (revolutionary)
pinout.
Easy memory expansion is provided by utilizing OE, CE, and
tri-state drivers.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Selection Guide
Description
Military/Space
12
95
15
Maximum access time
Maximum operating current
Maximum CMOS standby current
Unit
ns
mA
mA
Pin Configuration
Figure 1. 36-pin Ceramic Flat Package (Top View) [1]
A0
A1
A2
A3
A4
CE
IO0
IO1
VCC
GND
IO2
IO3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
IO7
IO6
GND
VCC
IO5
IO4
A14
A13
A12
A11
A10
DNU
Note
1. NC pins are not connected on the die.
Document Number: 001-64292 Rev. *C
Page 3 of 16
CYRS1049DV33
Maximum Ratings
DC input voltage [2] ............................. –0.5 V to VCC + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Storage temperature ................................ –65 C to +150 C
Latch up current ..................................................... > 140 mA
Ambient temperature with
power applied .......................................... –55 C to +125 C
Operating Range
Supply voltage on
VCC relative to GND [2] ................................–0.3 V to +4.6 V
Ambient
Temperature
Range
DC voltage applied to outputs
in High Z state [2] ................................ –0.5 V to VCC + 0.5 V
Military/Space
VCC
Speed
–55 C to +125 C 3.3 V  0.3 V
12 ns
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Military/Space
Test Conditions
VOH
Output high voltage
VCC = Min, IOH = –4.0 mA
VOL
Output low voltage
VCC = Min, IOL = 8.0 mA
Min
Max
Unit
2.4
–
V
–
0.4
V
VIH
[2]
Input high voltage
2.0
VCC + 0.3
V
VIL
[2]
Input low voltage
–0.3
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, output disabled
–1
+1
A
ICC
VCC operating supply current
VCC = Max, f = fMAX = 1/tRC
83 MHz
–
95
mA
66 MHz
–
85
mA
40 MHz
–
75
mA
ISB1
Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
–
15
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–
15
mA
Note
2. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
Document Number: 001-64292 Rev. *C
Page 4 of 16
CYRS1049DV33
Capacitance
Parameter [3]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
Max
Unit
8
pF
8
pF
CeramicFlat
Package
Unit
3.6
C/W
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Thermal Resistance
Parameter [3]
JC
Description
Test Conditions
Thermal resistance
(junction to case)
Test according to MIL-PRF 38538
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
Z = 50 
50 
* Capacitive load consists
of all components of the
test environment
All Input Pulses
3.0 V
Output
30 pF*
GND
90%
90%
10%
10%
1.5 V
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(a)
High-Z Characteristics
(b)
R 317
3.3 V
OUTPUT
R2
351 
5 pF
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load shown
in Figure 2 (c).
Document Number: 001-64292 Rev. *C
Page 5 of 16
CYRS1049DV33
AC Switching Characteristics
Over the Operating Range
Parameter [5]
Description
Military/Space
Min
Max
Unit
Read Cycle
tpower[6]
VCC (typical) to the first access
100
–
s
tRC
Read cycle time
12
–
ns
tAA
Address to data valid
–
12
ns
tOHA
Data hold from address change
3
–
ns
tACE
CE LOW to data valid
–
12
ns
tDOE
OE LOW to data valid
–
6
ns
0
–
ns
–
6
ns
3
–
ns
–
6
ns
tLZOE
OE LOW to Low Z
[7]
[7, 8]
tHZOE
OE HIGH to High Z
tLZCE
CE LOW to Low Z [7]
[7, 8]
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power-up
0
–
ns
tPD
CE HIGH to Power-down
–
12
ns
Write Cycle [9, 10]
tWC
Write cycle time
12
–
ns
tSCE
CE LOW to write end
8
–
ns
tAW
Address setup to write end
8
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
8
–
ns
tSD
Data setup to write end
6
–
ns
tHD
Data hold from write end
0
–
ns
WE HIGH to Low Z
[7]
3
–
ns
WE LOW to High Z
[7, 8]
–
6
ns
tLZWE
tHZWE
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given
device.
8. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high
impedance state.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-64292 Rev. *C
Page 6 of 16
CYRS1049DV33
Data Retention Characteristics
Over the Operating Range
Parameter
Conditions [11]
Description
Min
Max
Unit
2.0
–
V
VCC = VDR = 2.0 V,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
–
15
VDR
VCC for data retention
–
ICCDR
Data retention current
mA
tCDR[12]
Chip deselect to data retention
time
–
0
–
ns
tR[13]
Operation recovery time
–
12
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
Data Retention Mode
VCC
3.0 V
VDR > 2 V
tCDR
3.0 V
tR
CE
Notes
11. No input may exceed VCC + 0.3 V.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 001-64292 Rev. *C
Page 7 of 16
CYRS1049DV33
Switching Waveforms
Figure 4. Read Cycle No. 1 [14, 15]
tRC
Address
tOHA
Data out
tAA
Previous Data Valid
Data Valid
Figure 5. Read Cycle No. 2 (OE Controlled) [15, 16]
Address
tRC
CE
tACE
OE
tHZOE
tDOE
Data OUT
tLZOE
High Impedance
tLZCE
VCC
Supply
Current
tHZCE
High
Impedance
Data Valid
tPD
tPU
50%
50%
ICC
ISB
Notes
14. Device is continuously selected. OE, CE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document Number: 001-64292 Rev. *C
Page 8 of 16
CYRS1049DV33
Switching Waveforms(continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [17, 18]
tWC
Address
tSCE
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DataIN Valid
Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18]
tWC
Address
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
Data I/O
tHD
Data IN Valid
NOTE 19
tHZOE
Notes
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
19. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 001-64292 Rev. *C
Page 9 of 16
CYRS1049DV33
Switching Waveforms(continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
Address
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
Data
I/O
NOTE 20
tHD
DataIN Valid
tHZWE
tLZWE
Note
20. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 001-64292 Rev. *C
Page 10 of 16
CYRS1049DV33
Truth Table
CE
H
OE
X
WE
X
L
L
L
L
I/O0–I/O7
Mode
Power
High Z
Power-down
Standby (ISB1or ISB2)
H
Data out
Read
Active (ICC)
X
L
Data in
Write
Active (ICC)
H
H
High Z
Selected, Outputs disabled
Active (ICC)
Document Number: 001-64292 Rev. *C
Page 11 of 16
CYRS1049DV33
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
12
CYRS1049DV33-12CZSE
001-67583 36-pin ceramic flat package
Military/Space
12
CYPT1049DV33-12CZSE
001-67583 36-pin ceramic flat package, Prototype part
Military/Space
12
5962F1123501VXA
001-67583 36-pin ceramic flat package, DLAM part
Military/Space
12
CYLE1049DV33-12ZSE
51-85087 44-pin plastic TSOP II
Military/Space
12
CYLE1049DV33-12VE
51-85090 36-pin plastic SOP
Military/Space
Contact your local Cypress sales representative for availability of these parts
Ordering Code Definitions
CY RS 1 04 9
D V33 - 12 XXX X
X
Temperature range: X = E or A
E or A = Military/Space grade
Pb-free
Package type: XXX = CZS or V or ZS
CZS = 36-pin Ceramic FP, V = 36-pin SOP, ZS = 44-pin TSOP II
Speed: 12 = 12 ns
V33 = Voltage range (3 V to 3.6 V)
D= 90 nm Technology
Data width: 9 = × 8 bits
Density: 04 = 4-Mbit
1 = Fast Asynchronous SRAM family
RS = RadStop, PT = Prototype, LE = Low Earth Orbit
CY = Cypress
Document Number: 001-64292 Rev. *C
Page 12 of 16
CYRS1049DV33
Package Diagram
Figure 9. 36-pin Ceramic Flat Pack F36A/FZ36A (Solder Seal Lid) Package Outline, 001-67583
001-67583 *A
Document Number: 001-64292 Rev. *C
Page 13 of 16
CYRS1049DV33
Acronyms
Document Conventions
Acronym
Description
CE
chip enable
CMOS
complementary metal oxide semiconductor
DLAM
defense logistics agency land and maritime
DNU
do not use
EDAC
error detection and correction
I/O
input/output
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
MHz
megahertz
µA
microampere
µs
microsecond
mA
milliampere
LET
linear energy transfer
OE
output enable
ns
nanosecond
QML
qualified manufacturers list
%
percent
SEC-DED
single error correction – double error detection
pF
picofarad
SEL
single-event latch up
V
volt
SRAM
static random access memory
W
watt
TSOP
thin small outline package
TTL
transistor-transistor logic
WE
write enable
Glossary
Total Dose
Permanent device damage due to ions over device life
Heavy Ion
Instantaneous device latch up due to single ion
LET
Linear energy transfer (measured in MeVcm2)
Krad
Unit of measurement to determine device life in radiation environments.
Neutron
Permanent device damage due to energetic neutrons or protons
Prompt Dose
Data loss of permanent device damage due to X-rays and gamma rays <20 ns
RadStop Technology
Cypress's patented Rad Hard design methodology
QML V
Space level certification from DSCC.
DLAM
Defense Logistics Agency Land and Maritime
LSBU
Logical Single Bit Upset. Single bits in a single correction word are in error.
LMBU
Logical Multi Bit Upset. Multiple bits in a single correction word are in error
Document Number: 001-64292 Rev. *C
Page 14 of 16
CYRS1049DV33
Document History Page
Document Title: CYRS1049DV33, 4-Mbit (512 K × 8) Static RAM with RadStop™ Technology
Document Number: 001-64292
Rev.
ECN No.
Origin of
Change
Submission
Date
**
3098986
HRP
12/01/2010
New data sheet.
*A
3181475
PRAS
02/24/2011
Updated Package Diagram (Replaced 44-pin TSOP II package with 36-pin flat
package).
*B
3438781
HRP
11/14/2011
Updated Package Diagram (to current revision).
*C
3554946
HRP
03/19/2012
Changed status from Preliminary to Final.
Updated Radiation Performance (Updated Radiation Data, Prototyping
Options).
Updated Features (Added (PMAX = 315 mW)).
Updated Functional Description (Added the paragraph “Easy memory
expansion is provided by utilizing OE, CE, and tri-state drivers.”).
Updated Maximum Ratings (DC voltage applied to outputs in High Z state, DC
input voltage).
Updated AC Switching Characteristics(Changed the maximum value of tDOE
parameter from 7 ns to 6 ns).
Updated Ordering Information (Additional part numbers added).
Document Number: 001-64292 Rev. *C
Description of Change
Page 15 of 16
CYRS1049DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2010-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-64292 Rev. *C
Revised March 19, 2012
Page 16 of 16
RadStop™ is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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