Mitsubishi M69897VP 16:1 2.488 gbps multiplexer Datasheet

MITSUBISHI SEMICONDUCTOR <SOI/CMOS>
Preliminary
M69897VP
16:1 2.488 Gbps Multiplexer
DESCRIPTION
The M69897VP multiplexer chip is an integrated serialization SONET OC-48 (2.488 Gbps) interface
device. The chip performs parallel-to-serial functions in conformance with SONET/SDH transmission
standards. The device is suitable for SONET-based ATM applications.
The merits of SOI (Silicon-On-Insulator) technology, such as low voltage operation, low substrate noise
and good compatibility with standard CMOS technology, are fully utilized in the chip design to
achieve low jitter and low power operation and small package outline of 64-pin PQFP.
FEATURES
- Single 1.8 V power supply
- Supports 2.488 Gbps (OC-48, STM-16)
- 16-bit single-ended PECL interface
- On-chip high-frequency PLL for clock generation
- 155.52 MHz reference frequency
- Low power consumption
- Available in 64 PQFP
- Parity check function
APPLICATIONS
- SONET/SDH systems
- Fiber optic systems
- High-speed back plane interconnect and point-to-point data links
PARITY
PARIERRO
PARITYI
CHECK
16
2
16:1 PARALLEL
PDI[15:0]
D-FF
TO SERIAL
155.52 Mbps
SDOP/SDON
2.488 Gbps
2
2
PCLKOP/
PCLKON
TIMING
2.488 GHz
SCLKOP/
SCLKON
GENERATOR
155.52 MHz
2
SCLKIP/
SCLKIN
2.488 GHz
2.488 GHz
2.488 GHz
PCLKIP/
PCLKIN
2
2
155.52 MHz
PLL
LPF_EXT1/
LPF_EXT2
SELPLL
Figure 1 Functional Block Diagram
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MITSUBISHI ELECTRIC
December 2000
Table 1 Absolute Maximum Ratings
PARAMETER
MIN
Storage Temperature
TYP
MAX
UNITS
-65
150
ûC
-0.5
2.2
V
Voltage on any PECL Pin
0
2.2
V
ESD Rating (HBM model)
1000
Voltage on V DD with Respect to GND
V
Table 2 Recommended Operating Conditions
PARAMETER
MIN
Ambient Temperature Under Bias
TYP
UNITS
70
ûC
110
ûC
1.8
1.89
V
260
310
mW
All Outputs Unterminated.
320
420
mW
All Outputs Terminated.
0
Junction Temperature Under Bias
1.71
Voltage on V DD with Respect to GND
Power Consumption
CONDITIONS
MAX
Table 3 Differential PECL Input DC Characteristics
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
V IL
Input Low Voltage
GND
V DD -1.4
V
V IH
Input High Voltage
V DD -1.2
V DD -0.8
V
0.2
1.1
V
ÆV INDIFF
Differential Input Voltage Swing
CONDITIONS
See Figure 12.
Table 4 Single-Ended PECL Input DC Characteristics
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
V IL
Input Low Voltage
GND
V DD -1.5
V
V IH
Input High Voltage
V DD -1.1
V DD -0.8
V
0.4
1.1
V
ÆV IN
Input Voltage Swing
CONDITIONS
See Figure 12.
Table 5 CMOS Input DC Characteristics
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
V IL
Input Low Voltage
GND
V DD -1.3
V
V IH
Input High Voltage
V DD -0.5
V DD
V
CONDITIONS
Table 6 Differential PECL Output DC Characteristics
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
V OL
Output Low Voltage
GND
0.1
V
V OH
Output High Voltage
V DD -0.9
V DD -0.8
V
0.7
1.1
V
ÆV OUTDIFF
Differential Output Voltage Swing
CONDITIONS
See Figure 12.
Table 7 Single-Ended PECL Output DC Characteristics
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
V OL
Output Low Voltage
GND
0.1
V
V OH
Output High Voltage
V DD -0.9
V DD -0.8
V
ÆV OUT
Output Voltage Swing
1.1
V
0.7
2
MITSUBISHI ELECTRIC
CONDITIONS
See Figure 12.
December 2000
Table 8 Clock Jitter Characteristics
SYMBOL
DESCRIPTION
MIN
T jitter
Output Jitter
F -3dB
Jitter Transfer (12K-20MHz)
F peak
Jitter Transfer Peaking
TYP
MAX
UNITS
0.01
UIrms
10
MHz
0.1
CONDITIONS
dB
PDI[15:0]/
PARITYI
50 ½
M69897VP
Figure 2 Single-Ended PECL Input DC Termination
V DD
180 ½
0.1 µF
PDI[15:0]/
PARITYI
70 ½
M69897VP
Figure 3 Single-Ended PECL Input AC Termination
PCLKIP
50 ½
PCLKIN
50 ½
M69897VP
Figure 4 Differential PECL Input DC Termination for 155.52 MHz Clock.
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MITSUBISHI ELECTRIC
December 2000
V DD
180 ½
0.1 µF
PCLKIP
70 ½
V DD
180 ½
0.1 µF
PCLKIN
70 ½
M69897VP
Figure 5 Differential PECL Input AC Termination for 155.52 MHz Clock.
V DD
180 ½
100 pF
SCLKIP
V DD
180 ½
100 pF
SCLKIN
M69897VP
Figure 6 Differential PECL Input AC Termination for 2.488 GHz Clock
(Used for Internal PLL off-state mode).
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December 2000
PARIERRO
50ohm
M69897VP
Figure 7 Single-Ended PECL Output DC Termination
R1
0.1 µF
PARIERRO
330ohm
R2
M69897VP
R1xR2/(R1+R2) = 50ohm
Figure 8 Single-Ended PECL Output AC Termination
SCLKOP/
SDOP/
PCLKOP
50ohm
SCLKON/
SDON/
PCLKON
50ohm
M69897VP
Figure 9 Differential PECL Output DC Termination
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December 2000
R1
0.1 µF
SDOP/
PCLKOP
330ohm
R2
R1
0.1 µF
SDON/
PCLKON
330ohm
R2
M69897VP
R1xR2/(R1+R2) = 50ohm
Figure 10 Differential PECL Output AC Termination
R1
100 pF
SCLKOP
330ohm
R2
R1
100 pF
SCLKON
330ohm
R2
M69897VP
R1xR2/(R1+R2) = 50ohm
Figure 11 Differential PECL Output AC Termination for 2.488 GHz Clock Output
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MITSUBISHI ELECTRIC
December 2000
VH
VL
Single-Ended Swing = VH - VL
VH
VL
Differential Swing = VH - VL
Figure 12 Voltage Swing
Table 9 AC Characteristics
SYMBOL
DESCRIPTION
MIN
Serial Clock Rate
TYP
MAX
2.488
UNITS
GHz
T DS
Parallel Data Setup Time wrt PCLKIP
1.0
ns
T DH
Parallel Data Hold Time wrt PCLKIP
1.0
ns
TDS2
Parallel Data Setup Time wrt PCLKOP
1.0
ns
TDH2
Parallel Data Hold Time wrt PCLKOP
1.0
ns
Parallel Clock Input Duty Cycle
40
60
%
Parallel Clock Output Duty Cycle
45
55
%
-50
50
ps
Serial Clock Output to
Serial Data Output Delay
Serial Clock Output Rise and Fall Time
Serial Data Output Rise and Fall Time
Parallel Clock Input Rise and Fall Time
Parallel Data Input Rise and Fall Time
1
1
100
ps
120
ps
1
1
1.0
ns
2.0
ns
1.5
ns
Parallel Data Input and
Parity Input Skew
1. 20% - 80%
PCLKIP
TDS
TDH
PDI[15:0]
Figure 13 Input Timing (SELPLL = "H")
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December 2000
PCLKOP
TD S 2
TD H 2
PDI[15:0]
Figure 14 Input Timing (SELPLL = "L")
SCLKOP
TSD
SDOP/N
D15
D14
D13
D1
D0
Figure 15 Output Timing
Table 10 Input/Output Pin Assignment
PIN NAME
LPF_EXT1
LEVEL
I/O
-
-
LPF_EXT2
PDI[15:0]
SCLKIP
Single-Ended PECL
I
Differential PECL
I
Differential PECL
I
PCLKIN
PARITYI
SDOP
Single-Ended PECL
I
Differential PECL
O
Differential PECL
SCLKON
PCLKOP
Loop filter pins. (See Figure 16.)
Table 11
Received parallel data input.
29
Serial reference clock input.
30
( Used for Internal PLL off-state mode only.)
12
Reference clock input.
13
SDON
SCLKOP
22
DESCRIPTION
21
SCLKIN
PCLKIP
PIN #
Differential PECL
11
38
O
PCLKON
Differential serial data output.
37
41
O
Used for parity check.
Differential serial clock output.
40
52
Differential parallel clock output.
51
PARIERRO
Single-Ended PECL
O
53
Parity error output.
SELPLL
CMOS
I
20
High: Internal PLL operating mode.
NC
-
-
26,47,54
8
No connect. Leave open.
MITSUBISHI ELECTRIC
December 2000
0.02 µF
LPF_EXT1
LPF_EXT2
Figure 16 External Loop Filte
Table 11 Parity Check Condition
# of "High"s in
PARITYI
PARIERRO
PDI[15:0]
High
Even
High
High
Odd
Low
Low
Even
Low
Low
Odd
High
Table 12 PDI Pin Assignment
PIN NAME
PIN #
PIN NAME
PIN #
PDI0
55
PDI8
3
PDI1
56
PDI9
4
PDI2
57
PDI10
5
PDI3
58
PDI11
6
PDI4
59
PDI12
7
PDI5
60
PDI13
8
PDI6
61
PDI14
9
PDI7
62
PDI15
10
Table 13 Common Pin Assignment
PIN NAME
LEVEL
PIN #
V DD 1
1.8 V
1, 14, 15, 17, 63
V DD 2
1.8 V
DESCRIPTION
Core power supply.
28, 31, 33, 36,
I/O power supply.
42, 44, 46, 50
ANAVDD
1.8 V
GND
GND
ANAGND
GND
25
Analog power
2, 16, 18, 19, 27, 32, 34,
supply.
Ground.
35, 39, 43, 45, 48, 49, 64
23, 24
9
Analog ground.
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December 2000
GND
49
32
GND
VDD2
50
31
VDD2
PCLKON
51
30
SCLKIN
PCLKOP
52
29
SCLKIP
PARIERRO
53
28
VDD2
NC
54
27
GND
PDI0
55
26
NC
PDI1
56
25
ANAVDD
PDI2
57
24
ANAGND
PDI3
58
23
ANAGND
PDI4
59
22
LPF_EXT1
PDI5
60
21
LPF_EXT2
PDI6
61
20
SELPLL
PDI7
62
19
GND
VDD1
63
18
GND
GND
64
17
VDD1
Figure 17 Pin Diagrams
Figure 18 Package Information
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MITSUBISHI ELECTRIC
December 2000
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