Rohm BU7963GUW Data rate 1350mbps rgb interface Datasheet

MSDL (Mobile Shrink Data Link) Transceivers for Mobile Phones
Data rate 1350Mbps
RGB Interface
BU7963GUW
No.10058EAT05
●Description
BU7963GUW is a differential serial interface connecting mobile phone LCD modules to the host CPU. Unique technology is
utilized for lower power consumption and EMI. MSDL minimizes the number of wires required - an important consideration
in hinge phones - resulting in greater reliability and design flexibility.
●Features
1) MSDL3 high-speed differential interface with a maximum transfer rate of 1350 Mbps.
2) Compatible with24-bit RGB video mode for LCD controller-to-LCD interface.
3) Pixel clock frequency range from 4 to 45MHz.
4) Depending on the data transfer rate, one, two or three differential data channels can be selected.
●Applications
Serial Interface for LCD Display Interface of Mobile Devices Application.
●Absolute Maximum Ratings:
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Input Current
Symbol
Ratings
Unit
Remarks
DVDD
-0.3 ~ +2.5
V
-
MSVDD
VIN
VOUT
-0.3 ~ +2.5
V
-0.3 ~ MSVDD+0.3
V
I/O terminals of MSVDD line
-0.3 ~ DVDD+0.3
V
I/O terminals of DVDD line
-0.3 ~ MSVDD+0.3
V
I/O terminals of MSVDD line
-0.3 ~ DVDD+0.3
V
I/O terminals of DVDD line
-10 ~ +10
mA
IIN
-
-
Output Current
IOUT
-70 ~ +70
mA
-
Preservation Temperature
Tstg
-55 ~ +125
℃
-
Unit
Conditions
●Operating Conditions:
Parameter
Symbol
Ratings
Min
Typ
Max
Supply Voltage for DVDD
VDVDD
1.65
1.80
1.95
V
Supply Voltage for MSVDD
VMSVDD
1.65
1.80
1.95
V
Data Transmission Rate
DR
120
-
450
Mbps/ch
-
Operating Temperature Range
Topr
-30
25
85
℃
-
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1/19
VDVDD = VMSVDD
2010.04 - Rev.A
Technical Note
BU7963GUW
●Package View
1PIN
MARK
5.0±0.1
BU7963
LOT NO.
0.9 MAX
5.0±0.1
0.10
S
0.08
S
0.75±0.1
0.75±0.1
A
P = 0.5×7
0.5
63-φ0.295±0.05
0.05
M
S AB
H
B
G
P = 0.5×7
F
E
D
C
B
A
1
2
3
4
5
6
7
8
(UNIT:mm)
Fig.1. Package View (VBGA063W050)
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2010.04 - Rev.A
Technical Note
BU7963GUW
●Block Diagram
DVDD
MSVDD
High Speed I/F
D0+
Parallel
to
Serial
D0-
PD[26:0]
D1+
Odd
Parity
I/F
Logic
D1-
CKD
D2+
D2-
PCLK
PCLK
Control
Timing
Generator
Tx
PLL
Tx
CLK+
CLK-
XSD
LS[1:0]
RVS
POL_PCLK
PLL_BW
Reset
Generator
Clock
Detection
Control
Logic
Reference
DRVR
TEST[1:0]
DGND
MSGND
Fig.2. Block Diagram
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2010.04 - Rev.A
Technical Note
BU7963GUW
●Pin Layout
A
1
2
3
4
5
6
7
8
TEST0
PD19
PD17
PD16
PD14
PD13
PD10
CKD
PCLK
PD18
PD15
PD12
PD11
PD9
PD8
B
C
PD22
PD20
PLL_BW
DVDD
N.C.
RVS
PD7
PD6
D
PD23
PD21
N.C.
DGND
DGND
DVDD
PD4
PD5
E
PD25
PD24
DVDD
DGND
MSGND
N.C.
PD1
PD3
F
PD26
LS0
MSVDD
MSGND
MSVDD
N.C.
XSD
PD2
G
LS1
POL_
PCLK
D2+
(D0+)
D1+
(CLK+)
CLK+
(D1+)
D0+
(D2+)
N.C.
PD0
H
N.C.
N.C.
D2(D0-)
D1(CLK-)
CLK(D1-)
D0(D2-)
DRVR
TEST1
Fig.3. Pin Layout (Top View)
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2010.04 - Rev.A
Technical Note
BU7963GUW
●Pin Functions
Table 1. Power Supply and Ground
Power Supply / Ground :
10-pin
Name
Width
Functions
DVDD
3
CMOS I/O and logic core power supply.
MSVDD
2
Analog core power supply.
DGND
3
CMOS I/O and logic core ground.
MSGND
2
Analog core ground.
Table 2. MSDL3
High-Speed Serial Interface
8-pin
Shutdown
Equivalent
Schematic
CLK+ pin
When RVS = ‘L’ : CLK+
When RVS = ‘H’ : D1+
Hi-Z
D
O
CLK- pin
When RVS = ‘L’ : CLKWhen RVS = ‘H’ : D1-
Hi-Z
D
Analog
O
D0+ pin
When RVS = ‘L’ : D0+
When RVS = ‘H’ : D2+
Hi-Z
D
1
Analog
O
D0- pin
When RVS = ‘L’ : D0When RVS = ‘H’ : D2-
Hi-Z
D
D1+
1
Analog
O
D1+ pin
When RVS = ‘L’ : D1+
When RVS = ‘H’ : CLK+
Hi-Z
D
D1-
1
Analog
O
D1- pin
When RVS = ‘L’ : D1When RVS = ‘H’ : CLK-
Hi-Z
D
D2+
1
Analog
O
D2+ pin
When RVS = ‘L’ : D2+
When RVS = ‘H’ : D0+
Hi-Z
D
D2-
1
Analog
O
D2- pin
When RVS = ‘L’ : D2When RVS = ‘H’ : D0-
Hi-Z
D
Shutdown
Equivalent
Schematic
-
D
Name
Width
Level
I/O
CLK+
1
Analog
O
CLK-
1
Analog
D0+
1
D0-
Functions
Table 3. Analog
Analog
1-pin
Name
Width
Level
I/O
DRVR
1
Analog
-
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Functions
10kΩ±5% register should be connected between
DRVR and MSGND.
5/19
2010.04 - Rev.A
Technical Note
BU7963GUW
Table 4. Parallel Data Interface
Parallel Data Interface
29-pin
Shutdown
Equivalent
Schematic
PCLK interface.
Input
A
I
Parallel data interface.
Input
A
O
Output of PCLK detection result.
‘L’: clock stop.
‘H’: clock detect.
‘L’
C
Shutdown
Equivalent
Schematic
Name
Width
Level
I/O
PCLK
1
CMOS
I
PD[26:0]
27
CMOS
CKD
1
CMOS
Functions
Table 5. Control
Control
8-pin
Name
Width
Level
I/O
Functions
XSD
1
CMOS
I
Shutdown pin.
‘L’: shutdown.
‘H’: normal operation.
Input
A
LS0
1
CMOS
I
Selection of the number of data channel and
the data format.
*Refer to "Selection of the number of
MSDL3 channels".
*Set the same number of data channel
between the TX device and the RX device.
Input
A
LS1
1
RVS
1
CMOS
I
Selection of MSDL3 pins assignment.
‘L’: Default matrix.
‘H’: Flipped matrix.
Input
A
PLL_BW
1
CMOS
I
Selection of PLL bandwidth.
Input
A
POL_PCLK
1
CMOS
I
Selection of input clock polarity.
‘L’: sample parallel data at falling.
‘H’: sample parallel data at rising.
Input
A
TEST0
1
I
Test mode pin.
‘L’: normal mode.
‘H’: test mode.
Must be ‘L.’
Pull
down
TEST1
1
Input
B
DVDD
DVDD
A
B
B
MSVDD
DVDD
C
D
Fig.4. Equivalent Schematics
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2010.04 - Rev.A
Technical Note
BU7963GUW
●Operation Control
MSDL3 Channel Count Selection
Pin LS is used to control the high-speed data channel count and data format. The LS pin settings (i.e., high-speed data
channel count, data format) should be the same between the transmitting and receiving devices (the BU7963GUW and
BU7964GUW, respectively). Table 6 shows the PCLK input frequency ranges and transmission data rate ranges for the
LS pin settings.
Table 6. The Range of The Transmission Data rate
LS1
LS0
The Number of Data Channel
The Range of PCLK Input
Frequency [MHz]
The Range of The Data
Transmission Rate
[Mbits/sec]
‘L’
‘L’
1-channel
4.0-15.0
120-450
‘L’
‘H’
2-channel
8.0-30.0
240-900
‘H’
‘L’
3-channel
12.0-45.0
360-1350
‘H’
‘H’
Inhibit setting.
MSDL3 Pin Assignment
RVS determines the assignment of MSDL3 pins, CLK+ / CLK−, D0+ / D0−, D1+ / D1− and D2+ / D2-. Only the
MSDL3 high-speed signaling pins are affected by RVS, while pin assignment of other functions does not change.
User can select the assignment from ‘straight’ (default) and ‘flipped’ assignment in order to minimize channel-to-channel
skew in PWB design. Table 7 shows the MSDL3 pin assignment, and Fig.5 shows the ‘straight’ and ‘flipped’
Table 7. MSDL3 Pin Assignment
MSDL3 Pin Assignment
RVS
‘L’
‘Straight’ (default matrix)
‘H’
‘Flipped’
Top View
RVS='L'
Default MSDL3 terminal assignment
G
D2+
D1+
CLK+
D0+
H
D2-
D1-
CLK-
D0-
3
4
5
6
1
2
7
8
(a) ‘Straight’ Pin Assignment
Top View
RVS='H'
Flipped MSDL3 terminal assignment
G
D0+
CLK+
D1+
D2+
H
D0-
CLK-
D1-
D2-
3
4
5
6
1
2
7
8
(b) ‘Flipped’ Pin Assignment
Fig.5. MSDL3 Pin Assignment
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7/19
2010.04 - Rev.A
Technical Note
BU7963GUW
PCLK Polarity Selection
BU7963GUW controls PCLK input polarity by POL_PCLK setting. Table 8 shows PCLK input polarity.
POL_PCLK
Table 8. PCLK Polarity Selection
Parallel Data Capturing Polarity
‘L’
Capture parallel data at falling edge.
‘H’
(default)
Capture parallel data at rising edge.
PLL Bandwidth Selection
BU7963GUW controls the range of the CLK+ / CLK− input frequency (= PCLK output frequency) by the setting of the
data format (LS1, and LS0) of the high-speed data channel and the bandwidth setting of PLL_BW.
Table 9. PLL_BW Setting
CLK+ / CLK− Frequency Range [MHz]
(PCLK Input Frequency)
PLL_BW
Min
Max
LS1
LS0
‘L’
‘L’
‘L’
4
8
‘L’
‘L’
‘H’
7
15
‘L’
‘H’
‘L’
8
16
‘L’
‘H’
‘H’
14
30
‘H’
‘L’
‘L’
12
24
‘H’
‘L’
‘H’
21
45
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2010.04 - Rev.A
Technical Note
BU7963GUW
●Power Modes
BU7963GUW has three power modes.
1) Shutdown Mode
BU7963GUW goes to Shutdown Mode when XSD = ‘L’. All logic circuits are initialized in the Shutdown Mode.
All high-speed signaling channels are disabled, and the outputs keep Hi-Z status.
2) Standby Mode
BU7963GUW goes to Standby Mode when XSD = ‘H’ and PCLK is not provided. All high-speed signaling channel outputs
keep Hi-Z status. BU7963GUW is monitoring whether PCLK input is running or not and the link switches to Active Mode
when PCLK running is detected.
3) Active Mode
BU7963GUW goes to Active Mode when XSD = ‘H’ and PCLK is running. All high-speed signaling channels are enabled.
Table 10. Power Modes
Power Mode
Input
Shutdown
Standby
XSD
‘L’
‘H’
PCLK
Static (‘L’ or ‘H’)
Static (‘L’ or ‘H’)
Active
‘H’
Clock input is active
Operation
Functions
MSDL3 Terminals
Initialized
Disabled (Hi-Z)
PCLK detection
Disabled (Hi-Z)
PCLK detection
Normal operation
Enabled
(P2S conv)
4) Power Modes Transition
Fig.6 shows the transition of power modes.
XSD = ”L”
Shutdown
XSD = ”H”
Standby
PCLK input
stopped
PCLK input
detected
Active
Fig.6. Power Modes Transition
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2010.04 - Rev.A
Technical Note
BU7963GUW
●High-Speed Data Channel Protocols
Fig.7, Fig.8 and Fig.9 show high-speed data channel protocols.
D0channel
CP
PD26
PD25 PD24
PD23
PD22 PD21 PD20
PD19
PD18 PD17
PD16 PD15
PD3
PD2
PD0
PD14 PD13 PD12
CLK channel
Frame start/end
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD1
res
res
CP
PD26
PD25
Fig.7. MSDL3 Protocol for 1-channel Data (27-bit)
D0channel CP
PD26 PD25 PD24
PD23 PD22 PD21 PD20
D1channel res
PD14 PD13 PD12 PD11 PD10
PD9
PD8
PD19 PD18 PD17
PD2
res
CP
PD26
PD3
PD1
PD0
res
PD14
PD19 PD18 PD17 PD16 PD15
PD2
res
CP
PD26
PD7
PD6
PD5
PD16 PD15
PD4
CLK channel
Frame start/end
Fig.8. MSDL3 Protocol for 2-channel Data (27-bit)
D0channel CP
PD26 PD25 PD24
PD23 PD22 PD21 PD20
CLK channel
Frame start/end
Fig.9. MSDL3 Protocol for 1-channel Data (13-bit)
“res” is reserved bit for the future use, the default state of those is ‘0.’
CP is the parity bit of data payload. BU7961GUW adds an odd parity on CP of the high-speed channel data.
・When the number of ‘H’ bits in parallel data is even, CP bit is ‘H.’
・When the number of ‘H’ bits in parallel data is odd, CP bits is ‘L.’
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10/19
2010.04 - Rev.A
Technical Note
BU7963GUW
●Electrical Characteristics
1) DC Characteristics
Table 11. Digital Input / Output DC Characteristics
Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Symbol
Limits
Min
Typ
Max
Unit
Conditions
PCLK, PD[26:0], LS[1:0],
RVS, POL_PCLK, XSD,
PLL_BW, TEST[1:0] pin
PCLK, PD[26:0], LS[1:0],
RVS, POL_PCLK,
PLL_BW, TEST[1:0] pin
‘L’ Input Voltage 1
VIL1
DGND
-
0.3 x DVDD
V
‘H’ Input Voltage 1
VIH1
0.7 x DVDD
-
DVDD
V
‘L’ Input Current 1
IIL1
-5
-
+5
µA
VIN = DGND
‘H’ Input Current 1
IIH1
-5
-
+5
µA
VIN = DVDD
‘L’ Input Current 2
IIL2
-5
-
+5
µA
VIN = MSGND
‘H’ Input Current 2
IIH2
-5
-
+5
µA
VIN = MSVDD
‘L’ Output Voltage 1
VOL1
DGND
-
0.3 x DVDD
V
IO = 1mA,CKD pin
‘H’ Output Voltage 1
VOH1
0.7 x DVDD
-
DVDD
V
IO = -1mA,CKD pin
Table 12 Current Consumption
Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Symbol
Limits
Min
Typ
Max
Unit
Shutdown Current
Iop_sht_rx
-
0.2
10
µA
Standby Current
Iop_stb_rx
-
0.2
10
µA
Active Current
1-channel / 27-bit Format
Active Current
2-channel / 27-bit Format
Active Current
3-channel/ 27-bit Format
Iop_act_rx1
Iop_act_rx2
Iop_act_rx3
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-
-
-
14.0
19.7
25.4
11/19
18.5
25.7
32.9
Conditions
XSD = ‘L’,
IDVDD + IMSVDD
XSD = ‘H’,
IDVDD + IMSVDD
mA
LS[1:0] = ‘LL,’ PLL_BW[1:0] = ‘H’
DVDD = MSVDD
PCLK=15MHz,XSD=‘H
CL=10pF
Total operating current (IDVDD +
IMSVDD ) with PD[26:0] inputs to ggling
0x2AAAAAA and 0x5555555
mA
LS[1:0] = ‘LH,’ PLL_BW[1:0] = ‘H’
DVDD = MSVDD
PCLK=30MHz,XSD=‘H’
CL=10pF
Total operating current (IDVDD +
IMSVDD) with PD[26:0] inputs to ggling
0x2AAAAAA and 0x5555555
mA
LS[1:0] = ‘HL,’ PLL_BW[1:0] = ‘H’
DVDD = MSVDD
PCLK=45MHz,XSD=‘H’
CL=10pF
Total operating current (IDVDD +
IMSVDD) with PD[26:0] inputs to ggling
0x2AAAAAA and 0x5555555
2010.04 - Rev.A
Technical Note
BU7963GUW
2) AC Characteristics
Parallel Data Input Timing
tTX_DH
tTX_DS
0.7×DVDD
PD[26:0]
0.3×DVDD
0.7×DVDD
tTX_R1/tTX_R2
PCLK
tTX_F1/tTX_F2
0.3×DVDD
Fig.10 Parallel Data Input AC Timing
Table 13. Parallel Data Input AC Timing
Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Symbol
Limits
Unit
Conditions
Min
Typ
Max
fTX_PCLK1
4
-
15
MHz
LS0=L, LS1=L
fTX_PCLK2
8
-
30
MHz
LS0=H, LS1=L
fTX_PCLK3
12
-
45
MHz
LS0=L, LS1=H
tTX_DUTY
33
-
67
%
Input Data Setup Time
tTX_DS
5.0
-
-
ns
POL_PCLK=H
Input Data Hold Time
tTX_DH
5.0
-
-
ns
POL_PCLK=H
Input Signal Rise Time 1
tTX_R1
-
-
10
ns
PCLK Frequency≦30MHz
Input Signal Rise Time 2
tTX_R2
-
-
5
ns
PCLK Frequency>30MHz
Input Signal Fall Time 1
tTX_F1
-
-
10
ns
PCLK Frequency≦30MHz
Input Signal Fall Time 2
tTX_F2
-
-
5
ns
PCLK Frequency>30MHz
PCLK Input Frequency
PCLK Input Duty Cycle
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2010.04 - Rev.A
Technical Note
BU7963GUW
3) Serial Data Input Timing
Fig.11 and Table 14 shows Serial Data Input Timing of BU7963GUW.
1.0000 ×UI
CLK+/ -
tTXO_N
tTXO_N
tTXO_N
tTXO_N
D0+/ -
UI = (1 cycle time of CLK +/ - ) / 30
N = Bit position (0 ≦ N ≦ 30 )
Fig.11. Serial Data input AC Timing
Table 14. Serial Data input AC Timing
Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Output location CLKL+/- of N bit
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Symbol
tTXO_N
Limits
Min
Typ
Max
-0.1845×UI
+ UI×N
UI×N
0.1845×UI
+ UI×N
13/19
Unit
Conditions
sec
2010.04 - Rev.A
Technical Note
BU7963GUW
4) Power-On / Off Sequence
Power-On Sequence
Fig.12 shows power-on sequence of BU7963GUW.
DVDD,MSVDD of Tx
tTX_VDD_XSD
XSD of Tx
PCLK of Tx
t TX_IN_VAL
Provided
Stopped
tTX_OUT_VAL
Tx MSDL3 Output
HiZ
Valid
DVDD,MSVDD of Rx
tRX_VDD_XSD
XSD of Rx
Rx Power mode
t RX_IN_VAL
Standby / Active
Shutdown
t RX_OUT_VAL
Rx All Outputs
Valid Outputs
Initial Value
Tx: BU7963GUW
Rx: BU7964GUW
Fig.12. Power-On / Off Sequence
Table 15. Power-On Sequence Timing
Ta=25°C, DVDD=MS VDD=1.80V, and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Symbol
Limits
Min
Typ
Max
Unit
Core power supply startup time
tTX_VDD_IOV
0.0
-
2
ms
Reset Valid After Power Supplied
tTX_VDD_XSD
10
-
-
µs
tTX_IN_VAL
10
-
-
µs
tTX_OUT_VAL
-
-
2
ms
PCLK clock input startup time
MSDL3 output delay time
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Conditions
2010.04 - Rev.A
Technical Note
BU7963GUW
Power-Off Sequence
Fig.13 shows the power-off sequence of BU7963GUW.
PCLK of Tx
Provided
Stopped
t
Tx MSDL3 Output
TX_OUT_INV
HiZ
Valid
t RX_OUT_INV
Rx All Outputs
Valid Outputs
Initial Value
XSD of Tx
DVDD,MSVDD of Tx
t TX_XSD_VDD
XSD of Rx
DVDD,MSVDD of Rx
t RX_XSD_VDD
Tx: BU7963GUW
Rx: BU7964GUW
Fig.13. Power-Off Sequence
Table 16. Power-Off Sequence Timing
Ta=25°C, DVDD=MSVDD=1.80V, and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Symbol
Limits
Min
Typ
Max
-
-
100
Unit
MSDL3 output delay time
tTX_OUT_INV
XSD hold time
tTX_XSD_VDD
10
-
-
µs
Core power off time
tTX_VDD_IOV
0.0
-
2
ms
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Conditions
µs
2010.04 - Rev.A
Technical Note
BU7963GUW
Frequency Change Sequence
Fig.14 shows the frequency change sequence of BU7963GUW.
DVDD, MSVDD
of Tx and Rx
tTX_XSD_OUT
XSD of Tx
PCLK of Tx
tTX_IN_XSD
Frequency1
Frequency2
tTX_XSD_CTL
PLL_BW of Tx
tTX_CTL_XSD
State1
State2
XSD of Rx
tRX_XSD_CTL
PLL_BW[1:0] of Rx
tRX_CTL_XSD
State1
State2
Tx:BU7963GUW
Rx:BU7964GUW
Fig.14. Frequency Change Sequence
Table 17. Frequency Change Sequence
Ta=25°C, DVDD=MSVDD=1.80V, and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Symbol
Limits
Unit
Min
Typ
Max
tTX_XSD_OUT
1.0
-
-
µs
tTX_IN_XSD
1.0
-
-
µs
Control Signal Hold Time
tTX_XSD_CTL
2.0
-
-
µs
Control Signal Setup Time
tTX_CTL_XSD
2.0
-
-
µs
PCLK Clock Input Suspend Time
PCLK Clock Input Restart Time
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16/19
Conditions
2010.04 - Rev.A
Technical Note
BU7963GUW
●High-speed Channel Characteristic
Table 18. High-speed channel characteristic
Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Limits
Symbol
Min
Typ
Max
100
150
200
Unit
Differential Voltage Range
Vdiff_tx
Common Mode Voltage Range
Vcm_tx
0.8
0.9
1.0
V
tr_tx
200
-
500
ps
Vdiff_tx Rise Time
Vdiff_tx Fall Time
TX Hi-Z State Leak Current
mVpp
tf_tx
200
-
500
ps
fopr_tx
-
-
225
MHz
ILEAK_TX
-3
-
3
µA
Operating Frequency
Conditions
Shutdown mode or standby mode
fopr_tx
Single-ended
OutP(D0+,D1+,D2+)
Vcm_tx
OutN(D0-,D1-,D2-)
20%
Vdiff_tx
Differential
(OutP-OutN)
0
60%
20%
tr_tx
tf_tx
Fig.15. High-Speed Channel Electrical Characteristics
Fig.16 shows high-speed channel equivalent schematic.
MSDL3 TX
MSVDD
MSDL3 RX
Transmission
line
VO+
ILEAK_RX
ILEAK_TX
MSVDD
Logical input
to
MSDL3 TX
RTX/ 2
RRX/ 2
RTX/ 2
RRX/ 2
VO- I
LEAK_TX
VI+
Logical output
from
MSDL3 RX
VI-
MSGND
MSVDD
ILEAK_RX
IPULL_RX
MSGND
MSGND
V CM
VLINK_RX
Link detection
comparator
output
MSGND
Fig.16. high-speed channel equivalent schematic.
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17/19
2010.04 - Rev.A
Technical Note
BU7963GUW
●Application Circuit Example
1.8V
CLK-
D0+
D0-
D0+
D1+
D1-
D1+
D1-
D2+
D2-
D2+
D2-
D0-
Pixel clock
DVDD
PCLK
27
PD[26:0]
CPO
R[7:0],G[7:0],B[7:0],
HS,VS,DE
DVDD
PLLBW1
PLLBW0
PLLBW
POL_PCLK
LS1
LS0
DRVR
RVS
WVGA
LCD panel
LS1
LS0
DRVR
XSD
TEST[1:0]
DGND
MSVDD
MSGND
CLK+
CLK-
BU7964GUW
(Rx device)
CKD
CLK+
Video Mode
LCD Controller
Reset
Reset
DVD
D
GND
F_XS
TEST[1:0]
XSD
PD[26:0]
1.8V
10KΩ±5%
27
1.8V
GND
10KΩ±5%
DVDD
PCLK
BU7963GUW
(Tx device)
R[7:0],G[7:0],B[7:0],
HS,VS,DE
MSVDD
DGND
Pixel clock
100p×3
100p×2
DGND
100p×2
100p×3
MPU
1.8V 1.8V
0.1μ×3
0.1μ×2
0.1μ×2
MSGND
1.8V
0.1μ×3
MSGND
MSGND
DGND
Fig.17. Application circuit
●PCB Layout for MSDL3
The following points should be considered about the wiring for PCB of MSDL3.
・
・
・
・
Wire for the PCB wiring pattern of high-speed channel (CLK, D0+/-, D1+/-, D2+/-) as short as possible.
The PCB wiring for high-speed channel must not use the through-hole.
Do not bend the wiring for high-speed channel squarely.
Make the wiring length of each high-speed channel the same length (within 0.5mm).
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18/19
2010.04 - Rev.A
Technical Note
BU7963GUW
●Ordering Part Number
B
U
7
Part No.
9
6
3
G
Part No.
U
W
Package
GUW: VBGA063W050
-
E
2
Packaging and forming specification
E2: Embossed tape and reel
VBGA063W050
<Tape and Reel information>
5.0 ± 0.1
5.0±0.1
0.08 S
63- φ 0.295±0.05
φ 0.05 M S AB
P=0.5×7
0.5
0.1
0.9MAX
1PIN MARK
Tape
Embossed carrier tape (with dry pack)
Quantity
2500pcs
Direction
of feed
S
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.75±0.1
0.5
B
12345678
0.75± 0.1
H
G
F
E
D
C
B
A
P=0.5× 7
A
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© 2010 ROHM Co., Ltd. All rights reserved.
1pin
(Unit : mm)
Reel
19/19
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.04 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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The Products are not designed or manufactured to be used with any equipment, device or
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R1010A
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