IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FEATURES: IDT74SSTU32864/ A/C/D/G DESCRIPTION: • • • • • • • • 1:1 and 1:2 registered buffer 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Maximum operating frequency: 340MHz • Available in 96-pin LFBGA package The SSTU32864 is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from the A configuration (when low) to B configuration (when high). The C1 input controls the configuration from the 25-bit 1:1 (when low) to 14-bit 1:2 (when high). This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cx inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTU32864 must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. The device monitors both DCS and CSR inputs and will gate the outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the device will function normally. The RESET input has priority over the DCS control and will force the inputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case the set-up time requirement for DCS would be the same as for the other D data inputs. The SSTU32864G has two slew control pins (ZOH and ZOL) used to optimize the signal integrity on the DIMM. APPLICATIONS: • Ideally suited for DDR2-400/533 (PC2 - 3200/ 4200) registered DIMM applications • Along with CSPU877/A/D, zero delay PLL clock buffer, provides complete solution for DDR2-400/533 DIMMs • SSTU32864 is optimized for DDR2 Raw cards B and C • SSTU32864A is optimized for DDR2 Raw card A • SSTU32864C/D/G are optimized for DDR2 Raw cards A, B, and C • SSTU32864G has control pins for output slew rate control The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE APRIL 2006 1 c 2006 Integrated Device Technology, Inc. DSC-5980/27 IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM (1:2) RESET CLK CLK VREF DCKE QCKEA 1D C1 R DODT QCKEB QODTA 1D C1 R DCS QODTB QCSA 1D C1 R QCSB CSR Dx O 1 QxA 1D C1 R TO 10 OTHER CHANNELS 2 QxB IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION (TYPE A) 6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B 5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 2 NC NC NC NC NC NC RESET DCS CSR NC NC NC NC NC NC NC 1 DCKE D2 D3 DODT D5 D6 NC CLK CLK D8 D9 D10 D11 D12 D13 D14 A B C D E F G H J K L M N P R T 96-PIN LFBGA 1:2 REGISTER (TYPE A, FRONTSIDE) TOP VIEW PIN CONFIGURATION (TYPE B) 6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B QODTB Q12B Q13B QCKEB 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A QODTA Q12A Q13A QCKEA 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 2 NC NC NC NC NC NC RESET DCS CSR NC NC NC NC NC NC NC 1 D1 D2 D3 D4 D5 D6 NC CLK CLK D8 D9 D10 DODT D12 D13 DCKE A B C D E F G H J K L M N P R T 96-PIN LFBGA 1:2 REGISTER (TYPE B, BACKSIDE) TOP VIEW 3 IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM (1:1) RESET CLK1 CLK1 VREF DCKE 1D C1 QCKE C1 QOTD C1 QCS C1 Qx R DODT 1D R DCS 1D R CSR Dx O 1 1D R TO 21 OTHER CHANNELS 4 IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION 6 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 2 NC D15 D16 NC D17 D18 RESET DCS CSR D19 D20 D21 D22 D23 D24 D25 1 DCKE D2 D3 DODT D5 D6 NC CLK CLK D8 D9 D10 D11 D12 D13 D14 A B C D E F G H J K L M N P R T *Rows 3 and 4 are reserved for VDD and GND. 96-PIN LFBGA 1:1 REGISTER TOP VIEW 96 BALL LFBGA PACKAGE ATTRIBUTES 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Top Marking TOP VIEW A B C D E F G H J K L M N P R T 1 2 3 4 5 6 BOTTOM VIEW 5 SIDE VIEW IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE FUNCTION TABLE (EACH FLIP-FLOP) (1) Inputs Qx QCSx QODTx, QCKEx RESET DCS CSR CLK CLK Dx, DODT, DCKE Outputs Output Outputs H L L ↑ ↓ L L L L H L L ↑ ↓ H H L H (2) Q0(2) H L L L or H L or H X Q0 H L H ↑ ↓ L L L L H L H ↑ ↓ H H L H H L or H L or H H H L ↑ ↓ L L H L H H L ↑ ↓ H H H H H H L L or H L or H X Q0(2) Q0(2) Q0(2) H H H ↑ ↓ L Q0(2) H L H Q0 (2) H H Q0 (2) ↑ H ↓ H H H L or H L or H X L X or Floating X or Floating X or Floating X or Floating X or Floating L Q0 Q0(2) L H Q0 (2) H H X (2) Q0 (2) Q0 (2) L Q0(2) L NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2. Output level before the indicated steady-state conditions were established. MODE SELECT OUTPUT CONTROL (SSTU32864G) C0 C1 ZOH ZOL 0 0 1:1 25-bit to 25-bit Device Mode 0 0 Standard 0 1 1:2 14-bit to 28-bit, Front (Type A) 0 1 Highest 1 0 Reserved 1 0 Low 1 1 1:2 14-bit to 28-bit, Back (Type B) 1 1 High 6 Output Slew Rate IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol VDD VI (2,3) Description Supply Voltage Range Max. Unit –0.5 to 2.5 V Input Voltage Range –0.5 to 2.5 V VO(2,3) Output Voltage Range –0.5 to VDD +0.5 V IIK Input Clamp Current ±50 mA ±50 mA ±50 mA ±100 mA –65 to +150 °C VI < 0 VI > VDD IOK Output Clamp Current VO < 0 VO > VDD IO Continuous Output Current, VO = 0 to VDD VDD Continuous Current through each VDD or GND TSTG Storage Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum. TERMINAL FUNCTIONS (ALL PINS) Terminal Name Electrical Characteristics GND Ground Input Ground VDD 1.8V nominal Power Supply Voltage Input Reference Voltage Description VREF 0.9V nominal ZOH(1) LVCMOS Output Slew Rate Control ZOL(1) LVCMOS Output Slew Rate Control CLK Differential Input Positive Master Clock Input CLK Differential Input Negative Master Clock Input Cx LVCMOS Input Configuration Control Inputs RESET LVCMOS Input Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers. CSR, DCS SSTL_18 Input Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH. Dx SSTL_18 Input Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. DODT SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls DCKE SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls Qx 1.8V CMOS Data Outputs that are suspended by the DCS and CSR controls QCSx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls QODTx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls QCKEx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls NOTE: 1. The signals will be left unconnected for the SSTU32864/A/C/D. 7 IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25ºC (1,2) Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage 1.7 — 1.9 V VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V V TT Termination Voltage VREF– 40mV VREF VREF+ 40mV V 0 — VDD V VI Input Voltage VIH AC High-Level Input Voltage Data Inputs VREF+ 250mV — — V VIL AC Low-Level Input Voltage Data Inputs — — VREF– 250mV V VIH DC High-Level Input Voltage Data Inputs VREF+ 125mV — — V VIL DC Low-Level Input Voltage Data Inputs — — VREF– 125mV V VIH High-Level Input Voltage RESET, Cx 0.65 * VDD — — V VIL Low-Level Input Voltage RESET, Cx — — 0.35 * VDD V VICR Common Mode Input Voltage CLK, CLK 0.675 — 1.125 V VID Differential Input Voltage CLK, CLK 600 — — mV IOH High-Level Output Current — — –8 mA IOL Low-Level Output Current — — 8 TA Operating Free-Air Temperature 0 — 70 °C NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ±0.1V Symbol Test Conditions Min. Typ. VOH VDD = 1.7V to 1.9V, IOH = –6mA 1.2 VOL VDD = 1.7V to 1.9V, IOL = 6mA — II IDD IDDD Parameter Max. Unit — — V — 0.5 V All Inputs VI = VDD or GND –5 — 5 μA Static Standby IO = 0, VDD = 1.9V, RESET = GND — — 100 μA Static Operating IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) — — 40 mA Dynamic Operating IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), — — — μA/Clock (Clock Only) CLK and CLK Switching 50% Duty Cycle. 1:1 Mode — — — 1:2 Mode — — — 2.5 — 3.5 IO = 0, VDD = 1.8V, RESET = VDD, Dynamic Operating VI = VIH (AC) or VIL (AC), CLK and CLK Switching at (Per Each Data Input) 50% Duty Cycle. One Data Input Switching at Data Inputs VI = VREF ± 250mV MHz μA/Clock Half Clock Frequency, 50% Duty Cycle. CI Input CLK and CLK VICR = 0.9V, VID = 600mV 2 — 3 RESET VI = VDD or GND 2 — 4 8 MHz/Data pF IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 1.8V ± 0.1V Symbol Parameter fCLOCK(1) Min. Max. Unit Clock Frequency — 340 MHz Pulse Duration, CLK, CLK HIGH or LOW 1 — ns tACT(2) Differential Inputs Active Time — 10 ns tINACT(3) Differential Inputs Inactive Time — 15 ns DCS before CLK↑, CLK↓, CSR HIGH 0.7 — DCS before CLK↑, CLK↓, CSR LOW 0.5 — DODT, CSR, Data, and DCKE before CLK↑, CLK↓ 0.5 — Data, DCS, CSR, DCKE, and DODT after CLK↑, CLK↓ 0.5 — tw tSU Setup Time tH Hold Time ns ns NOTES: 1. 270MHz max clock frequency for parts assembled and tested prior to WW37. 2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH. 3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW. SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1) VDD = 1.8V ± 0.1V Symbol fMAX tPDM(2) tPDMSS(2,3) tRPHL dV/dt_r dV/dt_f dV/dt_Δ(4) Parameter Min 340 1.41 — — 1 1 — CLK and CLK to Q CLK and CLK to Q (simultaneous switching) RESET to Q Output slew rate from 20% to 80% Output slew rate from 20% to 80% Output slew rate from 20% to 80% NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. This parameter is not production tested. 4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 9 Max. — 2.15 2.35 3 4 4 1 Unit MHz ns ns ns V/ns V/ns V/ns IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) VDD DUT RL = 1KΩ TL = 50Ω CLK CLK CLK Inputs TL = 350ps, 50Ω Test Point Out CL = 30 pF RL = 1KΩ Test Point RL = 100Ω Load Circuit Test Point VDD LVCMOS RESET Input VDD/2 VDD/2 0V CLK tACT tINACT 90% IDD VICR VICR CLK tPLH VID tPHL VOH 10% Output VTT VTT VOL Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times tW Input VICR VICR VID LVCMOS RESET Input Voltage Waveforms - Pulse Duration VIH VDD/2 VIL tRPHL VOH Output VTT VOL CLK VICR VID CLK Voltage Waveforms - Propagation Delay Times tSU tH VIH Input VREF VREF VIL Voltage Waveforms - Setup and Hold Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. 10 IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) VDD DUT RL = 50Ω Out Test Point CL = 10 pF Load Circuit: High-to-Low Slew-Rate Adjustment Output VOH 80% 20% dv_f VOL dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out Test Point CL = 10 pF RL = 50Ω Load Circuit: Low-to-High Slew-Rate Adjustment dt_r VOH dv_r 80% 20% VOL Output Voltage Waveforms: Low-to-High Slew-Rate Adjustment NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 11 IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX XXX XX SSTU32 Temp. Range Device Type Package X Shipping Carrier 8 Blank Tape and reel Tray BF BFG Low Profile, Fine Pitch, Ball Grid Array LFBGA - Green 864 864A 864C 864D 864G 74 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 12 1:1 and 1:2 Registered Buffer with 1.8V SSTL I/O 0°C to +70°C for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com