SpectraLinear CY28339 Intel ck408 mobile clock synthesizer Datasheet

CY28339
Intel£ CK408 Mobile Clock Synthesizer
Features
• Compliant with Intel® CK 408 rev 1.1 Mobile Clock
Synthesizer specifications
• One VCH clock
• 3.3V power supply
• SMBus support with read-back capabilities
• Two differential CPU clocks
• Nine copies of PCI clocks
• Ideal Lexmark profile Spread Spectrum electromagnetic interference (EMI) reduction
• Three copies configurable PCI free-running clocks
• Dial-a-Frequency™ features
• Two 48 MHz clocks (USB, DOT)
• Dial-a-dB™ features
• Five/six copies of 3V66 clocks
• 48-pin TSSOP package
Table 1. Frequency
• One reference clock at 14.318 MHz
Table[1]
S2
S1
CPU (1:2)
3V66
66BUFF(0:2)/
3V66(0:4)
1
0
100M
66M
66IN
66-MHz clock input
66IN/2
14.318M
48M
1
1
133M
66M
66IN
66-MHZ clock input
66IN/2
14.318M
48M
0
0
100M
66M
66M
66M
33 M
14.318M
48M
0
1
133M
66M
66M
66M
33 M
14.318M
48M
M
0
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
66IN/3V66–5
Block Diagram
X1
X2
REF
PWR
Stop
Clock
Control
PWR
Stop
Clock
Control
1
48
VDD_REF
XOUT
2
47
REF
GND_REF
3
46
S1
VDD_CPU
CPUT1:2
PCI7
4
45
CPU_STOP#
PCI8
5
44
VDD_CPU
CPUC1:2
PCIF
6
43
CPUT1
GND_PCI
7
42
CPUC1
VDD_PCI
PCIF
PCI0
8
41
GND_CPU
PCI1
9
40
VDD_CPU
PCI0:2
PCI2
39
CPUT2
PCI4:8
10
VDD_PCI
11
38
CPUC2
PCI4
37
IREF
PCI5
12
13
/2
36
S2
PCI6
14
35
USB_48MHz
VDD_3V66
GND_3V66
15
34
DOT_48MHz
16
33
66BUFF0/3V66_2
66BUFF1/3V66_3
66BUFF2/3V66_4
17
32
VDD_48 MHz
GND_48 MHz
18
31
19
30
VDD_3V66
PWR
3V66_0:1
PWR
3V66_2:4/
66BUFF0:2
3V66_5/ 66IN
PLL 2
66IN/3V66_5
20
29
USB (48MHz)
PD#
21
28
VDD_3V66
DOT (48MHz)
VDD_CORE
22
27
GND_CORE
VTT_PWRGD#
23
26
GND_3V66
SCLK
24
25
SDATA
VCH_CLK/ 3V66_1
SDATA
SCLK
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_48MHz
PWR
CY28339
PCI_STOP#
Top View
XIN
Divider
Network
Gate
PD#
USB/ DOT
VDD_REF
PWR
PLL Ref Freq
S1:2
VTT_PWRGD##
CPU_STOP#
REF
Pin Configuration
XTAL
OSC
PLL 1
PCIF, PCI
SMBus
Logic
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device’s internal state register.
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 17
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
CY28339
Pin Definitions
Pin Number
Name
I/O
Description
47
REF0
3.3V 14.318 MHz clock output.
1
XIN
14.318 MHz crystal input.
2
XOUT
14.318 MHz crystal input.
43, 42,
39, 38
CPUT1,CPUC1
CPUT2, CPUC2
Differential CPU clock outputs.
29
3V66_0
3.3V 66 MHz clock output.
31
3V66_1/VCH
3.3V selectable through SMBus to be 66 MHz or 48 MHz.
20
66IN/3V66_5
66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal
VCO.
17, 18, 19
66BUFF [2:0] /3V66
[4:2]
66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO.
6
PCIF
33 MHz clocks divided down from 66Input or divided down from 3V66; PCIF
default is free-running.
8, 9, 10, 12, 13, 14, PCI [0:2]
4, 5
PCI [4:6]
PCI [7:8]
PCI clock outputs divided down from 66Input or divided down from 3V66;
PCI [7:8] are configurable as free-running PCI through SMBus.[2]
35
USB_48M
Fixed 48 MHz clock output.
34
DOT_48M
Fixed 48 MHz clock output.
36
S2
Special 3.3V three-level input for Mode selection.
46
S1
3.3V LVTTL inputs for CPU frequency selection.
37
IREF
A precision resistor is attached to this pin which is connected to the internal
current reference.
21
PD#
3.3V LVTTL input for Power_Down# (active LOW).
30
PCI_STOP#
3.3V LVTTL input for PCI_STOP# (active LOW).
45
CPU_STOP#
3.3V LVTTL input for CPU_STOP# (active LOW).
24
VTT_PWRGD#
3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1]
inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD#
is sampled LOW, the status of this input will be ignored.
25
SDATA
SMBus-compatible SDATA.
26
SCLK
SMBus-compatible SCLK.
11, 15, 28, 40, 44, VDD_PCI,
48
VDD_3V66,
VDD_CPU,VDD_REF
3.3V power supply for outputs.
33
VDD_48 MHz
3.3V power supply for 48 MHz.
22
VDD_CORE
3.3V power supply for phase-locked loop (PLL).
3, 7, 16, 27, 32, 41 GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
GND_CPU
Ground for outputs.
23
Ground for PLL.
GND_CORE
Note:
2. PCI3 is internally disabled and is not accessible.
Rev 1.0, November 25, 2006
Page 2 of 17
CY28339
Two-Wire SMBus Control Interface
Serial Control Registers
The two-wire control interface implements a Read/Write slave
only interface according to SMBus specification.
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
The device will accept data written to the D2 address and data
may read back from address D3. It will not respond to any
other addresses, and previously set control registers are
retained as long as power in maintained on the device.
1. “Command code“ byte
2. “Byte count” byte.
Although the data (bits) in the command is considered “don’t
care,” it must be sent and will be acknowledged. After the
Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid and acknowledged.
Byte 0: CPU Clock Register[3,4]
Bit
@Pup
7
0
Name
Spread Spectrum Enable.
0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.
6
0
CPU Clock Power-down Mode Select.
0 = Drive CPUT to 2x IREF and drive CPUC LOW
1 = Tri-state all CPU outputs.
This is only applicable when PD# is LOW. It is not applicable to CPU_STOP#.
5
0
3V66_1/VCH 3V66_1/VCH Frequency Select
0 = 66M selected, 1 = 48M selected. This is a Read and Write control bit.
4
3
Description
Reserved
HW
PCI_STOP# Reflects the current value of the internal PCI_STOP# function when read. Internally PCI_STOP#
is a logical AND function of the internal SMBus register bit and the external PCI_STOP# pin.
2
HW
S2
Frequency Select Bit 2. Reflects the value of S2. This bit is Read-only.
1
HW
S1
Frequency Select Bit 1. Reflects the value of S1. This bit is Read-only.
0
1
Reserved
Byte 1: CPU Clock Register
Bit
@Pup
Name
Description
7
1
6
0
CPUT1, CPUC1 CPUT/C Output Functionality Control when CPU_STOP# is asserted.
CPUT2, CPUC2 0 = Drive CPUT to 6x IREF and drive CPUC LOW
1 = three-state all CPU outputs.
This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs
will be three-stated.
5
0
CPUT2, CPUC2 CPUT/C2 Functionality Control when CPU_STOP# is asserted.
0 = Stopped LOW,1 = Free Running. This is a Read and Write control bit.
4
0
CPUT1, CPUC1 CPUT/C1 Functionality Control When CPU_STOP# is asserted.
0 = Stopped LOW, 1 = Free Running. This is a Read and Write control bit.
3
0
2
1
CPUT2, CPUC2 CPUT/C2 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
1
1
CPUT1, CPUC1 CPUT/C1 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
0
1
Reserved
Reserved
Reserved
Notes:
3. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.
4. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.
Rev 1.0, November 25, 2006
Page 3 of 17
CY28339
Byte 2:PCI Clock Control Register (all bits are Read and Write functional)
Bit @Pup Name
Description
7
0
REF
6
1
PCI6 PCI6 Output Control. 0 = forced LOW, 1 = enabled
REF Output Control. 0 = high strength, 1 = low strength.
5
1
PCI5 PCI5 Output Control. 0 = forced LOW, 1 = enabled
4
1
PCI4 PCI4 Output Control. 0 = forced LOW, 1 = enabled
3
1
2
1
PCI2 PCI2 Output Control. 0 = forced LOW, 1 = enabled
1
1
PCI1 PCI1 Output Control. 0 = forced LOW, 1 = enabled
0
1
PCI0 PCI0 Output Control. 0 = forced LOW, 1 = enabled
Reserved
Byte 3: PCIF Clock and 48M Control Register (all bits are Read and Write functional)
Bit
@Pup
Name
Description
7
1
DOT_48M DOT_48M Output Control. 0 = forced LOW, 1 = enabled
6
1
USB_48M USB_48M Output Control. 0 = forced LOW,1 = enabled
5
0
PCIF
PCI_STOP# Control of PCIF. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
4
1
PCI8
PCI_STOP# Control of PCI8. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
3
1
PCI7
PCI_STOP# Control of PCI7. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
2
1
PCIF
PCIF Output Control. 0 = forced LOW, 1 = running
1
1
PCI_8
PCI_8 Output Control. 0 = forced LOW, 1 = running
0
1
PCI_7
PCI_7 Output Control. 0 = forced LOW, 1 = running
Byte 4: Control Register (all bits are Read and Write functional)
Bit
@Pup
7
0
Name
Description
6
0
5
1
3V66_0
4
1
3V66_1/VCH
3
1
3V66_5
2
1
19
66BUFF2/3V66_4 Output Enable. 0 = disable, 1 = enabled
1
1
18
66BUFF1/3V66_3 Output Enable. 0 = disable, 1 = enabled
0
1
66BUFF0/3V66_2
66BUFF0/3V66_2 Output Enable. 0 = disable, 1 = enabled
SS2 Spread Spectrum Control Bit. 0 = down spread, 1 = center spread).
Reserved. Set = 0.
3V66_0 Output Enable. 0 = disable, 1 = enabled
3V66_1/VCH Output Enable. 0 = disable, 1 = enabled
3V66_5 Output Enable. 0 = disable, 1 = enabled
Byte 5:Clock Control Register (all bits are Read and Write functional)
Bit
@Pup
7
0
Name
SS1 Spread Spectrum Control Bit.
6
1
SS0 Spread Spectrum Control Bit.
5
0
66IN to 66M delay Control MSB.
4
0
66IN to 66M delay Control LSB.
3
0
Reserved. Set = 0.
2
0
1
0
0
0
DOT_48M
Description
DOT_48M Edge Rate Control. When set to 1, the edge is slowed by 15%.
Reserved. Set = 0.
USB_48M
USB_48M edge rate control. When set to 1, the edge is slowed by 15%.
Byte 6: Silicon Signature Register[5] (all bits are Read-only)
Bit
@Pup
Rev 1.0, November 25, 2006
Name
Description
Page 4 of 17
CY28339
Byte 6: Silicon Signature Register[5] (all bits are Read-only)
7
0
6
0
5
0
4
1
3
0
2
0
1
1
0
1
Revision = 0001
Vendor Code = 0011
Byte 7: Reserved Register
Bit
@Pup
7
0
Name
Reserved. Set = 0.
Description
6
0
Reserved. Set = 0.
5
0
Reserved. Set = 0.
4
0
Reserved. Set = 0.
3
0
Reserved. Set = 0.
2
0
Reserved. Set = 0.
1
0
Reserved. Set = 0.
0
0
Reserved. Set = 0.
Byte 8: Dial-a-Frequency Control Register N
Bit
@Pup
Name
7
0
6
0
N6, MSB
5
0
N5
4
0
N4
3
0
N3
2
0
N2
1
0
N3
0
0
N0, LSB
Description
Reserved. Set = 0.
These bits are for programming the PLL’s internal N register. This access
allows the user to modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks (clocks that are generated from
the same PLL, such as PCI) remain at their existing ratios relative to the
CPU clock.
Byte 9: Dial-a-Frequency Control Register R
Bit
@Pup
Name
7
0
6
0
R5, MSB
5
0
R4
4
0
R3
3
0
R2
2
0
R1
1
0
R0
0
0
Description
Reserved. Set = 0.
DAF_ENB
These bits are for programming the PLL’s internal R register. This access
allows the user to modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks (clocks that are generated from
the same PLL, such as PCI) remain at their existing ratios relative to the
CPU clock.
R and N register mux selection. 0 = R and N values come from the ROM.
1 = data is loaded from DAF (SMBus) registers.
Note:
5. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
Rev 1.0, November 25, 2006
Page 5 of 17
CY28339
Dial-a-Frequency Features
Special Functions
SMBus Dial-a-Frequency feature is available in this device via
Byte8 and Byte9.
PCIF and IOAPIC Clock Outputs
S(1:0)
P
00
32005333
The PCIF clock outputs are intended to be used, if required,
for systems IOAPIC clock functionality. Any two of the PCIF
clock outputs can be used as IOAPIC 33-Mhz clock outputs.
They are 3.3V outputs will be divided down via a simple
resistive voltage divider to meet specific system IOAPIC clock
voltage requirements. In the event that these clocks are not
required, they can be used as general PCI clocks or disabled
via the assertion of the PCI_STOP# pin.
01
48008000
3V66_1/VCH Clock Output
10
96016000
11
64010667
The 3V66_1/VCH pin has a dual functionality that is selectable
via SMBus.
P is a large-value PLL constant that depends on the frequency
selection achieved through the hardware selectors (S1, S0).
P value may be determined from Table 2.
Table 2. P Value
Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0”
Dial-a-dB Features
SMBus Dial-a-dB feature is available in this device via Byte8
and Byte9.
The default condition for this pin is to power-up in a 66M
operation. In 66M operation this output is SSCG-capable and
when spreading is turned on, this clock will be modulated.
Spread Spectrum Clock Generation (SSCG)
Configured as VCH (48M), SMBus Byte0, Bit 5 = “1”
Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
therefore causing the average energy at any one point in this
band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a
certain percentage (which also determines the amount of EMI
reduction). In this device, Spread Spectrum is enabled by
setting specific register bits in the SMBus control bytes.
Table 3 is a listing of the modes and percentages of Spread
Spectrum modulation that this device incorporates.
In this mode, output is configured as a 48-Mhz non-spread
spectrum output that is phase-aligned with other 48M outputs
(USB and DOT) to within 1-ns pin-to-pin skew. The switching
of 3V66_1/VCH into VCH mode occurs at system power-on.
When the SMBus Bit 5 of Byte 0 is programmed from a “0” to
a “1,” the 3V66_1/VCH output may glitch while transitioning to
48M output mode.
PD# (Power-down) Clarification
SS2
SS1
SS0
Spread Mode
Spread%
0
0
0
Down
+0.00, –0.25
The PD# (power-down) pin is used to shut off all clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so has not to cause
glitches while transitioning to the LOW “stopped” state.
0
0
1
Down
+0.00, –0.50
PD# Assertion
0
1
0
Down
+0.00, –0.75
0
1
1
Down
+0.00, –1.00
1
0
0
Center
+0.13, –0.13
1
0
1
Center
+0.25, –0.25
1
1
0
Center
+0.37, –0.37
1
1
1
Center
+0.50, –1.50
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock, then on the next HIGH-to-LOW transition
of PCIF, the PCIF clock is stopped LOW. On the next
HIGH-to-LOW transition of 66BUFF, the 66BUFF clock is
stopped LOW. From this time, each clock will stop LOW on its
next HIGH-to-LOW transition, except the CPUT clock. The
CPU clocks are held with the CPUT clock pin driven HIGH with
a value of 2 × Iref, and CPUC undriven. After the last clock has
stopped, the rest of the generator will be shut down.
Table 3. Spread Spectrum
3V66-0
Tpci
PCI
PCI_F
Figure 1. Unbuffered Mode – 3V66_0 to PCI and PCIF Phase Relationship
Rev 1.0, November 25, 2006
Page 6 of 17
CY28339
PWRDWN#
CPUT 133MHz
CPUC 133MHz
PCI 33MHz
3V66
USB 48MHz
REF 14.318MHz
Figure 2. Power-down Assertion Timing Waveforms – Unbuffered Mode
6 6 B u ff
P C IF
PW RDW N#
CPU 133M Hz
CPU# 133M Hz
3V66
6 6 In
USB 48M Hz
R E F 1 4 .3 1 8 M H z
Figure 3. Power-down Assertion Timing Waveforms Figure – Buffered Mode
Rev 1.0, November 25, 2006
Page 7 of 17
CY28339
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
<1.8m S
30uS min
400uS m ax
66Buff1 / GMCH
66Buff
PCIF / APIC
33MHz
PCI 33M Hz
PW RDW N#
CPU 133MHz
CPU# 133MHz
3V66
66In
USB 48MHz
REF 14.318MHz
Figure 4. Power-down Deassertion Timing Waveforms – Buffered Mode
CPU_STOP# Clarification
CPU_STOP# Assertion
The CPU_STOP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function.
When CPU_STOP# pin is asserted, all CPUT/C outputs that
are set with the SMBus configuration to be stoppable via
assertion of CPU_STOP# will be stopped after being sampled
by two falling CPUT/C clock edges. The final state of the
stopped CPU signals is CPUT = HIGH and CPU0C = LOW.
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 “select”) × (Iref), and the CPUC signal
will not be driven. Due to external pull-down circuitry CPUC will
be LOW during this stopped state.
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 5. CPU_STOP# Assertion Waveform
Rev 1.0, November 25, 2006
Page 8 of 17
CY28339
CPU_STOP# Deassertion
The deassertion of the CPU_STOP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner (meaning that no short or
stretched clock pulses will be produces when the clock
resumes). The maximum latency from the deassertion to
active outputs is no more than two CPUC clock cycles.
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 6. CPU_STOP# De-assertion Waveform
Three-state Control of CPU Clocks Clarification
During CPU_STOP# and PD# modes, CPU clock outputs may
be set to driven or undriven (tri-state) by setting the corresponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
PCI_STOP# Assertion
The PCI_STOP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STOP# going LOW is 10 ns (tsetup) (see
Figure 2.) The PCIF clocks will not be affected by this pin if
their control bits in the SMBus register are set to allow them to
be free running.
t setup
P C I_S TP #
P C IF 33M
P C I 33M
Figure 7. PCI_STOP# Assertion Waveform
PCI_STOP# Deassertion
The deassertion of the PCI_STOP# signal will cause all
PCI(0:2, 4:8) and stoppable PCIF clocks to resume running in
a synchronous manner within two PCI clock periods after
PCI_STOP# transitions to a HIGH level.
The PCI STOP function is controlled by two inputs. One is the
device PCI_STOP# pin number 34 and the other is SMBus
Rev 1.0, November 25, 2006
Byte 0,Bit 3. These two inputs to the function are logically
AND’ed. If either the external pin or the internal SMBus
register bit is set LOW, the stoppable PCI clocks will be
stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will
return a 0 value if either of these control bits are set LOW
(which indicates that the devices stoppable PCI clocks are not
running).
Page 9 of 17
CY28339
t setup
PCI_STP#
PCIF
PCI
Figure 8. PCI_STOP# Deassertion Waveform
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
0.2-0.3mS
Delay
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
State 0
Wait for
Sample Sels
VTT_PWRGD#
State 1
State 2
Off
Device is not affected,
VTT_PWRGD# is ignored.
State 3
On
On
Off
Figure 9. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PWRGD# = Low
Delay
>0.25mS
Sample
Inputs straps
VDDA = 2.0V
Wait for <1.8ms
S0
Power Off
S3
Normal
Operation
VDD3.3= off
Enable Outputs
VTT_PWRGD# = toggle
Figure 10. Clock Generator Power-up/Run State Program
Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage at
the pin of the device.
Rev 1.0, November 25, 2006
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is ±7% as shown in
the current accuracy table.
Page 10 of 17
CY28339
Charlene: Mult0 is FIXED at 1.
Table 4. CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, Iref – Vdd (3*Rr)
Output Current
Voh @ Z
50:
Rr = 330 1%, Iref = 3.33mA
Ioh = 6*Iref
1.0V @ 50
50:
Rr = 475 1%, Iref = 2.32mA
Ioh = 6*Iref
0.7V @ 50
Table 5. Group Timing Relationship and Tolerances
Offset
Tolerance
3V66 to PCI
Description
2.5 ns
r1.0 ns
Conditions
USB_48M to DOT_48M Skew
0.0 ns
r1.0 ns
0 degrees phase shift
66BUFF(0:2) to PCI offset
2.5 ns
r1.0 ns
66BUFF leads PCI (buffered mode)
3V66 leads PCI (unbuffered mode)
USB_48M and DOT_48M Phase Relationship
66BUFF(0:2) to PCI Buffered Clock Skew
The USB_48M and DOT_48M clocks are in phase. It is understood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 11.
Figure 13 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The measurements were
taken at 1.5V.
66IN to 66BUFF(0:2) Buffered Prop Delay
3V66 to PCI Un-Buffered Clock Skew
The 66IN to 66BUFF(0:2) output delay is shown in
Figure 12.The Tpd is the prop delay from the input pin (66IN)
to the output pins (66BUFF[0:2]). The outputs’ variation of Tpd
is described in the AC parameters section of this data sheet.
The measurement taken at 1.5V.
Figure 1 shows the timing relationship between 3V66_0 and
PCI(0:2,4:8) and PCIF when configured to run in the unbuffered mode.
USB_48M
DOT_48M
Figure 11. USB_48M and DOT_48M Phase Relationship
66IN
Tpd
66B
Figure 12. 66IN to 66BUFF(0:2) Output Delay Figure
66B
1.53.5ns
PCI
PCIF
Figure 13. Buffer Mode – 33V66_0; 66BUFF(0:2) Phase Relationship
Rev 1.0, November 25, 2006
Page 11 of 17
CY28339
Buffer Characteristics
1. Output impedance of the current mode buffer circuit – Ro
(see Figure 14).
Current Mode CPU Clock Buffer Characteristics
2. Minimum and maximum required voltage operation range
of the circuit – Vop (see Figure 14).
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
3. Series resistance in the buffer circuit – Ros (see Figure 14).
4. Current accuracy at given configuration into nominal test
load for given configuration.
VDD3 (3.3V +/- 5%)
Slope ~ 1/R0
Ro
Iout
Ros
0V
1.2V
Iout
Vout = 1.2V max
Vout
Figure 14. Buffer Characteristics
Table 6. Host Clock (HCSL) Buffer Characteristics
Characteristic
Min.
Max.
Ro
3000: (recommended)
N/A
N/A
1.2V
Ros
Vout
Table 7. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Units
PCI Clocks
30
pF
3V66
30
pF
66BUFF
30
pF
USB_48M Clock
20
pF
DOT_48M
10
pF
REF Clock
50
pF
Rev 1.0, November 25, 2006
Page 12 of 17
CY28339
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
–0.5
4.6
V
VDD
Core Supply Voltage
VDD_A
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to V SS
–0.5
VDD + 0.5
VDC
–65
150
°C
0
70
°C
–
150
°C
2000
–
Volts
TS
Temperature, Storage
Non Functional
TA
Temperature, Operating Ambient
Functional
TJ
Temperature, Junction
Functional
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
45
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
15
°C/W
UL-94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
V–0
1
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
3.135
3.465
V
All frequencies at maximum
values
–
280
mA
PD# Asserted
–
VDD_A,
3.3 Operating Voltage
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
3.3 ± 5%
IDD3.3V
Dynamic Supply Current
IPD3.3V
Power Down Supply Current
CIN
Input Pin Capacitance
–
5
pF
COUT
Output Pin Capacitance
–
6
pF
LIN
Pin Inductance
–
7
nH
CXTAL
Crystal Pin Capacitance
30
42
pF
Measured from the XIN
mA
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
TPERIOD
XIN period
When Xin is driven from an external clock source 69.841
71.0
ns
TR / TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–
10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1Ps duration
–
500
ps
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
66MHz CPUT and CPUC Period
Measured at crossing point VOX
14.85
15.3
ns
TPERIOD
100MHz CPUT and CPUC Period
Measured at crossing point VOX
9.85
10.2
ns
TPERIOD
133MHz CPUT and CPUC Period
Measured at crossing point VOX
7.35
7.65
ns
TPERIOD
200MHz CPUT and CPUC Period
Measured at crossing point VOX
4.85
5.1
ns
TSKEW
Any CPUT/C to CPUT/C Clock Skew Measured at crossing point VOX
–
100
ps
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
150
ps
TR / TF
CPUT and CPUC Rise and Fall
Times
Measured from Vol= 0.175 to Voh = 0.525V
175
700
ps
Rev 1.0, November 25, 2006
Page 13 of 17
CY28339
AC Electrical Specifications (continued)
Parameter
Description
Min.
Max.
Unit
–
20
%
Rise Time Variation
–
125
ps
Fall Time Variation
–
125
ps
280
430
mv
Measured at crossing point VOX
45
55
%
TRFM
Rise/Fall Matching
'TR
'TF
VOX
Crossing Point Voltage at 0.7V
Swing
TDC
CPUT and CPUC Duty Cycle
Condition
Determined as a fraction of 2*(TR-TF)/(TR+TF)
CPU at 1.0 Volts
TPERIOD
66MHz CPUT and CPUC Period
Measured at crossing point VOX
14.85
15.3
ns
TPERIOD
100MHz CPUT and CPUC Period
Measured at crossing point VOX
9.85
10.2
ns
TPERIOD
133MHz CPUT and CPUC Period
Measured at crossing point VOX
7.35
7.65
ns
TPERIOD
200MHz CPUT and CPUC Period
Measured at crossing point VOX
4.85
5.1
ns
TSKEW
Any CPUT/C to CPUT/C Clock Skew Measured at crossing point VOX
–
100
ps
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at crossing point VOX
–
150
ps
TR / TF
CPUT and CPUC Rise and Fall
Times
Measured from Vol= 0.175 to Voh = 0.525V
175
467
ps
VOX
Crossing Point Voltage at 0.7V
Swing
510
760
mv
–
325
ps
45
55
%
SE_ 'Slew Absolute Single-ended Rise/Fall
Waveform Symmetry
3V66
TDC
3V66 Duty Cycle
Measurement at 1.5V
TPERIOD
3V66 Period
Measured at crossing point VOX
15.0
15.3
ns
THIGH
3V66 High Time
Measurement at 2.4V
4.95
–
ns
TLOW
3V66 Low Time
Measurement at 0.4V
4.55
–
ns
TR / TF
3V66 Rise and Fall Times
Measured between 0.4V and 2.4V
0.5
2.0
ns
TSKEWUN-
Any 3V66 to Any 3V66 Clock Skew
Measurement at 1.5V
–
500
ps
Any 3V66 to Any 3V66 Clock Skew
Measurement at 1.5V
–
250
ps
3V66 Cycle to Cycle Jitter
Measurement at 1.5V
–
250
ps
BUFFERED
TSKEWBUFFERED
TCCJ
66BUFF
TDC
66BUFF Duty Cycle
Measurement at 1.5V
45
55
%
TR / TF
66BUFF Rise and Fall Times
Measured between 0.4V and 2.4V
0.5
2.0
ns
TSKEW
Any 66BUFF to Any 66BUFF Skew
Measurement at 1.5V
TCCJ
66BUFF Cycle to Cycle Jitter
Measurement at 1.5V
TPD
66IN to 66BUFF(Propagation Delay) Measurement at 1.5V
–
175
ps
100
ps
2.5
4.5
ns
55
PCI /PCIF
TDC
PCI /PCIF Duty Cycle
Measurement at 1.5V
45
TPERIOD
PCI /PCIF Period
Measured at crossing point VOX
30
%
ns
THIGH
PCI and PCIF high time
Measurement at 2.4V
12.0
–
nS
TLOW
PCI and PCIF low time
Measurement at 0.4V
12.0
–
nS
TR / TF
PCI and PCIF rise and fall times
Measured between 0.4V and 2.4V
0.5
2.0
nS
TSKEW
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
–
500
pS
TCCJ
PCIF and PCI Cycle to
Cycle Jitter
–
250
ps
Measurement at 1.5V
DOT_48M
Rev 1.0, November 25, 2006
Page 14 of 17
CY28339
AC Electrical Specifications (continued)
Parameter
Description
TDC
DOT_48M Duty Cycle
Min.
Max.
Unit
Measurement at 1.5V
Condition
45
55
%
20.83
20.83
ns
0.5
1.0
ns
–
350
ps
TPERIOD
DOT_48M Period
Measurement at 1.5V
TR / TF
DOT_48M Rise and Fall Times
Measured between 0.4V and 2.4V
TCCJ
DOT_48M Cycle to Cycle Jitter
Measurement at 1.5V
USB_48M
TDC
USB_48M Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
USB_48M Period
Measurement at 1.5V
20.82
20.83
ns
TR / TF
USB_48M Rise and Fall Times
Measured between 0.4V and 2.4V
1.0
2.0
ns
TCCJ
DOT_48M Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
45
55
REF
TDC
REF Duty Cycle
Measurement at 1.5V
TPERIOD
REF Period
Measurement at 1.5V
TR / TF
REF Rise and Fall Times
Measured between 0.4V and 2.4V
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
TPZL/TPZH
Output Enable Delay (All Outputs)
TPZL/TPZH
TSTABLE
69.827 69.855
%
ns
1.0
4.0
V/ns
–
1000
ps
1.0
10.0
ns
Output Disable Delay (All Outputs)
1.0
10.0
ns
Clock Stabilization from Power-up
–
3.0
ms
10.0
–
ns
0
–
ns
ENABLE/DISABLE and SETUP
TSS
Stopclock Set Up Time
TSH
Stopclock Hold Time
TSU
Oscillator Start-up time
When XIN is driven from external clock source
CPU_STOP# and PIC_STOP# set up time with
respect to PCIF clock to guarantee that the
effected clock will stop or start at the next PCIF
clock’s rising edge.
When crystal meets min. 40:device series resistance specification
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
TPCB
:
CPUT
M easurem ent P oint
2pF
:
CPUC
:
TPCB
:
:
M easurem ent P oint
2 pF
:
Figure 15. 1.0V Test Load Termination
Rev 1.0, November 25, 2006
Page 15 of 17
CY28339
T PCB
:
Measurement Point
CPUT
:
2pF
T PCB
:
Measurement Point
CPUC
2pF
:
:
Figure 16. 0.7V Test Load Termination
Output under Test
Probe
Load Cap
3.3V signals
tDC
-
-
3.3V
2.4V
1.5V
0.4V
0V
Tr
Tf
Figure 17. For Single-ended Output Signals
Rev 1.0, November 25, 2006
Page 16 of 17
CY28339
Ordering Information
Part Number
Package Type
Product Flow
CY28339ZC
48-pin TSSOP
Commercial, 0q to 70qC
CY28339ZCT
48-pin TSSOP – Tape and Reel
Commercial, 0q to 70qC
CY28339ZXC
48-pin TSSOP
Commercial, 0q to 70qC
CY28339ZCXT
48-pin TSSOP – Tape and Reel
Commercial, 0q to 70qC
Lead Free
Package Drawing and Dimensions
48-lead (240-mil) TSSOP II Z4824
0.500[0.019]
24
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
7.950[0.313]
8.255[0.325]
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.33gms
5.994[0.236]
6.198[0.244]
PART #
Z4824 STANDARD PKG.
ZZ4824 LEAD FREE PKG.
25
48
12.395[0.488]
12.598[0.496]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0.170[0.006]
0.279[0.011]
0.051[0.002]
0.152[0.006]
0°-8°
0.508[0.020]
0.762[0.030]
0.100[0.003]
0.200[0.008]
SEATING
PLANE
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 25, 2006
Page 17 of 17