ON NCP1237AD65R2G Fixed frequency current mode controller for flyback converter Datasheet

NCP1237
Fixed Frequency Current
Mode Controller for Flyback
Converters
The NCP1237 is a new generation of the NCP12xx fixed−frequency
current−mode controllers featuring Dynamic Self−Supply (DSS),
pin−to−pin compatible with the previous generation.
The DSS function greatly simplifies the design of the auxiliary supply
and the VCC capacitor by activating the internal startup current source to
supply the controller during transients.
Due to its proprietary Soft−Skip™ mode combined with frequency
foldback, the controller exhibits excellent efficiency in light load
condition while still achieving very low standby power consumption.
This Soft−Skip feature also dramatically reduces the risk of acoustic
noise, which enables the use of inexpensive transformers and
capacitors in the clamping network.
The NCP1237 features a dual−level timer−based fault detection that
controls the amount of transient peak power that the controller can
deliver for a limited time.
Internal frequency jittering, ramp compensation, and a versatile
latch input make this controller an excellent candidate for converters
where ruggedness and components cost are the key constraints.
In addition, the controller includes a new high voltage circuitry that
combines a startup current source and a brown−out / line OVP detector
able to sense the input voltage either from the rectified ac line or the dc
filtered bulk voltage.
Finally, due to a careful design, the precision of critical parameters
is well controlled over the entire temperature range (−40°C to
+125°C), enabling easier design and increased safety (e.g. ±5% for the
peak current limit, ±7% for the oscillator).
Features
• Timer−Based Transient Power and Overload
•
•
•
•
•
•
•
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MARKING
DIAGRAM
8
SOIC−7
CASE 751U
1
37Xff
ALYWX
G
37Xff = Specific Device Code
X = A or B
ff = 65, 00, or 33
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 32 of this data sheet.
• 65 kHz Oscillator (100 kHz and 133 kHz Versions
Protections with Auto−Recovery (Option B) or Latched
(Option A) Operation
High−Voltage Current Source with DSS with Built−in
Brown−out and Line Overvoltage Protections
Fixed−Frequency Current−Mode Operation with
Built−in Ramp Compensation
Frequency Jittering for a Reduced EMI Signature
Adjustable Overpower Compensation
Latch−off Input for Severe Fault Conditions, with
Direct Connection of an NTC for Overtemperature
Protection (OTP)
Protection Against Winding Short−Circuit
Frequency Foldback transitioning into Soft−Skip for
Improved Performance in Standby
•
•
•
•
•
•
Available Upon Request)
VCC Operation up to 28 V
Increased Precision on Critical Parameters
±1.0 A Peak Drive Capability
4.0 ms Soft−Start
Internal Thermal Shutdown with Hysteresis
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant*
Typical Applications
•
•
•
•
ac−dc Adapters for Notebooks, LCD, and Printers
Offline Battery Chargers
Consumer Electronic Power Supplies
Auxiliary/Housekeeping Power Supplies
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2010
February, 2010 − Rev. 1
1
Publication Order Number:
NCP1237/D
NCP1237
1
Latch
2
FB
3
4
HV
8
CS
VCC
6
GND
DRV
5
Figure 1. Pinout
TYPICAL APPLICATION EXAMPLE
VOUT
VIN
(dc)
LATCH
FB
HV
NCP1237
CS
VCC
GND
DRV
Figure 2. Typical Application
PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
1
LATCH
Latch−off Input
2
FB
Feedback
3
CS
Current Sense
4
GND
–
5
DRV
Drive Output
6
VCC
VCC Input
8
HV
High−Voltage Pin
Pin Description
Pull the pin up or down to latch−off the controller. An internal current
source allows the direct connection of an NTC for over temperature
detection
A pull−down optocoupler controls the output regulation.
Senses the primary current for current−mode operation, and provides a
mean for overpower compensation adjustment.
IC ground
Drives an external MOSFET
This supply pin accepts up to 28 Vdc
Connects to the bulk capacitor or the rectified AC line to perform the
functions of Dynamic Self−Supply and brown−out / line overvoltage
detections
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NCP1237
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
Brown−out
+
INTC
INTC
BO
HV stop
blanking
+
−
OVM
tLatch(OVP)
VOVP
−
+
VDD
HV dc
HV sample
HV
Latch
+
1 kW
−
+
VOTP
S
Q
R
Vclamp
TSD
TSD
blanking
tLatch(OTP)
Dual HV
start−up
current source
Latch
TSD HV current
Reset
VCC
UVLO
management
VDD
Start
Reset
UVLO
VDD
IC Start
Soft−start
end
Brown−out
Reset
FB
Soft−skip ramp
−
+
+
VDD
Reset
VCC
tSSKIP
Vskip
RFB(up)
Skip
KFB
FB
slope
comp.
HV sample
PWM
+
−
V to I
IOPC = 0.5m x
(VHV−125)
Jitter
Skip
Sawtooth
Soft−start
+
−
Stop Foldback
Oscillator
tSSTART
−
+
+
VFB(OPC)
Soft−start Start
ramp
Reset
End
S
+
blanking
ILIMIT
S
Q
R
Q
R
+
−
VILIM
tBCS
VCS(tran)
+
+
−
Clamp
DMAX
IC Stop
tLEB
DMAX
DCMAX
IC Start
Soft−start end
blanking
CS
FB
DRV
ILIMIT
IC stop
ITRAN
GND
UVLO
Fault Flag
+
tfault
ttran
ITRAN
Latch
Autorecovery
protection
mode only
VCS(stop)
PWM
R
Q
S
HV stop
Protection
Mode
release
+
−
timer
timer
tautorec
Fault
Brown−out
Reset
Figure 3. Simplified Internal Block Schematic
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TSD
NCP1237
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Pin (pin 6) (Note 2)
Voltage range
Current range
Rating
VCCMAX
ICCMAX
–0.3 to 28
$30
V
mA
High Voltage Pin (pin 8) (Note 2)
Voltage range
Current range
VHVMAX
IHVMAX
–0.3 to 500
$20
V
mA
Driver Pin (pin 5) (Note 2)
Voltage range
Current range
VDRVMAX
IDRVMAX
–0.3 to 20
$1000
V
mA
VMAX
IMAX
–0.3 to 10
$10
V
mA
All other pins (Note 2)
Voltage range
Current range
Thermal Resistance SOIC−7
Junction−to−Air, low conductivity PCB (Note 3)
Junction−to−Air, medium conductivity PCB (Note 4)
Junction−to−Air, high conductivity PCB (Note 5)
RqJA
Temperature Range
Operating Junction Temperature
Storage Temperature Range
TJMAX
TSTRGMAX
ESD Capability (Note 1)
Human Body Model (HBM) Model (All pins except HV)
Machine Model (MM)
162
147
125
−40 to +150
−60 to +150
2000
190
°C/W
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC standard JESD22, Method A114E
Machine Model Method 200 V per JEDEC standard JESD22, Method A115A
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 1 oz copper traces and heat spreading area. As specified
for a JEDEC 51−1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51−2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
5. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 1 oz copper traces and heat spreading area. As specified
for a JEDEC 51−3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
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NCP1237
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 120 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VHV(min)
−
−
60
V
Istart1
Istart2
0.2
4
0.5
8
0.8
12
mA
Istart(off)
−
25
50
mA
Turn−on threshold level, VCC going up
HV current source stop threshold
VCC(on)
11.0
12.0
13.0
V
HV current source restart threshold
VCC(min)
9.5
10.5
11.5
V
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source operation
Current flowing out of VCC pin @ VHV = 60 V
VCC = 0 V
VCC = VCC(on) − 0.5 V
Off−state leakage current
VHV = 500 V
SUPPLY
Turn−off threshold level
VCC(off)
8.5
9.5
10.5
V
tUVLO(blank)
7
10
13
ms
VCC decreasing level at which the internal logic resets
VCC(reset)
4.0
5.2
6.5
V
VCC level for ISTART1 to ISTART2 transition
VCC(inhibit)
0.4
0.65
0.9
V
DRV open, VFB = 3 V
ICC1
2.0
2.5
3.0
mA
Cdrv = 1 nF, VFB = 3 V
ICC2
2.3
3.3
4.3
Off mode (skip or before
startup)
Fault mode (fault or latch)
ICC3
0.9
1.2
1.5
ICC4
0.4
0.7
1.0
VHV(start)
VHV(stop)
104
97
112
105
120
113
V
tHV
43
61
79
ms
VHV(OV1)
VHV(OV2)
400
395
430
425
460
455
V
tOV(blank)
−
250
−
ms
Oscillator frequency
fOSC
60
65
70
kHz
Maximum duty ratio
DMAX
75
80
85
%
Blanking duration on VCC(min) and VCC(off) detection
Internal current consumption (Note 6)
Guaranteed by design
BROWN−OUT AND LINE OVERVOLTAGE
Brown−out threshold voltage
VHV going up
VHV going down
Timer duration for line cycle drop−out
Overvoltage threshold
VHV going up
VHV going down
Blanking duration on line overvoltage detection
OSCILLATOR
Frequency jittering amplitude, in percentage of FOSC
Guaranteed by design
Ajitter
$4
$6
$8
%
Frequency jittering modulation frequency
Guaranteed by design
Fjitter
85
125
165
Hz
Rise time, 10% to 90% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
trise
−
22
34
ns
Fall time, 90% to 10% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
tfall
−
22
34
ns
Current capability
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
DRV high, VDRV = 0 V
DRV low, VDRV = VCC
OUTPUT DRIVER
mA
IDRV(source)
IDRV(sink)
−
−
1000
1000
−
−
Clamping voltage (maximum gate voltage)
VCC = VCCmax – 0.2 V, DRV
high
VDRV(clamp)
11
13.5
16
V
High−state voltage drop
VCC = VCC(min) + 0.2 V,
RDRV = 33 kW, DRV high
VDRV(drop)
−
−
1
V
6. Internal supply current only, current in FB pin not included (current flowing through GND pin only).
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NCP1237
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 120 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
Ibias
−
0.02
−
mA
CURRENT SENSE
Input Bias Current
VCS = 0.7 V
Maximum internal current setpoint
VFB > 3.5 V
VILIM
0.665
0.7
0.735
V
VCS(stop)
0.95
1.05
1.15
V
tdelay
50
80
110
ns
Leading Edge Blanking Duration for VILIM
tLEB
190
250
310
ns
Leading Edge Blanking Duration for VCS(stop)
tBCS
90
120
150
ns
Scomp(65kHz)
−
−32.5
−
mV / ms
tSSTART
2.8
4.0
5.2
ms
KOPC
−
0.5
−
mA / V
IOPC(125)
IOPC(162)
IOPC(325)
IOPC(max)
−
−
−
102
0
52
104
120
−
−
−
138
mA
FB voltage above which IOPC is applied
VFB(OPC)
1.50
1.65
1.80
V
FB voltage below which IOPC = 0
VFB(OPCE)
−
1.25
−
V
tWD
25
35
45
ms
RFB(up)
15
20
25
kW
KFB
4.7
5.0
5.3
−
VFB(ref)
4.3
5.0
5.7
V
tfault
64
78
98
ms
tautorec
1.0
1.4
1.8
s
VCS(tran)
0.47
0.5
0.53
V
ttran
117
156
195
ms
VFB(fold)
1.3
1.4
1.5
V
fOSC(min)
21
27
31
kHz
VFB(endfold)
−
1.0
−
V
Vskip(in)
Vskip(out)
0.63
0.72
0.7
0.80
0.77
0.88
V
tSSKIP
−
100
−
ms
Threshold for immediate fault protection activation
Propagation delay from VILIM detection to DRV off
VCS = VILIM
Slope of the compensation ramp
Soft−start duration
1st
From
pulse to
VCS = VILIM
OVERPOWER COMPENSATION
VHV to IOPC conversion ratio
Current flowing out of CS pin
VHV = 125 V
VHV = 162 V
VHV = 325 V
VHV = VHV(OV2) − 5 V
Refresh operation for dc operation
FEEDBACK
Internal pull−up resistor
TJ = 25°C
VFB to internal current setpoint division ratio
Internal pull−up voltage on the FB pin
OVERCURRENT PROTECTION
Fault timer duration
From CS reaching VILIMIT to
DRV stop
Autorecovery mode latch−off time duration
CS threshold for transient peak timer activation
Transient peak power timer duration
VCS(peak) = VILIM – 5%
From 1st time VCS >
VCS(tran) to DRV stop
FREQUENCY FOLDBACK
Feedback voltage threshold below which frequency
foldback starts
Minimum switching frequency
VFB = Vskip(in) + 0.2 V
Threshold below which the frequency foldback is
finished and the controller switches at fOSC(min)
SKIP CYCLE MODE
Feedback voltage thresholds for skip mode
VFB going down
VFB going up
Soft−skip duration
From 1st pulse to VCS =
VFB(fold) / KFB
6. Internal supply current only, current in FB pin not included (current flowing through GND pin only).
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NCP1237
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 120 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
LATCH−OFF INPUT
High threshold
VLatch going up
VOVP
2.37
2.5
2.63
V
Low threshold
VLatch going down
VOTP
0.76
0.8
0.84
V
Current source for direct NTC connection
During normal operation
During soft−start
VLatch = 0 V
INTC
INTC(SSTART)
78
156
91
182
104
208
Blanking duration on high latch detection
tLatch(OVP)
40
55
70
ms
Blanking duration on low latch detection
tLatch(OTP)
−
400
−
ms
Vclamp0(Latch)
Vclamp1(Latch)
1.0
1.8
1.2
2.3
1.4
2.8
V
TTSD
135
150
165
°C
TTSD(HYS)
20
30
40
°C
Clamping voltage
ILatch = 0 mA
ILatch = 1 mA
mA
TEMPERATURE SHUTDOWN
Temperature shutdown
TJ going up
Temperature shutdown hysteresis
TJ going down
6. Internal supply current only, current in FB pin not included (current flowing through GND pin only).
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NCP1237
APPLICATION INFORMATION
Introduction
The NCP1237 includes all of the necessary features to build
a safe and efficient power supply based on a
fixed−frequency flyback converter. It is particularly well
suited for applications where low part count is a key
parameter, without sacrificing safety.
• Current−Mode Operation with slope compensation:
The primary peak current is permanently controlled by
the FB voltage, ensuring maximum safety: the DRV
turn−off event is dictated by the peak current setpoint.
It also ensures that the frequency response of the
system remains a first order if in DCM, which eases the
design of the feedback loop. The controller can also be
used in CCM with a wide input voltage range due to its
fixed ramp compensation that prevents the appearance
of sub−harmonic oscillations in most of the
applications.
• Fixed−Frequency Oscillator with Jittering: The
NCP1237 is available in various frequency options to
fit any application. The internal oscillator features a
low−frequency jittering that helps to pass the EMI
requirements by spreading out the energy content of
frequency peaks in quasi−peak and average mode.
• Latched / Autorecovery Timer−Based dual−level
Overcurrent Protection: The overcurrent protection
has 2 different levels. At the low level the controller
can still regulate but starts a long timer. The high level
corresponds to the loss of regulation and starts the usual
overload timer. This allows a power supply to
transiently deliver a higher power for a limited time.
The overcurrent protection depends only on the FB
signal, enabling it to work with any transformer, even
with very poor coupling or high leakage inductance.
Both protections are fully latched on the A version (the
power supply has to be unplugged then restarted in
order to resume operation, even if the overload
condition disappears), and autorecovery on the B
version. The timers’ durations are fixed. The controller
also enters the same protection mode if the voltage on
the CS pin reaches 1.5 times the maximum internal
setpoint, which enables to detect winding short circuits.
• High Voltage Startup Current Source with
Brown−Out and Line Overvoltage Detections: Due
to On Semiconductor’s Very High Voltage technology,
the NCP1237 can directly be connected to the high
input voltage. The startup current source ensures a
clean startup while ensuring low losses when it is off,
and the Dynamic Self−Supply (DSS) restarts the startup
current source to supply the controller if the VCC
supply transiently drops. The high voltage pin also
features a high−voltage sensing circuitry, which is able
to turn the controller off if the input voltage is too low
(brown−out condition) or too high (line overvoltage).
•
•
•
•
•
•
•
This protection works either with a DC input voltage or
a rectified AC input voltage, and is independent of the
high voltage ripple. It uses a peak detector
synchronized with line frequency, or with the internal
watchdog timer if the HV pin is tied to a dc voltage.
Adjustable Overpower Compensation: The high
voltage sensed on the HV pin is converted into a
current to add to the current sense voltage an offset
proportional to the input voltage. By choosing the value
of the resistor in series with the CS pin, the amount of
compensation can be adjusted to the application.
Frequency foldback then Soft−Skip mode for light
load operation: In order to ensure a high efficiency in
all load conditions, the NCP1237 implements a
frequency foldback (the switching frequency is lowered
to reduce switching losses) for light load condition; and
a Soft−Skip (disabled in case of fast load transients) for
extremely low load condition.
Extended VCC range: The NCP1237 accepts a supply
voltage as high as 28 V, making the design of the power
supply easier.
Clamped Driver Stage: Despite the high supply
voltage, the voltage on DRV pin is safely clamped
below 16 V; allowing the use of any standard MOSFET,
and reducing the current consumption of the controller.
Dual Latch−off Input: The NCP1237 can be latched
off by an increasing voltage applied to its Latch pin
(typically an overvoltage) or by a decreasing one, and
an NTC can be directly connected to the latch pin
thanks to the precise internal current source.
Soft−Start: At every startup the peak current is
gradually increased during 4 ms to minimize the stress
on power components.
Temperature Shutdown: The NCP1237 is internally
protected against self−heating: if the die temperature is
too high, the controller shuts all circuitries down
(including the HV startup current source), allowing the
silicon to cool down before attempting to restart. This
ensures a safe behavior in case of failure.
Typical Operation
• Startup: The HV startup current source ensures the
charging of the VCC capacitor up to the startup
threshold VCC(on), until the input voltage is high
enough (above VHV(start)) to enable the switching. The
controller then delivers pulses, starting with a soft−start
period tSSTART during which the peak current linearly
increases before the current−mode control takes over.
During the soft−start period, the low level latch is
ignored, and the latch current is double, to ensure a fast
pre−charge of the decoupling capacitor on the Latch
pin.
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NCP1237
• Normal operation: As long as the feedback voltage is
•
•
within the regulation range, the NCP1237 runs at a
fixed frequency (with jittering) in current−mode
control, where the peak current (sensed on the CS pin)
is set by the voltage on the FB pin. A fixed ramp
compensation is applied internally to prevent
sub−harmonic oscillations from occurring. The VCC
must be supplied by an external source (such as an
auxiliary winding), as the startup current source cannot
permanently supply the controller without overheating.
Light load operation: When the FB voltage decreases
below VFB(fold), typically corresponding to a load of
20% (DCM design only) to 30% (CCM / DCM design)
of the maximum load, the switching frequency starts to
decrease down to fOSC(min). By lowering the switching
losses, this feature helps to improve the efficiency in
light load conditions. The frequency jittering is disabled
in light load operation.
No load operation: When the FB voltage decreases
below Vskip(in), typically corresponding to a load of 1%
of the maximum load, the controller enters Skip mode.
By completely stopping the switching while the
feedback voltage is below Vskip(out), the losses are
further reduced, allowing to minimize the power
dissipation under extremely low load conditions. In
order to avoid audible noise, the peak current is
gradually increased during the tSSKIP duration while
exiting the skip mode (Soft−Skip function). In case of
abrupt load increase during Soft−Skip mode, the
soft−skip portion is bypassed and the peak current
•
•
•
needed for regulation is directly applied. VCC can be
maintained between VCC(on) and VCC(min) by the DSS.
Overload: The NCP1237 features a timer−based
dual−level overload detection, solely dependent on the
feedback information: as soon as the internal peak
current setpoint goes above the VCS(tran) threshold, a
first internal timer starts to count, but the controller is
still able to regulate up to VILIM. Once it reaches the
VILIM clamp, the internal overload timer starts to count.
When either timer times out, the controller stops and
enters the protection mode, autorecovery for the B
version (the controller initiates a new start−up after
tautorec elapses), or latched for the A version (the latch
is released if a brown−out event occurs or VCC is reset).
Brown−out: The NCP1237 features on its HV pin a
true AC line monitoring circuitry which includes a
minimum startup threshold, brown−out protection, and
overvoltage protection. All of these circuits are
autorecovery and operate independently of any ripple
on the input voltage. They can even work with an
unfiltered, rectified AC input. All thresholds are fixed,
but they are designed to fit most of the standard ac−dc
conversion applications.
Latch−off: When the Latch input is pulled up (typically
by an overvoltage condition), or pulled low (typically
by an overtemperature condition, using the provided
current source with an NTC), the controller latches off.
The latch is released when a brown−out condition
occurs, or when VCC decreases below VCC(reset).
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NCP1237
DETAILED DESCRIPTION
High−Voltage Current Source (Dynamic Self−Supply)
with Built−in Brown−out Detection
The NCP1237 HV pin can be connected either to the
rectified bulk voltage, or to the ac line through a rectifier.
Startup
HV
Istart
TSD
Control
IC Start
VCC
+
+
−
VCC(on)
+
R
Q
S
−
+
VCC(min)
+
blanking
−
+
UVLO
tUVLO(blank)
VCC(off )
+
−
+
Reset
VCC(reset)
Figure 4. HV Startup Current Source Functional Schematic
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NCP1237
current source on and off, it can only be used in light load
conditions, otherwise the power dissipation on the die would
be too high. As a result, an auxiliary voltage source is needed
to supply VCC during normal operation.
The DSS is useful to keep the controller alive when no
switching pulses are delivered, e.g. in a brown−out
condition, or to prevent the controller from stopping during
load transients when the VCC might drop below VCC(off).
At startup, the current source turns on when the voltage on
the HV pin is higher than VHV(min), and turns off when VCC
reaches VCC(on). It turns on again when VCC reaches
VCC(min). This sequence repeats until the input voltage is
high enough to ensure a proper startup, i.e. when VHV
reaches VHV(start). The switching actually starts the next
time VCC reaches VCC(on), as shown in Figure 5.
Even though the DSS is able to maintain the VCC voltage
between VCC(on) and VCC(min) by turning the HV startup
VHV
VHV(start)
Waits
next
VCC(on)
before
starting
VHV(min)
time
VCC
VCC(on)
VCC(min)
HV
current
source =
Istart1
HV
current
source =
Istart2
VCC(inhibit)
time
DRV
Figure 5. Startup Timing Diagram
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time
NCP1237
Brown−out and Line Overvoltage
To reduce the power dissipation in case the VCC pin is
shorted to GND (in case of VCC capacitor failure, or external
pulldown on VCC to disable the controller), the startup
current is lowered when VCC is below VCC(inhibit).
There are only two conditions for which the current source
doesn’t turn on when VCC reaches VCC(min): the voltage on
HV pin is too low (below VHV(min)), or a thermal shutdown
condition (TSD) has been detected. In all other conditions,
the HV current source always turns on and off to maintain
VCC between VCC(min) and VCC(on).
When the input voltage goes below VHV(stop), a
brown−out condition is detected, and the controller stops.
The HV current source alternatively turns on and off to
maintain VCC between VCC(on) and VCC(min) until the input
voltage is back above VHV(start).
The same situation occurs when an overvoltage is
detected on the ac line, i.e. when the input voltage goes
above VHV(OV): the controller stops, and resumes normal
operation when the overvoltage condition has gone.
HV stop
Brown-out
or AC OVP
detected
Waits next
VCC(on) before
starting
VCC
time
VCC(on)
VCC(min)
time
DRV
Figure 6. Brown−out or Line Overvoltage Timing Diagram
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time
NCP1237
When VHV crosses the VHV(start) threshold, the controller
can start immediately. When it crosses VHV(stop), it triggers
a timer of duration tHV: this ensures that the controller
doesn’t stop in case of line cycle drop−out.
VHV
Brown-out
VHV(start)
VHV(stop)
DRV
time
Starts at next
VCC(ON)
t HV
Figure 7. AC Input Brown−out Timing Diagram
The same scheme is used for the Line OVP, except that this
time the controller must not stop instantaneously when the
input voltage goes above VHV(OV1). In order to be
time
insensitive to spikes and voltage surges a blanking circuit is
inserted after the output of the comparator, with a duration
of tOV(blank).
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NCP1237
Blanked
voltage
surge
VHV
VHV(OV1)
VHV(OV2)
time
OVP
detected
HV
timer
starts
HV
timer
restarts
One Shot
Restarts at
VCC(on)
t HV
time
DRV
Figure 8. AC Input Line Overvoltage Timing Diagram
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time
NCP1237
Oscillator with Maximum Duty Ratio and Frequency
Jittering
In order to improve the EMI signature, the switching
frequency jitters around its nominal value, with a
triangle−wave shape.
The NCP1237 includes an oscillator that sets the
switching frequency with an accuracy of $7%. The
maximum duty ratio of the DRV pin is 80% (typical), with
an accuracy of $7%.
fOSC
fOSC + Ajitter
Nominal fOSC
fOSC - Ajitter
1 / Fjitter
Time
Figure 9. Frequency Jittering
This driver has a typical current capability of ±1.0 A.
Clamped Driver
The supply voltage for the NCP1237 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot tolerate a gate−to−source voltage greater
than 20 V on their gate. The driver pin is therefore clamped
safely below 16 V.
VCC
Clamp
DRV signal
DRV
Figure 10. Clamped Driver
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NCP1237
CURRENT−MODE CONTROL WITH OVERPOWER COMPENSATION AND SOFT−START
Current Sensing
one input of the PWM comparator through the LEB block.
On the other input the FB voltage divided by KFB sets the
threshold: when VCS reaches this threshold, the output
driver is turned off.
The maximum value for the peak current, VILIM, is set by
a dedicated comparator.
NCP1237 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
resulting voltage is applied to the CS pin. VCS is applied to
VDD
KFB
+
−
RFB(up)
PWM
Jitter
Soft−start
+
−
Oscillator
Soft−start ramp
Start
tSSTART
Reset
FB
DCMAX
IC Start
IC Stop
S
Q
R
blanking
tLEB
CS
+
−
+
VILIM
IC stop
UVLO
blanking
tBCS
+
−
+
Protection
Mode
VCS(stop)
Fault
Figure 11. Current Sense Block Schematic
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HV stop
Latch
TSD
DRV Stage
NCP1237
Each time the controller is starting (i.e. the controller was
off and starts, or restarts, when VCC reaches VCC(on)), a
soft−start is applied: the current sense setpoint is linearly
increased from 0 (the minimum level can be higher than 0
because of the LEB and propagation delay) until it reaches
VILIM (after a duration of tSSTART), or until the FB loop
imposes a setpoint lower than the one imposed by the
soft−start (the 2 comparators outputs are OR’ed).
VFB
VFB(fault)
Time
Soft-start ramp
VFB takes
over soft-start
VILIM
tSSTART
Time
CS Setpoint
VILIMI
Figure 12. Soft−Start
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above VILIM,
because the controller is blind during the LEB blanking
Time
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. In order to protect
against this, an additional comparator is included, that
senses when VCS reaches VCS(stop) ( = 1.5 x VILIM ). As soon
as this comparator toggles, the controller immediately enters
the protection mode (latched or autorecovery according to
the chosen option).
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NCP1237
Compensation for Overpower Detection
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, as shown in Figure 13.
This leads to a significant difference in the maximum output
power delivered by the power supply.
The power delivered by a flyback power supply is
proportional to the square of the peak current:
P OUT +
1
@ h @ L P @ F SW @ IP
2
2
(eq. 1)
(in discontinuous conduction mode).
IP
IP to be
compensated
ILIMIT
High
Line
Low
Line
time
tdelay
tdelay
Figure 13. Line Compensation for True Overpower Protection
Since in light load conditions this offset is in the same
order of magnitude as the current sense signal, it must be
removed. Therefore the compensation current is only added
when the FB voltage is higher than VFB(OPC), as shown in
Figure 15.
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added to the CS signal by turning on an internal current
source (IOPC): by adding an external resistor (ROPC) in
series between the sense resistor and the CS pin, a voltage
offset is created across it by the current. The compensation
can be adjusted by changing the value of the ROPC resistor.
VDD
V to I
HV Sensing
HV
IOPC = 0.5m x
(VHV − 125)
+
FB
−
+
VFB(OPC)
CS
blanking
To CS
block
t LEB
ROPC
Rsense
Figure 14. Schematic Overpower Compensation Circuit
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NCP1237
IOPC
VHV
VFB
VFB(fold)
VFB(OPC)
Figure 15. Overpower Compensation Current Relation to Feedback Voltage and Input Voltage
Feedback with Slope Compensation
to VILIM is 3.5 V. There is a pullup resistor of 20 kW
(typical) from FB pin to the internal reference VFB(ref).
The ratio from the FB voltage to the current sense setpoint
is typically 5. This means that the FB voltage corresponding
VDD
20 kW
FB
K FB
slope
comp.
+
PWM
−
CS
Oscillator
blanking
t LEB
Figure 16. FB Circuitry
In order to allow the NCP1237 to operate in CCM with a
duty cycle above 50%, a fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical for the 65 kHz version
(and respectively −50 mV/ms and −67 mV/ms for the
100 kHz and 133 kHz versions).
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NCP1237
OVERCURRENT PROTECTION WITH FAULT TIMER
Classical Overcurrent Protection
controller is either latched off (latched protection,
Version A), or it enters an autorecovery mode (Version B).
The timer is reset when the CS setpoint goes back below
VILIM before the timer elapses. The fault timer is also started
if the driver signal is reset by the max duty ratio.
When an overcurrent occurs on the output of the power
supply, the feedback loop asks for more power than the
controller can deliver, and the CS setpoint reaches VILIM.
When this event occurs, an internal tfault timer is started:
once the timer times out, DRV pulses are stopped and the
FB
+
−
/5
Fault Flag
PWM
R
Q
S
timer
tfault
Protection
Mode
Autorecovery
protection
mode only
blanking
CS
Reset DRV
release
timer
tLEB
+
+
−
Brown−out
Reset
VILIM
DC MAX
DRV
Figure 17. Timer−Based Overcurrent Protection
In autorecovery mode, the controller tries to restart after
tautorec. If the fault has gone, the supply resumes operation;
if not, the system starts a new burst cycle (see Figure 18).
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t autorec
NCP1237
Fault
disappears
Output Load Overcurrent
applied
Max Load
Fault Flag
time
Fault
timer
starts
VCC
time
VCC(on)
VCC(min)
Restart
At VCC(on)
(new burst
cycle if Fault
DRV
time
still present)
Controller
stops
Fault timer
time
tfault
tfault
tautorec
Figure 18. Autorecovery Timer−Based Protection Mode
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time
NCP1237
In the latched version (Figure 19), the controller can
restart only if a brown−out or a VCC reset occurs. In a real
application this can only happen if the power supply is
unplugged from the mains line.
Output Load
No restart
when fault
disappears
Overcurrent
applied
Max Load
Fault Flag
time
Fault
timer
starts
VCC
time
VCC(on)
VCC(min)
DRV
time
Controller
latches off
Fault timer
time
tfault
tfault
Figure 19. Latched Timer−Based Overcurrent Protection
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time
NCP1237
Dual−Level Overcurrent Protection
This is implemented by adding another comparator whose
threshold is VCS(tran), a CS voltage level lower than VILIM,
which starts the charging of another timer, with a duration
ttran longer than tfault (168 ms typical). If the timer reaches
its maximum duration, the controller enters protection mode
(latched or autorecovery depending on the option).
For some applications (e.g. printer adapters), it is
necessary that the controller maintains regulation while it
has detected a first level of overload. This is to authorize a
transient peak power higher than the maximum continuous
output power.
Fault Flag
FB
PWM
+
−
KFB
tfault
R
Q
S
timer
ttran
Protection
Mode
Reset DRV
release
Autorecovery
protection
mode only
timer
CS
blanking
tLEB
+
+
−
Brown−out
tautorec
Reset
VCS(tran)
Figure 20. Dual−Level Timer−Based Overcurrent Protection
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NCP1237
The typical level at which this transient peak timer starts
is VCS(tran) = 0.5 V, which gives half the maximum output
power in DCM.
The duration of the transient peak timer is ttran (168 ms
typical). Figures 21 and 22 show the operation of the
transient peak timer in two different peak power conditions.
Transient
peak power
Output Load
Max transient Load
Max continuous Load
time
Transient
peak timer
starts
Transient peak
timer discharges
DRV
time
Timer duration
ttran
tfault
time
Figure 21. Transient Peak Power Delivery
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NCP1237
Output Load
Max transient Load
Transient
peak power
Max continuous Load
time
Transient
peak timer
starts
DRV
Controller enters
Protection mode
time
Timer duration
ttran
tfault
Figure 22. Too Long Transient Peak Power Delivery
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time
NCP1237
LOW LOAD OPERATION
Frequency Foldback
whatever the nominal switching frequency option is. The
current−mode control is still active while the oscillator
frequency decreases, but the frequency jittering is off.
Note that the frequency foldback is disabled if the
controller runs at its maximum duty cycle.
In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to fOSC(min). This frequency
foldback starts when the voltage on FB pin VFB goes below
VFB(fold), and is complete before VFB reaches Vskip(in),
fOSC
Nominal fOSC
Skip
fOSC(min)
FB
Vskip(in)
VFB(fold)
Figure 23. Frequency Foldback when the FB Voltage Decreases
Skip Cycle Mode with Soft−Skip
+
−
+
Soft−skip ramp
Reset
tSSKIP
Sawtooth
Oscillator
DCMAX
Vskip
FB
CS
S
Q
R
K FB
blanking
tLEB
DRV stage
−
+
+
−
Figure 24. Skip Cycle with Soft−Skip Schematic
When VFB reaches Vskip(in) while decreasing, the skip
mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While VFB is
below Vskip(out), the controller remains in this state. When
VFB crosses Vskip(out), the DRV pin starts to pulse again, and
the controller restarts with a short Soft−Skip duration
(tSSKIP). The soft−skip imposes the peak current from nearly
0, in a voltage−mode manner: it doesn’t have the same
behavior as the startup soft−start which is current−mode
driven.
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NCP1237
VFB
VFB(fold)
Vskip(out)
Vskip(in)
Exits
skip
Time
Enters
skip
Enters
skip
DRV
Exits
soft-skip
Exits
skip
Time
CS setpoint
Soft-skip
Softskip
Figure 25. Skip Cycle with Soft−Skip Timing Diagram
If during the Soft−Skip duration the FB voltage goes
above VFB(fold), the Soft−Skip ends instantaneously, and the
peak current follows the setpoint imposed by the
Time
current−mode control. This transient load detection feature
avoids large output voltage drops if a load transient occurs
while the controller is in soft−skip mode.
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NCP1237
Latch−off Input
VDD
+
−
+
INTC
blanking
tLatch(OVP)
VOVP
INTC
Latch
+
1 kW
−
+
blanking
tLatch(OTP)
S
Q
R
Latch
VOTP
Vclamp
Brown−out
Reset
Soft−start
end
Figure 26. Latch Detection Schematic
The Latch pin is dedicated to the latch−off function. It
includes two thresholds that define a working window,
between a high latch and a low latch. Within these 2
thresholds; the controller is allowed to run; but as soon as
either the low or the high threshold is crossed, the controller
is latched off. The lower threshold is intended to be used
with an NTC thermistor, with the internal current source
INTC providing the necessary bias current.
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the ILatch current. To
reach the high threshold, the pullup current has to be higher
than the pulldown capability of the clamp (typically 1.5 mA
at VOVP).
To avoid any false triggering, noise spikes shorter than
tLatch(OVP) or tLatch(OTP) respectively are blanked, and only
longer events can actually latch the controller.
Reset occurs when a brown−out condition is detected or
the VCC is cycled down to a VCC(reset), which in a real
application can only happen if the power supply is
unplugged from the AC line.
Upon startup, the internal references take some time
before reaching their nominal values; and one of the
comparators could toggle inadvertantly. Therefore the
internal logic ignores the latch signal before the controller is
ready to start. Once VCC reaches VCC(on), the latch pin High
latch state is enabled and the DRV switching starts only if it
is allowed; whereas the Low latch (typically sensing an
overtemperature) is taken into account only after the
soft−start is finished. In addition, the NTC current is doubled
during the soft−start period, to speed up the charging of the
Latch pin capacitor.
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NCP1237
VCC
VCC(on)
VCC(min)
Start-up
initiated by
VCC(on)
Internal Latch Signal
Noise spike
ignored
(tLatch blanking)
Latch signal
high during
pre-start phase
time
time
DRV
Latch-off
Switching
allowed (no
latch event)
Figure 27. Latch−off Function Timing Diagram
Temperature shutdown
time
instantaneously, the HV current source is turned off, and the
internal logic state is reset.
When the temperature falls below the low threshold, the
HV startup current source is enabled, and a regular startup
sequence takes place.
The die includes a temperature shutdown protection with
a turn−off threshold guaranteed between 140°C and 160°C,
and a typical hysteresis of 30°C. When the temperature rises
above the high threshold, the controller stops switching
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NCP1237
STATE DIAGRAMS
HV Startup Current Source
VCC > VCC(inhibit)
Istart1
No TSD
Istart2
VCC < VCC(inhibit)
TSD
TSD
Stop
TSD
VCC < VCC(min)
VCC > VCC(on)
TSD
Off
Figure 28. HV Startup Current Source State Diagram
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NCP1237
Controller Operation (Latched Version: A Option)
High Latch
VCC > VCC(on)
Soft−start
Soft-start ends
S Brown-out
S HV OVP
S TSD
S Brown-out
S HV OVP
S TSD
Stopped
S Brown-out
S HV OVP
S TSD
S Brown-out
S VCC reset
S Brown-out
S HV OVP
S TSD
Skip
S High Latch
S Low Latch
S Brown-out
S HV OVP
S TSD
Skip in
Latch
Skip out
Running
Soft−skip
S High Latch
S Low Latch
S Soft-skip ends
S VFB > V FB(fold)
S Fault
S High Latch
S Low Latch
With Fault =
S tfault or ttran expires
S VCS > VCS(stop)
S VCC < VCC(off)
Figure 29. Controller Operation State Diagram (Latched Overload Protection)
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NCP1237
Controller Operation (Autorecovery Version: B Option)
High Latch
VCC > VCC(on)
Soft−start
Soft-start ends
S Brown-out
S HV OVP
S TSD
S t autorec counting
S Brown-out
S HV OVP
S TSD
Stopped
S Brown-out
S HV OVP
S TSD
S Brown-out
S VCC reset
S Fault
S Brown-out
S HV OVP
S TSD
Skip
S High Latch
S Low Latch
S Brown-out
S HV OVP
S TSD
Latch
Skip in
Skip out
Running
Soft−skip
S High Latch
S Low Latch
S Soft-skip ends
S V FB > VFB(fold)
S High Latch
S Low Latch
With Fault =
S tfault or ttran expires
S VCS > VCS(stop)
S VCC < VCC(off)
Figure 30. Controller Operation State Diagram (Autorecovery Overload Protection)
Table 1. ORDERING INFORMATION
Overload Protection
Switching Frequency
Package
Shipping†
NCP1237AD65R2G
Latched
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1237BD65R2G
Autorecovery
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
Part No.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1237
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE D
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
S
The product described herein (NCP1237) may be covered by one or more of the following U.S. patents: 5,073,850, 6,271,735, 6,362,067, 6,385,060,
6,597,221, 6,633,193, 6,587,351, 6,940,320, 7,638,405. There may be other patents pending.
Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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33
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP1237/D