ON NCP1244BD065R2G Fixed frequency current mode controller Datasheet

NCP1244
Fixed Frequency Current
Mode Controller for Flyback
Converters
The NCP1244 is a new fixed−frequency current−mode controller
featuring the Dynamic Self−Supply. This function greatly simplifies
the design of the auxiliary supply and the VCC capacitor by activating
the internal startup current source to supply the controller during
start−up, transients, latch, stand−by etc. This device contains a special
HV detector which detect the application unplug from the AC input
line and triggers the X2 discharge current.
It features a timer−based fault detection that ensures the detection of
overload and an adjustable compensation to help keep the maximum
power independent of the input voltage.
Due to frequency foldback, the controller exhibits excellent
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp
compensation, and a versatile latch input make this controller an
excellent candidate for the robust power supply designs.
A dedicated Off mode allows to reach the extremely low no load
input power consumption via “sleeping” whole device and thus
minimize the power consumption of the control circuitry.
• Fixed−Frequency Current−Mode Operation (65 kHz and 100 kHz
•
•
•
•
•
•
•
MARKING
DIAGRAM
8
SOIC−7
CASE 751U
44Xfff
ALYWX
G
1
44Xfff = Specific Device Code
X = A or B
fff = 065 or 100
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
Features
•
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Latch 1
8
HV
frequency options)
FB 2
Frequency Foldback then Skip Mode for Maximized Performance in
6 VCC
CS 3
Light Load and Standby Conditions
GND 4
5 DRV
Timer−Based Overload Protection with Latched (Option A) or
(Top View)
Auto−Recovery (Option B) Operation
High−voltage Current Source with Dynamic Self−Supply,
Simplifying the Design of the VCC Circuitry
ORDERING INFORMATION
See
detailed
ordering and shipping information in the package
Frequency Modulation for Softened EMI Signature
dimensions section on page 39 of this data sheet.
Adjustable Overpower Protection Dependant on the Bulk Voltage
Latch−off Input Combined with the Overpower Protection Sensing
Input
VCC Operation up to 28 V, With Overvoltage Detection
Typical Applications
500/800 mA Source/Sink Drive Peak Current
• AC−DC Adapters for Notebooks, LCD, and Printers
Capability
• Offline Battery Chargers
10 ms Soft−Start
• Consumer Electronic Power Supplies
Internal Thermal Shutdown
• Auxiliary/Housekeeping Power Supplies
No−Load Standby Power < 30 mW
• Offline Adapters for Notebooks
X2 Capacitor in EMI Filter Discharging Feature
•
•
•
•
• These Devices are Pb−Free and Halogen Free/BFR Free
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 1
1
Publication Order Number:
NCP1244/D
NCP1244
TYPICAL APPLICATION EXAMPLE
Figure 1. Flyback Converter Application Using the NCP1244
PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
LATCH
Latch−Off Input
Pull the pin up or down to latch−off the controller. An internal current source
allows the direct connection of an NTC for over temperature detection.
2
FB
Feedback + Shutdown pin
An optocoupler collector to ground controls the output regulation. The part
goes to the low consumption Off mode if the FB input pin is pulled to GND.
3
CS
Current Sense
4
GND
−
5
DRV
Drive output
6
VCC
VCC input
8
HV
High−voltage pin
This Input senses the Primary Current for current−mode operation, and
offers an overpower compensation adjustment.
The controller ground
Drives external MOSFET
This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is
connected to an external auxiliary voltage. It is not allowed to connect
another circuit to this pin to keep low input power consumption.
Connects to the rectified AC line to perform the functions of Start−up
Current Source, Self−Supply and X2 capacitor discharge function and the
HV sensing for the overpower protection purposes. It is not allowed to
connect this pin to DC voltage.
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2
NCP1244
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
Intc
Intc
Vdd
Vhv sample
HV
OVP_CMP
SG & X2 & Vcc
ON_CMP
10.8V
X2 discharge
10.8V regulator
Vdd reg
PowerOnReset_CMP
RESET
Vdd
12V
VccON
VccON
Vcc(reg)
Vcc regulator
5V
Q
Reset Qb
VCC
Vcc_Int
ICstartB
9.5V
Set
RESET
Latch
Dual HV
start−up
current source
control
VccRESET
26V
0.8V
+Shv
TSD
UVLO_CMP
UVLO
SS_end
1.2V
Votp
1k
300 us OTP
Filter
VccOVP
OTP_CMP
15 mA
VccOVP_CMP
VccOVP 10 us
Filter
VccOFF
Vovp
2.5V
LATCH
VclampRclamp
AC_Off
OVP
55 us
Filter
STOP_CMP
VccMIN
10.5V
Off_mode_CMP1
2.2V
Set
Von
VccMIN
5uA
VCC
Q
ICstart
Reset Qb
Off_mode_CMP2
FM input
jittering
0.4V
Voff
GoToOffMode timer 150ms
Square output
OSC 65kHz
Internal resitance 20k
ton_max output
3.0V
PFM input
CSref
4uMho
FBbuffer
MAX_ton
Q
IC stopB
PWM
Reset Qb
1uA
Ilimit_CMP
Ilimit
Set
0.7V
Vilim
Vfb < 1.5V fix current setpoint 300mV
Q
Reset Qb
Fault timer
Fault
Autorecovery timer
CSstop_CMP
+Shv
1.05V
VCSstop
LEB 120ns
TSD
Figure 2. Simplified Internal Block Schematic
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3
TSD
Latch management
Enable
Soft Start timerSS_end
LatchB
FaultB
SoftStart_CMP
LEB 250ns
Iopc = 0.5u*(Vhv−125)
GND
DRV
Set
PWM_CMP
Vdd
CS
VCC
Clamp
0.7V
Vskip
Division ratio 5
Rfb3 Rfb2
2.35V
Vfb(opc)
Vhv sample
Skip_CMP
SkipB
V to I
Saw output
Ramp_OTA
1.4V
FB
freq folback
Vramp_offset
Rfb1
Vfb(reg)
RESET
IC stop
Latch
NCP1244
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
–0.3 to 20
±1000 (peak)
V
mA
VCCPower Supply voltage, VCC pin, continuous voltage
Power Supply voltage, VCC pin, continuous voltage (Note 1)
–0.3 to 28
±30 (peak)
V
mA
Maximum voltage on HV pin
(Dc−Current self−limited if operated within the allowed range)
–0.3 to 500
±20
V
mA
Vmax
Maximum voltage on low power pins (except pin 5, pin 6 and pin 8)
(Dc−Current self−limited if operated within the allowed range) (Note 1)
–0.3 to 10
±10 (peak)
V
mA
RqJ−A
Thermal Resistance SOIC−7
Junction-to-Air, low conductivity PCB (Note 2)
Junction-to-Air, medium conductivity PCB (Note 3)
Junction-to-Air, high conductivity PCB (Note 4)
162
147
115
RqJ−C
Thermal Resistance Junction−to−Case
73
°C/W
TJMAX
Operating Junction Temperature
−40 to +150
°C
Storage Temperature Range
−60 to +150
°C
> 2000
V
ESD Capability, Machine Model per JEDEC Standard JESD22, Method A115A
> 200
V
ESD Capability, Charged Device Model per JEDEC Standard JESD22, Method C101E
> 1000
V
DRV
(pin 5)
Maximum voltage on DRV pin
(Dc−Current self−limited if operated within the allowed range) (Note 1)
VCC
(pin 6)
HV
(pin 8)
TSTRGMAX
°C/W
ESD Capability, HBM model (All pins except HV) per JEDEC Standard JESD22,
Method A114E
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
2. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
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NCP1244
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VHV(min)
−
30
40
V
VCC = 0 V
VCC = VCC(on) − 0.5 V
Istart1
Istart2
0.2
5
0.5
8
0.8
11
mA
Off−state leakage current
VHV = 500 V, VCC = 15 V
Istart(off)
10
25
50
mA
Off−mode HV supply current
VHV = 141 V,
VHV = 325 V,
VCC loaded by 4.7 mF cap
IHV(off)
−
−
45
50
60
70
mA
HV current source regulation threshold
VCC(reg)
8
11
−
V
Turn−on threshold level, VCC going up
HV current source stop threshold
VCC(on)
11.0
12.0
13.0
V
HV current source restart threshold
VCC(min)
9.5
10.5
11.5
V
Turn−off threshold
VCC(off)
8.5
8.9
9.3
V
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source
operation
Current flowing out of VCC pin
SUPPLY
Overvoltage threshold
VCC(ovp)
25
26.5
28
V
Blanking duration on VCC(off) and VCC(ovp)
detection
tVCC(blank)
−
10
−
ms
VCC decreasing level at which the internal
logic resets
VCC(reset)
4.8
7.0
7.7
V
VCC level for ISTART1 to ISTART2 transition
VCC(inhibit)
0.2
0.8
1.25
V
DRV open, VFB = 3 V, 65 kHz
DRV open, VFB = 3 V, 100 kHz
ICC1
ICC1
1.3
1.3
1.85
1.85
2.2
2.2
mA
Cdrv = 1 nF, VFB = 3 V, 65 kHz
Cdrv = 1 nF, VFB = 3 V, 100 kHz
ICC2
ICC2
1.8
2.3
2.6
2.9
3.0
3.5
ICC3
0.67
0.9
1.13
ICC4
0.3
0.6
0.9
VHV(hyst)
1.5
3.5
5
V
Tsample
−
1.0
−
ms
Timer duration for no line detection
tDET
21
32
43
ms
Discharge timer duration
tDIS
21
32
43
ms
fOSC
58
87
65
100
72
109
kHz
Internal current consumption (Note 5)
Off mode (skip or before start−up)
Fault mode (fault or latch)
X2 DISCHARGE
Comparator hysteresis observed at HV pin
HV signal sampling period
OSCILLATOR
Oscillator frequency
Maximum on time for TJ = 25°C to +125°C
only
fOSC = 65 kHz
fOSC = 100 kHz
tONmax(65kHz)
tONmax(100kHz)
11.5
7.5
12.3
8.0
13.1
8.5
ms
Maximum on time
fOSC = 65 kHz
fOSC = 100 kHz
tONmax(65kHz)
tONmax(100kHz)
11.3
7.4
12.3
8.0
13.1
8.5
ms
Maximum duty cycle (corresponding to
maximum on time at maximum switching
frequency)
fOSC = 65 kHz
fOSC = 100 kHz
DMAX
−
80
−
%
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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NCP1244
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
Frequency jittering amplitude, in percentage
of FOSC
Ajitter
±4
±6
±8
%
Frequency jittering modulation frequency
Fjitter
85
125
165
Hz
Feedback voltage threshold below which
frequency foldback starts
VFB(foldS)
1.8
2.0
2.2
V
Feedback voltage threshold below which
frequency foldback is complete
VFB(foldE)
0.8
0.9
1.0
V
VFB = Vskip(in) + 0.1
fOSC(min)
23
27
32
kHz
Rise time, 10 to 90% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
trise
−
40
70
ns
Fall time, 90 to 10% of VCC
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
tfall
−
40
70
ns
Current capability
VCC = VCC(min) + 0.2 V,
CDRV = 1 nF
DRV high, VDRV = 0 V
DRV low, VDRV = VCC
OSCILLATOR
FREQUENCY FOLDBACK
Minimum switching frequency
OUTPUT DRIVER
mA
IDRV(source)
IDRV(sink)
−
−
500
800
−
−
VCC = VCCmax – 0.2 V, DRV high,
RDRV = 33 kW, Cload = 220 pF
VDRV(clamp)
11
13.5
16
V
VCC = VCC(min) + 0.2 V,
RDRV = 33 kW, DRV high
VDRV(drop)
−
−
1
V
Input Pull−up Current
VCS = 0.7 V
Ibias
−
1
−
mA
Maximum internal current setpoint
VFB > 3.5 V
VILIM
0.66
0.70
0.74
V
Propagation delay from VIlimit detection to
DRV off
VCS = VILIM
tdelay
−
80
110
ns
tLEB
200
250
320
ns
VCS(stop)
0.95
1.05
1.15
V
tBCS
90
120
150
ns
tSSTART
8
11
14
ms
VI(freeze)
275
300
325
mV
Scomp(65kHz)
Scomp(100kHz)
−
−
−32.5
−50
−
−
mV /
ms
RFB(up)
15
20
25
kW
KFB
4.7
5
5.3
−
VFB(ref)
4.5
5
5.5
V
VFB(freeze)
1.35
1.5
1.65
V
Clamping voltage (maximum gate voltage)
High−state voltage drop
CURRENT SENSE
Leading Edge Blanking Duration for VILIM
Threshold for immediate fault protection
activation
Leading Edge Blanking Duration for VCS(stop)
(Note 6)
Soft−start duration
From 1st pulse to VCS = VILIM
Frozen current setpoint
INTERNAL SLOPE COMPENSATION
Slope of the compensation ramp
FEEDBACK
Internal pull−up resistor
TJ = 25°C
VFB to internal current setpoint division ratio
Internal pull−up voltage on the FB pin
(Note 6)
Feedback voltage below which the peak
current is frozen
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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NCP1244
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VHV = 125 V,
VCC = 11 V unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VFB going down
VFB going up
Vskip(in)
Vskip(out)
0.63
0.72
0.70
0.80
0.77
0.88
V
The voltage above which the part enters the
on mode
VCC > VCC(off), VHV = 60 V
VON
−
2.2
−
V
The voltage below which the part enters the
off mode
VCC > VCC(off)
VOFF
0.35
0.40
0.45
V
VCC > VCC(off), VHV = 60 V
VHYST
500
−
−
mV
SKIP CYCLE MODE
Feedback voltage thresholds for skip mode
REMOTE CONTROL ON FB PIN
Minimum hysteresis between the VON and
VOFF
Pull−up current in off mode
VCC > VCC(off)
IOFF
−
5
−
mA
Go To Off mode timer
VCC > VCC(off)
tGTOM
500
600
700
ms
tfault
108
128
178
ms
tautorec
0.85
1.00
1.35
s
OVERLOAD PROTECTION
Fault timer duration
Autorecovery mode latch−off time duration
OVERPOWER PROTECTION
KOPC
−
0.54
−
mA / V
Current flowing out of CS pin (Note 7)
VHV = 125 V
VHV = 162 V
VHV = 325 V
VHV = 365 V
IOPC(125)
IOPC(162)
IOPC(325)
IOPC(365)
−
−
−
105
0
20
110
130
−
−
−
150
mA
FB voltage above which IOPC is applied
VHV = 365 V
VFB(OPCF)
2.12
2.35
2.58
V
FB voltage below which is no IOPC applied
VHV = 365 V
VFB(OPCE)
−
2.15
−
V
High threshold
VLatch going up
VOVP
2.35
2.5
2.65
V
Low threshold
VLatch going down
VOTP
0.76
0.8
0.84
V
INTC
65
130
95
190
105
210
tLatch(OVP)
35
20
50
35
70
50
ms
tLatch(OTP)
−
350
−
ms
ILatch = 0 mA
ILatch = 1 mA
Vclamp0(Latch)
Vclamp1(Latch)
1.0
1.8
1.2
2.4
1.4
3.0
V
TJ going up
TTSD
−
150
−
°C
TJ going down
TTSD(HYS)
−
30
−
°C
VHV to IOPC conversion ratio
LATCH−OFF INPUT
Current source for direct NTC connection
During normal operation
During soft−start
VLatch = 0 V
Blanking duration on high latch detection
65 kHz version
100 kHz version
INTC(SSTART)
Blanking duration on low latch detection
Clamping voltage
mA
TEMPERATURE SHUTDOWN
Temperature shutdown
Temperature shutdown hysteresis
5. Internal supply current only, currents sourced via FB pin is not included (current is flowing in GND pin only).
6. Guaranteed by design.
7. CS pin source current is a sum of Ibias and IOPC, thus at VHV = 125 V is observed the Ibias only, because IOPC is switched off.
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NCP1244
TYPICAL CHARACTERISTIC
32
40
38
30
36
Istart(off) (mA)
VHV(min) (V)
34
32
30
28
26
24
28
26
24
22
22
20
−50
−25
0
25
50
75
100
20
−50
125
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 3. Minimum Current Source Operation
VHV(min)
Figure 4. Off−State Leakage Current Istart(off)
50
8.8
45
8.7
IHV(off) @ VHV = 325 V
8.6
35
Istart2 (mA)
40
IHV(off) (mA)
−25
TEMPERATURE (°C)
IHV(off) @ VHV = 141 V
8.5
8.4
30
8.3
25
8.2
−25
0
25
50
75
100
8.1
−50
125
0
25
50
75
100
TEMPERATURE (°C)
Figure 5. Off−Mode HV Supply Current IHV(off)
Figure 6. High Voltage Startup Current
Flowing Out of VCC Pin Istart2
0.75
310
0.74
308
0.73
306
0.72
304
0.71
0.70
0.69
300
298
296
0.67
294
0.66
292
−25
0
25
50
75
100
290
−50
125
125
302
0.68
0.65
−50
−25
TEMPERATURE (°C)
VI(freeze) (mV)
VILIM (V)
20
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Maximum Internal Current Setpoint
VILIM
Figure 8. Frozen Current Setpoint VI(freeze) for
the Light Load Operation
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NCP1244
TYPICAL CHARACTERISTIC
110
1.15
1.13
100
1.11
90
1.07
tdelay (ns)
VCS(stop) (V)
1.09
1.05
1.03
1.01
80
70
60
0.99
50
0.97
0.95
−50
−25
0
25
50
75
100
40
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Threshold for Immediate Fault
Protection Activation VCS(stop)
Figure 10. Propagation Delay tdelay
125
130
300
290
125
280
IOPC(365) (mA)
tLEB (ns)
270
260
250
240
230
220
120
115
110
105
210
−25
0
25
50
75
100
100
−50
125
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Maximum Overpower
Compensating Current IOPC(365) Flowing Out
of CS Pin
24
5.20
23
5.15
22
5.10
125
5.05
21
20
19
18
5.00
4.95
4.90
4.85
17
4.80
16
4.75
15
−50
−25
Figure 11. Leading Edge Blanking Duaration
tLEB
VFB(ref) (V)
RFB(up) (kW)
200
−50
−25
0
25
50
75
100
4.70
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. FB Pin Internal Pull−up Resistor
RFB(up)
Figure 14. FB Pin Open Voltage VFB(ref)
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125
NCP1244
TYPICAL CHARACTERISTIC
0.85
2.65
0.84
2.60
0.83
0.82
VOTP (V)
VOVP (V)
2.55
2.50
2.45
0.81
0.80
0.79
0.78
0.77
2.40
0.76
0
25
50
75
100
0.75
−50
125
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Latch Pin Low Threshold VOTP
105
210
100
200
INTC(SSTART) (mA)
220
95
90
85
180
170
160
75
150
−25
0
25
50
75
100
140
−50
125
125
190
80
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Current INTC Sourced from the
Latch Pin, Allowing Direct NTC Connection
Figure 18. Current INTC(SSTART) Sourced from
the Latch Pin, During Soft−Start
70
100
69
99
68
98
67
97
66
65
64
96
95
94
63
93
62
92
61
91
60
−50
−25
Figure 15. Latch Pin High Threshold VOVP
110
70
−50
fOSC (kHz)
−25
fOSC (kHz)
INTC (mA)
2.35
−50
−25
0
25
50
75
100
125
90
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Oscillator fOSC for the 65 kHz
Version
Figure 20. Oscillator fOSC for the 100 kHz
Version
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NCP1244
TYPICAL CHARACTERISTIC
12.8
8.4
12.7
8.3
12.6
8.2
tONmax (ms)
tONmax (ms)
12.5
12.4
12.3
12.2
8.1
8.0
12.1
7.9
12.0
11.9
−50
−25
0
25
50
75
100
7.8
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Maximum ON Time tONmax for the
65 kHz Version
Figure 22. Maximum ON Time tONmax for the
100 kHz Version
85
30
84
29
83
28
fOSC(min) (ms)
DMAX (%)
82
81
80
79
27
26
25
78
24
77
23
76
75
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
22
−50
125
Figure 23. Maximum Duty Ratio DMAX
1.00
2.15
0.98
25
50
75
TEMPERATURE (°C)
100
125
0.96
2.10
0.94
VFB(foldE) (V)
VFB(foldS) (V)
0
Figure 24. Minimum Switching Frequency
fOSC(min)
2.20
2.05
2.00
1.95
0.92
0.90
0.88
0.86
1.90
0.84
1.85
1.80
−50
−25
0.82
−25
0
25
50
75
100
125
0.80
−50
TEMPERATURE (°C)
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 25. FB Pin Voltage Below Which
Frequency Foldback Starts VFB(foldS)
Figure 26. FB Pin Voltage Below Which
Frequency Foldback Complete VFB(foldE)
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NCP1244
TYPICAL CHARACTERISTIC
0.77
0.88
0.75
0.86
0.84
Vskip(on) (V)
Vskip(in) (V)
0.73
0.71
0.69
0.67
0.82
0.80
0.78
0.76
0.65
0.74
0.63
−50
−25
0
25
50
75
100
0.72
−50
125
−25
TEMPERATURE (°C)
2.35
2.50
2.30
2.45
2.25
VFB(OPCE) (V)
VFB(OPCF) (V)
2.40
2.55
2.40
2.35
2.30
2.00
2.15
1.95
75
100
1.90
−50
125
−25
0
TEMPERATURE (°C)
11.3
12.6
11.1
12.4
10.9
VCC(min) (V)
VCC(on) (V)
11.5
12.8
12.2
12.0
11.8
125
10.3
10.1
9.9
11.2
9.7
50
100
10.5
11.4
25
75
10.7
11.6
0
50
Figure 30. FB Pin Level VFB(OPCE) Below
Which is No Overpower Compensation
Applied
13.0
−25
25
TEMPERATURE (°C)
Figure 29. FB Pin Level VFB(OPCF) Above
Which is the Overpower Compensation
Applied
11.0
−50
125
2.10
2.20
50
100
2.15
2.05
25
75
2.20
2.25
0
50
Figure 28. FB Pin Skip−Out Level Vskip(out)
2.60
−25
25
TEMPERATURE (°C)
Figure 27. FB Pin Skip−In Level Vskip(in)
2.10
−50
0
75
100
125
9.5
−50
TEMPERATURE (°C)
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 31. VCC Turn−on Threshold Level, VCC
Going Up HV Current Source Stop Threshold
VCC(on)
Figure 32. HV Current Source Restart
Threshold VCC(min)
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NCP1244
TYPICAL CHARACTERISTIC
9.4
7.3
7.2
9.2
7.1
VCC(reset) (V)
VCC(off) (V)
9.0
8.8
8.6
7.0
6.9
6.8
6.7
8.4
6.6
8.2
6.5
8.0
−50
−25
0
25
50
75
100
6.4
−50
125
−25
TEMPERATURE (°C)
25
50
75
100
125
TEMPERATURE (°C)
Figure 33. VCC Turn−off Threshold (UVLO)
VCC(off)
Figure 34. VCC Decreasing Level at Which the
Internal Logic Resets VCC(reset)
2.0
3.2
ICC1(100kHz)
1.9
ICC2(100kHz)
3.0
1.9
2.8
ICC2 (mA)
ICC1 (mA)
0
ICC1(65kHz)
1.8
1.8
2.4
1.7
2.2
1.7
−50
−25
0
25
50
TEMPERATURE (°C)
75
100
ICC2(65kHz)
2.6
2.0
−50
125
Figure 35. Internal Current Consumption when
DRV Pin is Unloaded
−25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 36. Internal Current Consumption when
DRV Pin is Loaded by 1 nF
4.0
1.10
3.9
1.08
1.06
3.8
Tsample (ms)
VHV(hyst) (V)
1.04
3.7
3.6
3.5
1.02
1.00
0.98
0.96
3.4
0.94
3.3
3.2
−50
0.92
−25
0
25
50
75
100
0.90
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 37. X2 Discharge Comparator
Hysteresis Observed at HV Pin VHV(hyst)
Figure 38. HV Signal Sampling Period Tsample
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NCP1244
TYPICAL CHARACTERISTIC
2.6
0.45
2.6
0.44
0.43
2.5
0.42
VOFF (V)
VON (V)
2.5
2.4
2.4
0.41
0.40
0.39
0.38
2.3
0.37
2.3
0.36
2.2
−50
−25
0
25
50
75
100
0.35
−50
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 39. FB Pin Voltage Level Above Which
is Entered On Mode VON
Figure 40. FB Pin Voltage Level Below Which
is Entered Off Mode VOFF
300
150
280
145
260
240
tGTOM (ms)
tfault (ms)
140
135
130
220
200
180
160
140
125
120
120
−50
−25
0
25
50
75
100
125
100
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. Fault Timer Duration tfault
Figure 42. Go To Off Mode Timer Duration
tGTOM
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NCP1244
APPLICATION INFORMATION
Functional Description
For loads that are between approximately 32% and 10%
of full rated power, the converter operates in frequency
foldback mode (FFM). If the feedback pin voltage is lower
than 1.5 V the peak switch current is kept constant and the
output voltage is regulated by modulating the switching
frequency for a given and fixed input voltage VHV.
Effectively, operation in FFM results in the application of
constant volt−seconds to the flyback transformer each
switching cycle. Voltage regulation in FFM is achieved by
varying the switching frequency in the range from 65 kHz
(or 100 kHz) to 27 kHz. For extremely light loads (below
approximately 6% full rated power), the converter is
controlled using bursts of 27 kHz pulses. This mode is called
as skip mode. The FFM, keeping constant peak current and
skip mode allows design of the power supplies with
increased efficiency under the light loading conditions.
Keep in mind that the aforementioned boundaries of
steady−state operation are approximate because they are
subject to converter design parameters.
The NCP1244 includes all necessary features to build a
safe and efficient power supply based on a fixed−frequency
flyback converter. The NCP1244 is a multimode controller
as illustrated in Figure 43. The mode of operation depends
upon line and load condition. Under all modes of operation,
the NCP1244 terminates the DRV signal based on the switch
current. Thus, the NCP1244 always operates in current
mode control so that the power MOSFET current is always
limited.
Under normal operating conditions, the FB pin commands
the operating mode of the NCP1244 at the voltage
thresholds shown in Figure 43. At normal rated operating
loads (from 100% to approximately 33% full rated power)
the NCP1244 controls the converter in fixed frequency
PWM mode. It can operate in the continuous conduction
mode (CCM) or discontinuous conduction mode (DCM)
depending upon the input voltage and loading conditions. If
the controller is used in CCM with a wide input voltage
range, the duty−ratio may increase up to 50%. The build−in
slope compensation prevents the appearance of
sub−harmonic oscillations in this operating area.
Low consumption off mode
OFF
ON
Fixed Ipeak
0V
PWM at fOSC
FFM
Skip mode
0.4 V 0.7 V 1.1 V
0.8 V
1.5V
2.0 V 2.2 V
3.5 V
VFB
Figure 43. Mode Control with FB pin voltage
decreases below the 0.4 V the controller will enter the low
consumption off mode. The controller can start if the FB pin
voltage increases above the 2.2 V level.
See the detailed status diagrams for the both versions fully
latched A and the autorecovery B on the following figures.
The basic status of the device after wake–up by the VCC is
the off mode and mode is used for the overheating protection
mode if the thermal shutdown protection is activated.
There was implemented the low consumption off mode
allowing to reach extremely low no load input power. This
mode is controlled by the FB pin and allows the remote
control (or secondary side control) of the power supply
shut−down. Most of the device internal circuitry is unbiased
in the low consumption off mode. Only the FB pin control
circuitry and X2 cap discharging circuitry is operating in the
low consumption off mode. If the voltage at feedback pin
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NCP1244
VCC < VCCreset
VHV > VHV(min)
TSD
Reset
Latch=0
No AC
X2 cap
Discharge
Latch=0
TSD
Stop
(VCC
Soft
Start
SSend
Efficient operating mode
VCC < VCCoff
>
VCCON)*SHV
Skip in
Running
Skip
mode
Skip out
16
Extra Low Consumption
>
VON)*Latch
VCC < VCCreset
Latch
Latch=1
OVP+OTP+VCCovp+VCSstop
Dynamic Self−Supply
(if not enoughgh auxiliary voltage is
present)
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(VFB < VOFF) * GTOMtimer*(VCC > VCCoff)
(VFB
(VFB > VON) * Latch
Off Mode
Latch=X
Regulated Self−Supply
Latch=0
Power On
Reset
VCC > VCCreset
VILIM * tfault
Figure 44. Operating Status Diagram for the Fully Latched Version A of the Device
NCP1244
VCC < VCCreset
TSD
VHV > VHV(min)
No AC
X2 cap
Discharge
Latch=0
AutoRec=0
TSD
Stop
>
VCCON)*SHV
VCC < VCCoff
(VCC
SSend
Efficient operating mode
Soft
Start
Skip in
Skip out
Running
Skip
mode
17
Reset
Latch=0
AutoRec=0
Autorecovery
Latch
AutoRec=1
VCSstop
Dynamic Self−Supply
(if not enoughgh auxiliary voltage is
present)
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(VFB < VOFF) * GTOMtimer*(VCC > VCCoff)
(VFB > VON)*Latch * AutoRec
(VFB > VON) * Latch
Off Mode
Latch=X
AutoRec=X
tautorec
VCC < VCCreset
Latch
Latch=1
OVP+OTP+VCCovp
(VFB > VON) * AutoRec
VILIM * tfault
Extra Low Consumption
Power On
Reset
Latch=0
AutoRec=0
Regulated Self−Supply
VCC > VCCreset
Figure 45. Operating Status Diagram for the Autorecovery Version B of the Device
NCP1244
the HV start−up current source on and off, it can only be used
in light load condition, otherwise the power dissipation on
the die would be too much. As a result, an auxiliary voltage
source is needed to supply VCC during normal operation.
The Dynamic Self−Supply is useful to keep the controller
alive when no switching pulses are delivered, e.g. in latch or
fault condition, or to prevent the controller from stopping
during load transients when the VCC might drop. The
NCP1244 accepts a supply voltage as high as 28 V, with an
overvoltage threshold VCC(ovp) that latches the controller
off.
The information about the fault (permanent Latch or
Autorecovery) is kept during the low consumption off mode
due the safety reason. The reason is not to allow unlatch the
device by the remote control being in off mode.
Start−up of the Controller
At start−up, the current source turns on when the voltage
on the HV pin is higher than VHV(min), and turns off when
VCC reaches VCC(on), then turns on again when VCC reaches
VCC(min), until VCC is supplied by an external source. The
controller actually starts the first time VCC reaches VCC(on)
when the slope on HV pin is positive.
Even though the Dynamic Self−Supply is able to maintain
the VCC voltage between VCC(on) and VCC(min) by turning
VHV
V HV(start)
V HV(min)
Waits next VCC(on)
before starting
time
VCC
V CC(on)
V CC(min)
HV current
source = I start1
HV current
source = Istart2
V CC(inhibit)
time
DRV
Figure 46. VCC Start−up Timing Diagram
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time
NCP1244
when the slope on HV pin is positive during the short ac line
drop−outs. This feature differentiates between the short ac
line drop−outs and application plug off. The minimum
positive slope is defined by the Equation 1 in following
chapter.
For safety reasons, the start−up current is lowered when
VCC is below VCC(inhibit), to reduce the power dissipation in
case the VCC pin is shorted to GND (in case of VCC capacitor
failure, or external pull−down on VCC to disable the
controller). There is only one condition for which the current
source doesn’t turn on when VCC reaches VCC(inhibit): the
voltage on HV pin is too low (below VHV(min)). The
controller can restart only when VCC reaches VCC(on) and
VHV
HV pin slope
SHV is positive
Ac line drop−out
time
VCC
VCC(on)
VCC(min)
VCC(off)
Controller stops
at VCC(off)
VCC charges
up when VHV
is high enough
time
DRV
Switching
restarts at
VCC(on) and
positive SHV
time
Output
VOUT
Loss of
regulation when
VHV is too low
time
Figure 47. Ac Line Drop−out Timing Diagram
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NCP1244
X2 Cap Discharge Feature
In case of the dc signal presence on the high voltage input,
the direct sample of the high voltage obtained via the high
voltage sensing structure and the delayed sample of the high
voltage are equivalent and the comparator produces the low
level signal during the presence of this signal. No edges are
present at the output of the comparator, that’s why the
detection timer is not reset and dc detect signal appears.
The minimum detectable slope by this ac detector is given
by the ration between the maximum hysteresis observed at
HV pin VHV(hyst),max and the sampling time:
The X2 capacitor discharging feature is offered by usage
of the NCP1244. This feature save approx. 16 mW – 25 mW
input power depending on the EMI filter X2 capacitors
volume and it saves the external components count as well.
The discharge feature is ensured via the start−up current
source with a dedicated control circuitry for this function.
The X2 capacitors are being discharged by current defined
as Istart2 when this need is detected.
There is used a dedicated structure called ac line unplug
detector inside the X2 capacitor discharge control circuitry.
See the Figure 48 for the block diagram for this structure and
Figures 49, 50 and 52 for the timing diagrams. The basic
idea of ac line unplug detector lies in comparison of the
direct sample of the high voltage obtained via the high
voltage sensing structure with the delayed sample of the high
voltage. The delayed signal is created by the sample & hold
structure.
The comparator used for the comparison of these signals
is without hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the
sampling time TSAMPLE and additional internal offset NOS.
These parameters ensure the noise immunity as well. The
additional offset is added to the picture of the sampled HV
signal and its analog sum is stored in the C1 storage
capacitor. If the voltage level of the HV sensing structure
output crosses this level the comparator CMP output signal
resets the detection timer and no dc signal is detected. The
additional offset NOS can be measured as the VHV(hyst) on
the HV pin. If the comparator output produces pulses it
means that the slope of input signal is higher than set
resolution level and the slope is positive. If the comparator
output produces the low level it means that the slope of input
signal is lower than set resolution level or the slope is
negative. There is used the detection timer which is reset by
any edge of the comparator output. It means if no edge
comes before the timer elapses there is present only dc signal
or signal with the small ac ripple at the HV pin. This type of
the ac detector detects only the positive slope, which fulfils
the requirements for the ac line presence detection.
S min +
V HV(hyst),max
(eq. 1)
T sample
Than it can be derived the relationship between the
minimum detectable slope and the amplitude and frequency
of the sinusoidal input voltage:
V max +
V HV(hyst),max
2 @ p @ f @ T sample
+
5
2 @ p @ 35 @ 1 @ 10 −3 (eq. 2)
+ 22.7 V
The minimum detectable AC RMS voltage is 16 V at
frequency 35 Hz, if the maximum hysteresis is 5 V and
sampling time is 1 ms.
The X2 capacitor discharge feature is available in any
controller operation mode to ensure this safety feature. The
detection timer is reused for the time limiting of the
discharge phase, to protect the device against overheating.
The discharging process is cyclic and continues until the ac
line is detected again or the voltage across the X2 capacitor
is lower than VHV(min). This feature ensures to discharge
quite big X2 capacitors used in the input line filter to the safe
level. It is important to note that it is not allowed to
connect HV pin to any dc voltage due this feature. e.g.
directly to bulk capacitor.
During the HV sensing or X2 cap discharging the VCC net
is kept above the VCC(off) voltage by the Self−Supply in any
mode of device operation to supply the control circuitry.
During the discharge sequence device runs normally.
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NCP1244
Figure 48. The ac Line Unplug Detector Structure Used for X2 Capacitor Discharge System
Figure 49. The ac Line Unplug Detector Timing Diagram
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NCP1244
Figure 50. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects
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NCP1244
Figure 51. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence when the Application is
Unplugged Under Extremely Low Line Condition
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NCP1244
Figure 52. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under High Line and Heavy Load Condition
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NCP1244
VHV
X2 capacitor
discharge
X2 capacitor
discharge
AC line unplug
time
AC line Unplug
detector starts
No AC detection
One Shot
tDET
tDET
time
DRV
DRV pulses stops
when VCC < VCC(off)
Starts
only at
VCC(on)
X2 discharge
X2 discharge
time
X2 discharge
current
tDIS
tDIS
time
Figure 53. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under High Line and Light Load Condition
The Low Consumption Off Mode
Only the X2 cap discharge and Self−Supply features is
enabled in the low consumption off mode. The X2 cap
discharging feature is enable due the safety reasons and the
Self−Supply is enabled to keep the VCC supply, but only
very low VCC consumption appears in this mode. Any other
features are disabled in this mode.
The information about the latch status of the device is kept
in the low consumption off mode and this mode is used for
the TSD protection as well. The protection timer
GoToOffMode tGTOM is used to protect the application
against the false activation of the low consumption off mode
by the fast drop outs of the FB pin voltage below the 0.4 V
level. E.g. in case when is present high FB pin voltage ripple
during the skip mode.
There was implemented the low consumption off mode
allowing to reach extremely low no load input power as
described in previous chapters. If the voltage at feedback pin
decreases below the 0.4 V the controller enters the off mode.
The internal VCC is turned−off, the IC consumes extremely
low VCC current and only the voltage at external VCC
capacitor is maintained by the Self−Supply circuit. The
Self−Supply circuit keeps the VCC voltage at the VCC(reg)
level. The supply for the FB pin watch dog circuitry and FB
pin bias is provided via the low consumption current sources
from the external VCC capacitor. The controller can only
start, if the FB pin voltage increases above the 2.2 V level.
See Figure 54 for timing diagrams.
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NCP1244
Figure 54. Start−up, Shutdown and AC Line Unplug Time Diagram
Oscillator with Maximum On Time and Frequency
Jittering
The NCP1244 includes an oscillator that sets the
switching frequency 65 kHz or 100 kHz depending on the
version. The maximum on time is 12.3 ms (for 65 kHz
version) or 8 ms (for 100 kHz version) with an accuracy of
±7%. The maximum on time corresponds to maximum duty
cycle of the DRV pin is 80% at full switching frequency. In
order to improve the EMI signature, the switching frequency
jitters ±6 % around its nominal value, with a triangle−wave
shape and at a frequency of 125 Hz. This frequency jittering
is active even when the frequency is decreased to improve
the efficiency in light load condition.
Figure 55. Frequency Modulation of the Maximum
Switching Frequency
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NCP1244
Low Load Operation Modes: Frequency Foldback
Mode (FFM) and Skip Mode
frequency foldback mode to provide the natural transformer
core anti−saturation protection. The frequency jittering is
still active while the oscillator frequency decreases as well.
The current setpoint is fixed to 300 mV in the frequency
foldback mode if the feedback voltage decreases below the
VFB(freeze) level. This feature increases efficiency under the
light loads conditions as well.
In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to fOSC(min). This frequency
foldback starts when the voltage on FB pin goes below
VFB(foldS), and is complete when VFB reaches VFB(foldE).
The maximum on−time duration control is kept during the
Figure 56. Frequency Foldback Mode Characteristic
Figure 57. Current Setpoint Dependency on the Feedback Pin Voltage
When the FB voltage reaches Vskip(in) while decreasing,
skip mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While VFB is
below Vskip(out), the controller remains in this state; but as
soon as VFB crosses the skip out threshold, the DRV pin
starts to pulse again.
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NCP1244
Figure 58. Skip Mode Timing Diagram
Clamped Driver
resulting voltage is applied to the CS pin. It is applied to one
input of the PWM comparator through a 250 ns LEB block.
On the other input the FB voltage divided by 5 sets the
threshold: when the voltage ramp reaches this threshold, the
output driver is turned off. The maximum value for the
current sense is 0.7 V, and it is set by a dedicated comparator.
Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when VCC reaches VCC(on), a
soft−start is applied: the current sense setpoint is increased
by 15 discrete steps from 0 (the minimum level can be
higher than 0 because of the LEB and propagation delay)
until it reaches VILIM (after a duration of tSSTART), or until
the FB loop imposes a setpoint lower than the one imposed
by the soft−start (the two comparators outputs are OR’ed).
The supply voltage for the NCP1244 can be as high as
28 V, but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore clamped safely below 16 V. This
driver has a typical capability of 500 mA for source current
and 800 mA for sink current.
Current−Mode Control With Slope Compensation and
Soft−Start
NCP1244 is a current−mode controller, which means that
the FB voltage sets the peak current flowing in the
inductance and the MOSFET. This is done through a PWM
comparator: the current is sensed across a resistor and the
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NCP1244
Figure 59. Soft−Start Feature
In order to allow the NCP1244 to operate in CCM with a
duty cycle above 50%, the fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical for the 65 kHz version,
and −50 mV/ms for the 100 kHz version. The slope
compensation can be observable as a value of the peak
current at CS pin.
The internal slope compensation circuitry uses a sawtooth
signal synchronized with the internal oscillator is subtracted
from the FB voltage divided by KFB.
Under some conditions, like a winding short−circuit for
instance, not all the energy stored during the on time is
transferred to the output during the off time, even if the on
time duration is at its minimum (imposed by the propagation
delay of the detector added to the LEB duration). As a result,
the current sense voltage keeps on increasing above VILIM,
because the controller is blind during the LEB blanking
time. Dangerously high current can grow in the system if
nothing is done to stop the controller. That’s what the
additional comparator, that senses when the current sense
voltage on CS pin reaches VCS(stop) ( = 1.5 x VILIM ), does:
as soon as this comparator toggles, the controller
immediately enters the protection mode.
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NCP1244
Figure 60. Slope Compensation Block Diagram
Figure 61. Slope Compensation Timing Diagram
Internal Overpower Protection
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.
The power delivered by a flyback power supply is
proportional to the square of the peak current in
discontinuous conduction mode:
P OUT +
1
@ h @ L P @ F SW @ I P
2
2
(eq. 3)
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NCP1244
Figure 62. Needs for Line Compensation For True Overpower Protection
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than VFB(OPCE). However, because the HV pin can be
connected to an ac voltage, there is needed an additional
circuitry to read or at least closely estimate the actual voltage
on the bulk capacitor.
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
Figure 63. Overpower Protection Current Relation to Feedback Voltage
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NCP1244
Figure 64. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage
Figure 65. Block Schematic of Overpower Protection Circuit
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NCP1244
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the output from the ac
line unplug detector. The sensed HV pin voltage peak value
is validated when no HV edges from comparator are present
after last falling edge during two sample clocks. See
Figure 66 for details.
times out, DRV pulses are stopped and the controller is either
latched off (latched protection, option A) or this latch can be
released in autorecovery mode (option B), the controller
tries to restart after tautorec. Another possibility of the latch
release is the VCC power on reset or the ac line unplug event
detected via ac detector. Therefore the latch can be released
by the end of the 1st X2 discharge event. The timer is reset
when the CS setpoint goes back below VILIM before the
timer elapses. The fault timer is also started if the driver
signal is reset by the max duty−ratio. The controller also
enters the same protection mode if the voltage on the CS pin
reaches 1.5 times the maximum internal setpoint VCS(stop)
(allows to detect winding short−circuits) or there appears
low VCC supply. See Figures 67 and 68 for the timing
diagram.
In autorecovery mode if the fault has gone, the supply
resumes operation; if not, the system starts a new burst cycle.
Overcurrent Protection with Fault timer
The overload protection depends only on the current
sensing signal, making it able to work with any transformer,
even with very poor coupling or high leakage inductance.
When an overcurrent occurs on the output of the power
supply, the FB loop asks for more power than the controller
can deliver, and the CS setpoint reaches VILIM. When this
event occurs, an internal tfault timer is started: once the timer
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NCP1244
Figure 66. Overpower Compensation Timing Diagram
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NCP1244
PROTECTION MODES AND THE LATCH MODE RELEASES
Event
Timer Protection
Next Device Status
Release to Normal Operation Mode
Overcurrent
VILIM > 0.7 V
Fault timer
Latch
Autorecovery – B version
1st X2 discharge event
VCC < VCC(reset)
Winding short
Vsense > VCS(stop)
Immediate reaction
Latch
Autorecovery – B version
1st X2 discharge event
VCC < VCC(reset)
Low supply
VCC < VCC(off)
10 ms timer
Latch
1st X2 discharge event
VCC ≥ VCC(reset)
External OTP, OVP
55 ms (35 ms at 100 kHz)
Latch
1st X2 discharge event
VCC < VCC(on)
High supply
VCC > VCC(ovp)
10 ms timer
Latch
1st X2 discharge event
VCC < VCC(reset)
Internal TSD
10 ms timer
Device stops, HV start−up
current source stops
(VCC > VCC(on)) & TSDb
Off mode
VFB < VOFF
600 ms timer
Device stops and internal
VCC is turned off
(VCC > VCC(on)) &
( VFB > VON)
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NCP1244
VCC(on)
VCC(min)
Figure 67. Latched Timer−Based Overcurrent Protection (Option A)
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NCP1244
VCC(on)
VCC(min)
Figure 68. Timer−Based Protection Mode with Autorecovery Release from Latch−off (Option B)
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NCP1244
Latch−Off Input
Figure 69. Latch Detection Schematic
The Latch pin is dedicated to the latch−off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run, but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source INTC.
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the INTC current. To
reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically
1.5 mA at VOVP).
To avoid any false triggering, spikes shorter than 50 ms
(for the high latch and 65 kHz version) or 350 ms (for the low
latch) are blanked and only longer signals can actually latch
the controller.
C LATCH
max +
t SSTART
Reset occurs the VCC is cycled down to a reset voltage,
which in a real application can only happen if the power
supply is unplugged from the ac line.
Upon startup, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once VCC reaches
VCC(on), the latch pin High latch state is taken into account
and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an over temperature) is
taken into account only after the soft−start is finished. In
addition, the NTC current is doubled to INTC(SSTART) during
the soft−start period, to speed up the charging of the Latch
pin capacitor. The maximum value of Latch pin capacitor is
given by the following formula (The standard start−up
condition is considered and the NTC current is neglected):
min @ I NTC(SSTART) min
V clamp0
min
+
8.0 @ 10 −3 @ 130 @ 10 −6
F + 1.04 mF (eq. 4)
1.0
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NCP1244
VCC(on)
VCC(min)
Figure 70. Latch Timing Diagram
Temperature Shutdown
low power consumption. There is kept the VCC supply to
keep the TSD information. When the temperature falls
below the low threshold, the start−up of the device is enabled
again, and a regular start−up sequence takes place. See the
status diagrams at the Figures 44 and 45.
The NCP1244 includes a temperature shutdown
protection with a trip point typically at 150°C and the typical
hysteresis of 30°C. When the temperature rises above the
high threshold, the controller stops switching
instantaneously, and goes to the off mode with extremely
ORDERING INFORMATION 5
Overload Protection
Switching Frequency
Package
Shipping†
NCP1244AD065R2G
Latched
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1244BD065R2G
Autorecovery
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1244AD100R2G
Latched
100 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1244BD100R2G
Autorecovery
100 kHz
SOIC−7
(Pb−Free)
2500 / Tape & Reel
Ordering Part No.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1244
PACKAGE DIMENSIONS
SOIC−7
CASE 751U
ISSUE E
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
DIM
A
B
C
D
G
H
J
K
M
N
S
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NCP1244/D