ON NCP1580DR2G Low voltage synchronous buck controller Datasheet

NCP1580
Low Voltage Synchronous
Buck Controller
The NCP1580 is a voltage mode PWM controller designed to
operate from a 5.0 V or 12 V supply and produce an output voltage as
low as 0.8 V. This 8−pin device provides an optimal level of
integration to reduce size and cost of the power supply. The NCP1580
has a fixed 350 kHz oscillator and soft−start function. The NCP1580
provides a 1.5 A floating gate driver design to drive N−Channel
MOSFETs in a synchronous configuration. Adaptive non−overlap
circuitry reduces switching losses by preventing simultaneous
conduction of both outputs. Protection features include thermal
shutdown and undervoltage lockout (UVLO). The NCP1580 is
available in an 8−pin SOIC package.
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MARKING
DIAGRAM
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A
L
Y
W
Input Voltage Range from 4.5 V to 13.2 V
350 kHz Internal Oscillator
Boost Pin Operates to 26.5 V
Voltage Mode PWM Control
0.8 V 1.5% Internal Reference Voltage
Adjustable Output Voltage
Internal Soft−Start
Internal 1.5 A Gate Drivers
Adaptive Non−Overlap Circuit
90% Max Duty Cycle
Input UVLO
Overtemperature Protection
Fully Specified over −40°C to 85°C
Pb−Free Package is Available
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
BST 1
8 PHASE
TG 2
7 COMP
GND 3
6 FB
BG 4
5 VCC
(Top View)
ORDERING INFORMATION
Device
Applications
•
•
•
•
•
1580
ALYW
NCP1580DR2
Graphics Cards
Desktop Computers
Servers/Networking
DSP and FPGA Power Supply
DC−DC Regulator Modules
NCP1580DR2G
Package
Shipping†
SOIC−8
2500/Tape & Reel
SOIC−8
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
VIN
BST
VCC
FB
TG
VOUT
SWN
COMP
BG GND
Figure 1. Typical Application Diagram
 Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 4
1
Publication Order Number:
NCP1580/D
NCP1580
COMP
FB
TG
GND
VCC
3.3 nF
15 k
BG
2.2
1 F
68.1
4x
22 F
1 H
10 nF
VOUT
MBR130LSFT1
BST
NTD110N02R
10 nF
PHASE
2x
1500 F
NTD60N02R
0.1 F
RB751V40T10
VIN
2x
100 F
2x
1800 F
5.36 k
4.7 nF
20 k
GND
Figure 2. Application Diagram; 12 V Input, 1.0 V at 20 A Output
OSC
FAULT
Comparator
FAULT
+
R
−
SS
S
FB
6
Error Amp
+
−
+
+
−
FAULT
Ramp
OSC
VCC
TG
8
PHASE
4
BG
3
GND
+
−
7
2V
0.8 V (VREF)
2
2V
POR
OSC
COMP
BST
Q
Clock
(VSS)
1
TSD
FAULT
5
Figure 3. Detailed Block Diagram
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2
VCC
NCP1580
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Description
1
BST
Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the
desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this
pin and the PHASE pin. Typical values for CBST range from 0.1 F to 1 F. Ensure that CBST is placed
near the IC.
2
TG
Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET.
3
GND
IC ground reference. All control circuits are referenced to this pin.
4
BG
Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET.
5
VCC
Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 F
capacitor to GND. Ensure that this decoupling capacitor is placed near the IC.
6
FB
This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to
compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or
directly to Vout.
7
COMP
Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM
comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop.
This pin should not be shorted to ground to disable switching.
8
PHASE
Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the
top MOSFET. A Schottky diode between this pin and ground is recommended to reduce negative transient
voltages which is common in a power supply system.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Symbol
VMAX
VMIN
Main Supply Voltage Input
VCC
15 V
−0.3 V
Bootstrap Supply Voltage Input
BST
30 V wrt/GND
15 V wrt/PHASE
−0.3 V
PHASE
30 V
−0.7 V, t > 50 ns
−2.0 V, t < 50 ns
High−Side Driver Output (Top Gate)
TG
30 V wrt/GND
15 V wrt/PHASE
−0.3 V
wrt/PHASE
Low−Side Driver Output (Bottom Gate)
BG
15 V
−0.3 V
Feedback
FB
5.5 V
−0.3 V
COMP
5.5 V
−0.3 V
Symbol
Value
Unit
RJC
45
°C/W
Operating Junction Temperature Range
TJ
−40 to 150
°C
Operating Ambient Temperature Range
TA
−40 to 85
°C
Storage Temperature Range
Tstg
−55 to +150
°C
2.0
200
kV
V
1
−
Switching Node (Bootstrap Supply Return)
COMP
MAXIMUM RATINGS
Rating
Thermal Resistance, Junction−to−Case
ESD Susceptibility
Human Body Model
Charge Device Model
Moisture Sensitivity Level
MSL
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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NCP1580
ELECTRICAL CHARACTERISTICS (−40°C < TA < 85°C, −40°C < TJ < 125°C (Note 1), 4.5 V < VCC < 13.2 V, 4.5 V < BST < 26.5 V,
CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.)
Characteristic
Conditions
Min
Typ
Max
Unit
Input Voltage Range
−
4.5
−
13.2
V
Boost Voltage Range
−
4.5
−
26.5
V
Quiescent Supply Current
VFB = 1.0 V, No Switching
VCC = 13.2 V
−
1.0
1.75
mA
Boost Quiescent Current
VFB = 1.0 V, No Switching
−
140
−
A
UVLO Threshold
VCC Rising Edge
3.85
4.2
−
V
UVLO Hysteresis
−
−
0.5
−
V
TA = 0 to 70°C
TA = −40 to 85°C
0.788
0.784
0.800
−
0.812
0.816
V
Oscillator Frequency
−
288
350
412
kHz
Ramp−Amplitude Voltage
−
−
1.1
−
V
Minimum Duty Cycle
−
−
0
−
%
Maximum Duty Cycle
−
85
90
95
%
Minimum Pulse Width
Static Operating (Note 2)
50
100
150
nsec
DC Gain
(Note 2 )
70
80
−
dB
Gain−Bandwidth Product
(Note 2)
8.0
10
−
MHz
COMP_GND = 100 pF (Note 2)
2.0
4.0
−
V/S
VFB = 1 V (Note 2)
−
0.1
1.0
A
−
6.0
15
ns
−
15
30
ns
−
6.0
15
ns
−
6.0
15
ns
−
1.0
−
A
−
1.5
−
A
−
1.5
−
A
−
1.5
−
A
VCC = 12 V
PHASE < 2.0 V
BG > 2.0 V
−
30
90
ns
VCC = 12 V
BG < 2.0 V
TG > 2.0 V
−
30
40
ns
−
1.0
2.0
3.0
ms
(Note 2)
−
160
−
°C
Supply Current
Undervoltage Lockout
Switching Regulator
VFB Feedback Voltage,
Control Loop in Regulation
Error Amplifier
Slew Rate
FB Bias Current
Gate Drivers
TG Rise Time
TG Fall Time
BG Rise Time
Load = 1.0 nF
VCC = 8.0 V
BG Fall Time
TG Sink Current
TG Source Current
BG Sink Current
VCC = 12 V
VTG = VBG = 2
2.0
0V
((Note 2))
BG Source Current
PHASE falling to BG rising delay
BG falling to TG rising delay
Internal Soft−Start
Time
Thermal Shutdown
Overtemperature Trip Point
1. Specifications to −40°C are guaranteed via correlation using standard statistical quality control (SQC), not tested in production.
2. Guaranteed by design, not tested in production.
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NCP1580
TYPICAL CHARACTERISTIC CURVES
410
400
816
fSW, FREQUENCY (kHz)
VREF, REFERENCE (mV)
812
808
804
800
796
792
390
380
370
VCC = 5.0 V
360
350
340
VCC = 12 V
330
320
310
788
784
−50
−25
0
25
50
75
100
125
300
290
−50
150
−25
2.20
1.25
2.15
1.20
2.10
2.05
VCC = 5.0 V
1.95
VCC = 12 V
1.90
1.85
50
75
100
125
150
1.15
1.10
VCC = 12 V
1.05
1.00
VCC = 5.0 V
0.95
0.90
0.85
0.80
1.80
−50
−25
0
25
50
75
100
125
0.75
−50
150
TJ, JUNCTION TEMPERATURE (°C)
0
25
50
75
100
125
150
Figure 7. Quiescent Current (ICC) vs. Temperature
(No Switching)
100
6.0
VCC = 12 V
5.5
80
60
GAIN (dB)
5.0
VCC = 8.0 V
4.5
4.0
3.5
40
20
0
−20
VCC = 5.0 V
3.0
2.5
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Soft−Start Time (tSS) vs. Temperature
ICC, SUPPLY CURRENT (mA)
25
Figure 5. Oscillator Frequency (fSW) vs.
Temperature
ICC, SUPPLY CURRENT (mA)
tSS, SOFT−START TIME (ms)
Figure 4. Reference Voltage (VREF) vs.
Temperature
2.00
0
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
−40
100
125
150
−60
1.E+02
TJ, JUNCTION TEMPERATURE (°C)
1.E+03
1.E+04
1.E+05
FREQUENCY (Hz)
Figure 8. Quiescent Current (ICC) vs. Temperature
(Switching)
Figure 9. Error Amplifier
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1.E+06 1.E+07
NCP1580
DETAILED OPERATING DESCRIPTION
Input Voltage Range (VCC and BST)
General
The NCP1580 is an 8−pin PWM controller intended for
DC−DC conversion from 5.0 V and 12 V buses. The
NCP1580 has a 1.5 A internal floating gate driver circuit
designed to drive N−Channel MOSFETs in a
synchronous−rectifier buck topology. The internal floating
gate driver simplifies design, improves performance, and
minimizes board area. The output voltage of the converter
can be precisely regulated down to 800 mV 1.5% when
the VFB pin is tied to VOUT. The switching frequency, which
is internally set to 350 kHz, and soft−start are completely
integrated. The voltage error amplifier features a 10 MHz
unity gain bandwidth and 4 V/sec slew rate for fast
transient response.
The input voltage range for both VCC and BST is 4.5 V to
13.2 V with respect to GND and PHASE, respectively.
Although BST is rated at 13.2 V with respect to PHASE, it
can also tolerate 26.5 V with respect to GND.
Normal Shutdown Behavior
Normal shutdown occurs when the IC stops switching
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal SS is discharged, and all
GATE pins go low. The switch node enters a high impedance
state and the output capacitors discharge through the load
with no ringing on the output voltage.
Internal Soft−Start
The NCP1580 features an internal soft−start function,
which reduces inrush current and overshoot of the output
voltage. Figure 10 shows a typical soft−start sequence.
Soft−start is achieved by ramping up the internal soft−start
voltage (VSS) which is applied to the input of the error
amplifier. This ramp is generated by applying 0.5 A to a
100 pf capacitor for 1 sec on every fourth clock pulse. This
sequence begins once VCC surpasses its UVLO threshold
(see Figure 11). The typical soft−start time is 2 msec. The
internal soft−start voltage is held low when the part is in
UVLO.
Duty Cycle and Maximum Pulse Width Limits
In steady state DC operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The NCP1580 can achieve a 90% duty cycle.
There is a built in off−time which ensures that the bootstrap
supply is charged every cycle. The NCP1580, which is
capable of a 100 nsec minimum pulse width (typ), can allow
a 12 V to 1.0 V conversion at 350 kHz.
4.2 V
VCC
4.2 V
2 ms
CLK
VCC
SS
VOUT
1 S
5 mV
TG
UVLO
Startup
VSS
Normal Operation
Figure 10. Normal Startup
Figure 11. Achieving Internal Soft−Start
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NCP1580
UVLO
Drivers
The NCP1580 includes 1.5 A gate drivers to switch
external N−Channel MOSFETs. This allows the NCP1580
to address high−power as well as low−power conversion
requirements. The gate drivers also include adaptive
non−overlap circuitry. The non−overlap circuitry increases
efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time.
A detailed block diagram of the non−overlap and gate
drive circuitry used in the chip is shown in Figure 12.
Careful selection and layout of external components is
required, to realize the full benefit of the onboard drivers.
The capacitors between VCC and GND and between BST
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when VCC is too low to
support the internal rails and power the converter. For the
NCP1580, the UVLO is set to ensure that the IC will start up
when VCC reaches 4.2 V and shutdown when VCC drops
below 3.7 V. This permits operation when converting from
a 5.0 V input voltage.
Thermal Shutdown
The NCP1580 also provides Thermal Shutdown (TSD)
for added protection. The TSD circuit monitors the die
temperature and turns off the top and bottom gate drivers if
an over temperature condition is detected. The internal soft−
start capacitor is also discharged. This is a latched state and
requires a power cycle to reset.
BST
UVLO
FAULT
TG
PHASE
+
−
2V
+
−
2V
VCC
BG
PWM
OUT
GND
UVLO
FAULT
Figure 12. Block Diagram
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NCP1580
APPLICATION SECTION
Input Capacitor Selection
VOUT DISCHARGE 2C
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
where VOUT−DISCHARGE is the voltage deviation of VOUT
due to the effects of discharge, LOUT is the output inductor
value and VIN is the input voltage.
It should be noted that VOUT−DISCHARGE and
VOUT−ESR are out of phase with each other, and the larger
of these two voltages will determine the maximum deviation
of the output voltage (neglecting the effect of the ESL).
IinRMS IOUT D (1 D) ,
where D is the duty cycle, IinRMS is the input RMS current,
and IOUT is the load current. The equation reaches its
maximum value with D = 0.5. Losses in the input capacitors
can be calculated with the following equation:
Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the regulation system, a minimum
inductor
value
is
particularly
important
in
space−constrained applications. From an electrical
perspective, the maximum current slew rate through the
output inductor for a buck regulator is given by:
PCIN ESRCIN IinRMS2,
where PCIN is the power loss in the input capacitors and
ESRCIN is the effective series resistance of the input
capacitance. Due to large dI/dt through the input capacitors,
electrolytic or ceramics should be used. If a tantalum must
be used, it must be surge protected. Otherwise, capacitor
failure could occur.
Calculating Input Startup Current
V VOUT
SlewRateLOUT IN
LOUT
To calculate the input startup current, the following
equation can be used.
Iinrush IOUT2 LOUT
,
OUT (VIN D VOUT)
This equation implies that larger inductor values limit the
regulator’s ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level. This
results in larger values of output capacitance to maintain
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator’s maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak−to−peak ripple
current is given by the following equation:
COUT VOUT
,
tSS
where Iinrush is the input current during startup, COUT is
the total output capacitance, VOUT is the desired output
voltage, and tSS is the internal soft−start interval.
If the inrush current is higher than the steady state input
current during max load, then the input fuse should be rated
accordingly, if one is used.
Output Capacitor Selection
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initially
drops due to the current variation inside the capacitor and the
ESR. (neglecting the effect of the effective series inductance
(ESL)):
Ipk−pkLOUT VOUT(1 D)
LOUT 350 kHZ
,
where Ipk−pkLOUT is the peak to peak current of the output.
From this equation it is clear that the ripple current increases
as LOUT decreases, emphasizing the trade−off between
dynamic response and ripple current.
Feedback and Compensation
The NCP1580 allows the output of the DC−DC converter
to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to VOUT, the controller will
regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.
VOUT−ESR IOUT ESRCOUT,
where VOUT−ESR is the voltage deviation of VOUT due to the
effects of ESR and the ESRCOUT is the total effective series
resistance of the output capacitors.
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is given by
the following equation:
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NCP1580
VOUT
The compensation network consists of the internal error
amplifier and the impedance networks ZIN (R1, R3 and C3)
and ZFB (R4, C1 and C2). The compensation network has to
provide a closed loop transfer function with the highest 0 dB
crossing frequency to have fast response (but always lower
than fSW/8) and the highest gain in DC conditions to
minimize the load regulation. A stable control loop has a
gain crossing with −20 dB/decade slope and a phase margin
greater than 45°. Include worst−case component variations
when determining phase margin. To place the poles and
zeroes of the compensation networks, the following
equations may be used:
Modulator frequencies:
R1
FB
R2
Figure 13.
The relationship between the resistor divider network in
Figure 13 and the output voltage is shown in the following
equation:
LC VREF
R2 R1 .
VOUT VREF
Compensation network frequency:
Resistor R1 is selected based on a design trade off between
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):
Error% 0.1 A R1
VREF
P1 1
1
P2 R3 C3
C1C2
R4 C1C2
Z1 1
1
R4 C2 Z2
(R1 R3) C3
Place Z1, and Z2 around the output filter resonance
LC; Place P1 at the output capacitor ESR zero ESR; Place
P2 at one half of the switching frequency;
The modulator transfer function is the small−signal
transfer function of VOUT/VCOMP. This function has a
double pole at frequency LC and a zero at ESR. The DC
Gain of the modulator is simply the input voltage VIN
divided by the peak−to−peak oscillator voltage VOSC.
100%
Once R1 has been determined, R2 can be calculated.
The NCP1580 utilizes voltage mode control. This is to
say, the control loop regulates VOUT by monitoring VOUT
and controlling the output current. However, since the
control loop is controlling the output current to regulate the
output voltage, there are some stability concerns since the
inductor current is 90 degrees out of phase with the voltage.
It is inherent with all voltage−mode control loops to have a
compensation network.
Error Amplifier
VIN
VRAMP
1
1
ESR L
ESR C
C
OUT
OUT
OUT
Closed Loop
Gain
LOUT
−
+
VOUT
Z1 Z2
ESR
P1 P2
PWM
COMPARATOR
COUT
C1
R4
R1
C2
LC
C3 R3
VREF
ESR
Compensation
Network
Modulator Gain
R2
+
−
Figure 15.
Figure 14. Simplified Diagram of Control Loop
Visit http://www.onsemi.com/pub/Collateral/COMPCALC for
self extracting compensation program for design assistance.
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NCP1580
Thermal Considerations
Where:
QBG = total lower MOSFET gate charge at VCC.
The power dissipation of the NCP1580 varies with the
MOSFETs used, VCC, and the boost voltage (VBST). The
average MOSFET gate current typically dominates the
control IC power dissipation. The IC power dissipation is
determined by the formula:
The junction temperature of the control IC can then be
calculated as:
TJ TA PIC JA.
PIC (ICC VCC) PTG PBG.
Where:
TJ = The junction temperature of the IC,
TA = The ambient temperature,
JA = The junction−to−ambient thermal resistance of the
IC package.
Where:
PIC = Control IC power dissipation,
ICC = IC measured supply current,
VCC = IC supply voltage,
PTG = Top gate driver losses,
PBG = Bottom gate driver losses.
The package thermal resistance (RJC) can be obtained
from the specifications section of this data sheet and a
calculation can be made to determine the IC junction
temperature. In addition, a thermal resistance
(Junction−to−Ambient/Safe Operating Area) curve has been
included below to further aid design. However, it should be
noted that the physical layout of the board, the proximity of
other heat sources such as MOSFETs and inductors, and the
amount of metal connected to the IC, impact the temperature
of the device. Use these calculations as a guide, but
measurements should be taken in the actual application.
The upper (switching) MOSFET gate driver losses are:
PTG QTG fSW VBST.
Where:
QTG = Total upper MOSFET gate charge at VBST,
fSW = The switching frequency,
VBST = The BST pin voltage.
The lower (synchronous) MOSFET gate driver losses are:
175
0.570
0.595
165
0.620
0.645
0.670
JA (°C/W)
155
0.695
145
0.720
1 oz cu
0.745
0.770
135
0.795
125
115
0
0.820
2 oz cu
0.845
0.870
50 100 150 200 250 300 350 400 450 500 550 600 650
Copper Area (mm2)
Figure 16. Thermal Resistance
(Junction−to−Ambient/Safe Operating Area)
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Pd (W) (@ 25°C Ambient)
PBG QBG fSW VCC.
NCP1580
Layout Considerations
VIN
As in any high frequency switching converter, layout is
very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. Figure 17 shows the critical power components
of the converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 17 should be located as close
together as possible. Please note that the capacitors CIN and
COUT each represent numerous physical capacitors. It is
desirable to locate the NCP1580 within 1 inch of the
MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’
gate and source connections from the NCP1580 must be
sized to handle up to 2.0 A peak current.
Q1
PHASE
NCP1580
Q2
BG
VOUT
CIN
D2
COUT
GND
RETURN
Figure 17.
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11
R1
LOAD
LOUT
TG
NCP1580
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
X 45 DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NCP1580/D
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