LTM8048 3.1VIN to 32VIN Isolated µModule DC/DC Converter with LDO Post Regulator FEATURES DESCRIPTION n The LTM®8048 is an isolated flyback μModule DC/DC converter with LDO post regulator. The LTM8048 has an isolation rating of 725VDC. Included in the package are the switching controller, power switches, transformer, and all support components. Operating over an input voltage range of 3.1V to 32V, the LTM8048 supports an output voltage range of 2.5V to 13V, set by a single resistor. There is also a linear post regulator whose output voltage is adjustable from 1.2V to 12V as set by a single resistor. Only output, input, and bypass capacitors are needed to finish the design. Other components may be used to control the soft-start control and biasing. n n n n n n n n n Complete Switch Mode Power Supply 725VDC Isolation Wide Input Voltage Range: 3.1V to 32V VOUT1 Output: Up to 440mA (VOUT1 = 2.5V, 24VIN) 2.5V to 13V Output Range VOUT2 Low Noise Linear Post Regulator: Up to 300mA 1.2V to 12V Output Range Current Mode Control Programmable Soft-Start User Configurable Undervoltage Lockout (e1) RoHS Compliant Package Low Profile (11.25mm × 9mm × 4.92mm) Surface Mount BGA Package APPLICATIONS n n n The LTM8048 is packaged in a thermally enhanced, compact (11.25mm × 9mm × 4.92mm) over-molded ball grid array (BGA) package suitable for automated assembly by standard surface mount equipment. The LTM8048 is RoHS compliant. L, LT, LTC, LTM, Linear Technology, the Linear logo and μModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Industrial Sensors Industrial Switches Ground Loop Mitigation TYPICAL APPLICATION Total Output Current vs VIN 725V DC Isolated Low Noise μModule Regulator VIN 3.1V TO 30V VIN RUN BIAS 4.7μF 6.19k ADJ1 SS GND ISOLATION BARRIER 2.2μF VOUT1 330 5.7V 280 VOUT2 5V VOUT2 BYP 22μF ADJ2 162k 10μF VOUT– 725VDC ISOLATION 8048 TA01 VOUT1 CURRENT (mA) LTM8048 230 180 130 80 0 5 10 20 15 INPUT VOLTAGE (V) 25 30 8048 TA01b 8048fa 1 LTM8048 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) VIN, RUN, BIAS ........................................................32V ADJ1, SS .....................................................................5V VOUT1 Relative to VOUT– ............................................16V (VIN – GND) + (VOUT1 – VOUT–) .................................36V VOUT2 Relative to VOUT– ..........................................+20V ADJ2 Relative to VOUT– .............................................+7V BYP Relative to VOUT– ............................................+0.6V BIAS Above VIN ........................................................ 0.1V GND to VOUT– Isolation (Note 2) ........................ 725VDC Maximum Internal Temperature (Note 3) .............. 125°C Maximum Solder Temperature .............................. 250°C Storage Temperature.............................. –55°C to 125°C TOP VIEW A ADJ2 B C D BANK 3 VOUT2 BYP BANK 2 VOUT– BANK 1 VOUT1 E F BANK 5 VIN BANK 4 GND RUN ADJ1 G H BIAS SS 1 2 3 4 5 6 7 BGA PACKAGE 45-LEAD (11.25mm × 9mm × 4.92mm) TJMAX = 125°C, θJA = 23.2°C/W, θJCbottom = 5.8°C/W, θJCtop = 23.2°C/W, θJB = 6.7°C/W WEIGHT = 1.1g, θ VALUES DETERMINED PER JEDEC 51-9, 51-12 ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (Note 3) LTM8048EY#PBF LTM8048EY#PBF LTM8048Y 45-Lead (11.25mm × 9mm × 4.92mm) BGA –40°C to 125°C LTM8048IY#PBF LTM8048IY#PBF LTM8048Y 45-Lead (11.25mm × 9mm × 4.92mm) BGA –40°C to 125°C LTM8048MPY#PBF LTM8048MPY#PBF LTM8048Y 45-Lead (11.25mm × 9mm × 4.92mm) BGA –55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 8048fa 2 LTM8048 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, RUN = 12V (Note 3). PARAMETER CONDITIONS Minimum Input DC Voltage BIAS = VIN MIN TYP VOUT1 DC Voltage RADJ1 = 12.4k RADJ1 = 7.15k RADJ1 = 3.16k 2.5 5 12 VIN Quiescent Current VRUN = 0V Not Switching 850 l MAX UNITS 3.1 V V V V 1 μA μA VOUT1 Line Regulation 6V ≤ VIN ≤ 31V, IOUT = 0.15A 1.7 % VOUT1 Load Regulation 0.05A ≤ IOUT ≤ 0.2A 1.5 % VOUT1 Ripple (RMS) IOUT = 0.1A 20 mV Input Short Circuit Current VOUT1 Shorted RUN Pin Input Threshold RUN Pin Rising 30 RUN Pin Current VRUN = 1V VRUN = 1.3V 2.5 0.1 0.7 V SS Sourcing Current SS = 0V –10 μA BIAS Current VIN = 12V, BIAS = 5V, ILOAD1 = 100mA 8 mA 1.18 SS Threshold 1.24 Minimum BIAS Voltage (Note 4) ILOAD1 = 100mA LDO (VOUT2) Minimum Input DC Voltage (Note 5) 1.8 VOUT2 Voltage Range VOUT1 = 16V, RADJ2 Open, No Load (Note 5) VOUT1 = 16V, RADJ2 = 41.2k, No Load (Note 5) 1.22 15.8 ADJ2 Pin Voltage VOUT1 = 2V, IOUT2 = 1mA (Note 5) VOUT1 = 2V, IOUT2 = 1mA, E- and I-Grades (Note 5) VOUT1 = 2V, IOUT2 = 1mA, MP-Grade (Note 5) l l mA 1.30 V μA μA 3.1 V 2.3 V V V 1.22 1.19 1.15 V V V 1.25 1.29 VOUT2 Line Regulation 2V < VOUT1 < 16V, IOUT2 = 1mA (Note 5) 1 5 mV VOUT2 Load Regulation VOUT1 = 5V, 10mA < IOUT2 = 300mA (Note 5) 2 10 mV LDO Dropout Voltage IOUT2 = 10mA (Note 5) IOUT2 = 100mA (Note 5) IOUT2 = 300mA (Note 5) VOUT2 Ripple (RMS) CBYP = 0.01μF, IOUT2 = 300mA, BW = 100Hz to 100kHz (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM8048 isolation is tested at 725VDC for one second in each polarity. Note 3: The LTM8048E is guaranteed to meet performance specifications from 0°C to 125°C. Specifications over the –40°C to 125°C internal temperature range are assured by design, characterization and correlation with statistical process controls. LTM8048I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature 0.25 0.34 0.43 20 V V V μVRMS range. The LTM8048MP is guaranteed to meet specifications over the full –55°C to 125°C internal operating temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 4: This is the BIAS pin voltage at which the internal circuitry is powered through the BIAS pin and not the integrated regulator. See BIAS Pin Considerations for details. Note 5: VRUN = 0V (Flyback not running), but the VOUT2 post regulator is powered by applying a voltage to VOUT1. 8048fa 3 LTM8048 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, operating conditions are as in Table 1 (TA = 25°C). Efficiency vs Load 90 Efficiency vs Load 90 VOUT1 = 2.5V BIAS = 5V Efficiency vs Load 90 VOUT1 = 3.3V BIAS = 5V VOUT1 = 5V BIAS = 5V 12VIN EFFICIENCY (%) EFFICIENCY (%) 12VIN 70 24VIN 80 24VIN 70 60 50 12VIN 80 EFFICIENCY (%) 80 60 0 100 300 200 400 VOUT1 CURRENT (mA) 50 500 60 100 300 200 VOUT1 CURRENT (mA) 0 VOUT1 = 8V BIAS = 5V 300 VOUT1 = 2.5V 8.0 BIAS = 5V VOUT1 = 12V BIAS = 5V EFFICIENCY (%) 80 24VIN 70 60 60 12VIN 7.5 12VIN 70 350 BIAS Current vs VOUT1 Load 90 24VIN 100 150 200 250 VOUT1 CURRENT (mA) 8.5 BIAS CURRENT (mA) 90 80 50 8048 G03 Efficiency vs Load 100 12VIN 0 8048 G02 Efficiency vs Load EFFICIENCY (%) 50 400 8048 G01 100 24VIN 70 7.0 24VIN 6.5 6.0 5.5 5.0 4.5 0 50 100 150 200 250 VOUT1 CURRENT (mA) 300 350 0 50 150 200 100 VOUT1 CURRENT (mA) 8048 G04 BIAS Current vs VOUT1 Load VOUT1 = 5V BIAS = 5V 12VIN 9 6.0 5.5 VOUT1 = 8V 11 BIAS = 5V 12VIN 8 24VIN 7 6 12VIN 10 9 24VIN 8 7 6 5.0 5 5 4.5 4.0 500 BIAS Current vs VOUT1 Load BIAS CURRENT (mA) BIAS CURRENT (mA) BIAS CURRENT (mA) 24VIN 200 300 400 VOUT1 CURRENT (mA) 12 7.5 6.5 100 8048 G06 BIAS Current vs VOUT1 Load 10 7.0 0 8048 G05 8.5 VOUT1 = 3.3V 8.0 BIAS = 5V 4.0 250 0 100 300 200 VOUT1 CURRENT (mA) 400 8048 G07 4 0 50 100 150 200 250 VOUT1 CURRENT (mA) 300 350 8048 G08 4 0 50 100 150 200 250 VOUT1 CURRENT (mA) 300 350 8048 G09 8048fa 4 LTM8048 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, operating conditions are as in Table 1 (TA = 25°C). BIAS Current vs VOUT1 Load Maximum Load vs VIN 13 BIAS = VIN IF VIN ≤ 5V 450 BIAS = 5V IF VIN > 5V MAXIMUM VOUT1 LOAD (mA) 12VIN BIAS CURRENT (mA) 11 10 9 350 24VIN 8 7 6 400 350 300 250 200 2.5VOUT1 3.3VOUT1 5VOUT1 150 5 0 50 100 150 200 VOUT1 CURRENT (mA) 250 100 0 5 10 15 VIN (V) 20 25 8048 G10 15 150 100 50 0 30 30 25 20 15 10 10 15 VIN (V) 20 25 70 12 9 6 60 50 40 30 3 20 0 5 10 15 VIN (V) 20 25 30 0 0 5 10 15 VIN (V) 20 25 10 30 VOUT2 Output Ripple and Noise 0.6 500μV/DIV 150 125 100 1μs/DIV 75 MEASURED PER AN70, USING HP461A AMPLIFIER, 150MHz BW 20 VIN (V) 30 40 8048 G16 8048 G26 VOUT2 DROPOUT VOLTAGE (mV) 200 10 8 12 16 20 VIN (V) 24 28 32 VOUT2 Dropout Voltage vs Load 0.7 0 4 8048 G15 225 175 0 8048 G14 Input Current vs VIN VOUT2 Shorted INPUT CURRENT (mA) 5 80 8VOUT1 12VOUT1 8048 G13 50 0 Input Current vs VIN VOUT1 Shorted 5 0 8VOUT1 12VOUT1 8048 12 INPUT CURRENT (mA) MINIMUM VOUT1 LOAD (mA) MINIMUM VOUT1 LOAD (mA) 200 Minimum Load vs VIN 2.5VOUT1 3.3VOUT1 5VOUT1 35 250 8048 G11 Minimum Load vs VIN 40 BIAS = VIN IF VIN ≤ 5V BIAS = 5V IF VIN > 5V 300 MAXIMUM VOUT1 LOAD (mA) VOUT1 = 12V 12 BIAS = 5V 4 Maximum Load vs VIN 500 VOUT2 = 3.3V 125°C 0.5 25°C 0.4 0.3 –40°C 0.2 0.1 0 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) 300 8048 G17 8048fa 5 LTM8048 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, operating conditions are as in Table 1 (TA = 25°C). Junction Temperature Rise vs Load Current 8 7 6 5 4 3 3.3VIN 5VIN 12VIN 24VIN 2 1 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) 8 7 6 5 4 3 3.3VIN 5VIN 12VIN 24VIN 2 1 0 300 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) 8048 G18 7 6 5 4 3 3.3VIN 5VIN 12VIN 24VIN 1 0 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) 6 5 4 3 300 8048 G21 3.3VIN 5VIN 12VIN 24VIN 2 1 0 300 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) Junction Temperature Rise vs Load Current 14 VOUT2 = 3.3V VOUT2 = 5V 12 8 6 4 3.3VIN 5VIN 12VIN 24VIN 2 0 300 8048 G20 10 TEMPERATURE RISE (°C) TEMPERATURE RISE (°C) 12 8 2 7 Junction Temperature Rise vs Load Current VOUT2 = 2.5V 9 8 8048 G19 Junction Temperature Rise vs Load Current 10 VOUT2 = 1.8V 9 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) 300 8048 G22 TEMPERATURE RISE (°C) 0 10 VOUT2 = 1.5V 9 TEMPERATURE RISE (°C) TEMPERATURE RISE (°C) 10 VOUT2 = 1.2V 9 Junction Temperature Rise vs Load Current TEMPERATURE RISE (°C) 10 Junction Temperature Rise vs Load Current 10 8 6 4 3.3VIN 5VIN 12VIN 24VIN 2 0 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) 300 8048 G23 8048fa 6 LTM8048 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, operating conditions are as in Table 1 (TA = 25°C). Junction Temperature Rise vs Load Current 16 Junction Temperature Rise vs Load Current 16 VOUT2 = 8V 12 10 8 6 4 3.3VIN 5VIN 12VIN 24VIN 2 0 VOUT2 = 12V 14 0 50 100 150 200 250 VOUT2 LOAD CURRENT (mA) 300 8048 G24 TEMPERATURE RISE (°C) TEMPERATURE RISE (°C) 14 12 10 8 6 4 3.3VIN 5VIN 12VIN 24VIN 2 0 0 50 100 150 200 VOUT2 LOAD CURRENT (mA) 250 8048 G25 8048fa 7 LTM8048 PIN FUNCTIONS VOUT1 (Bank 1): VOUT1 and VOUT– comprise the isolated output of the LTM8048 flyback stage. Apply an external capacitor between VOUT1 and VOUT–. Do not allow VOUT– to exceed VOUT1. VOUT– (Bank 2): VOUT– is the return for both VOUT1 and VOUT2. VOUT1 and VOUT– comprise the isolated output of the LTM8048. In most applications, the bulk of the heat flow out of the LTM8048 is through the GND and VOUT– pads, so the printed circuit design has a large impact on the thermal performance of the part. See the PCB Layout and Thermal Considerations sections for more details. Apply an external capacitor between VOUT1 and VOUT–. VOUT2 (Bank 3): The output of the secondary side linear post regulator. Apply the load and output capacitor between VOUT2 and VOUT–. See the Applications Information section for more information on output capacitance and reverse output characteristics. BYP (Pin B2): The BYP pin is used to bypass the reference of the LDO to achieve low noise performance from the linear post regulator. The BYP pin is clamped internally to ±0.6V relative to VOUT–. A small capacitor from VOUT2 to this pin will bypass the reference to lower the output voltage noise. A maximum value of 0.01μF can be used for reducing output voltage noise to a typical 20μVRMS over a 100Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. RUN (Pin F3): A resistive divider connected to VIN and this pin programs the minimum voltage at which the LTM8048 will operate. Below 1.24V, the LTM8048 does not deliver power to the secondary. Above 1.24V, power will be delivered to the secondary and 10μA will be fed into the SS pin. When RUN is less than 1.24V, the pin draws 2.5μA, allowing for a programmable hysteresis. Do not allow a negative voltage (relative to GND) on this pin. GND (Bank 4): This is the primary side local ground of the LTM8048 primary. In most applications, the bulk of the heat flow out of the LTM8048 is through the GND and VOUT– pads, so the printed circuit design has a large impact on the thermal performance of the part. See the PCB Layout and Thermal Considerations sections for more details. ADJ1 (Pins G7): Apply a resistor from this pin to GND to set the output voltage VOUT1 relative to VOUT–, using the recommended value given in Table 1. If Table 1 does not list the desired VOUT1 value, the equation VIN (Bank 5): VIN supplies current to the LTM8048’s internal regulator and to the integrated power switch. These pins must be locally bypassed with an external, low ESR capacitor. may be used to approximate the value. To the seasoned designer, this exponential equation may seem unusual. The equation is exponential due to non-linear current sources that are used to temperature compensate the regulation. ADJ2 (pin A2): This is the input to the error amplifier of the secondary side LDO post regulator. This pin is internally clamped to ±7V. The ADJ2 pin voltage is 1.22V referenced to VOUT– and the output voltage range is 1.22V to 12V. Apply a resistor from this pin to VOUT–, using the equation RADJ2 = 608.78/(VOUT2 – 1.22)kΩ. If the post regulator is not used, leave this pin floating. BIAS (Pin H5): This pin supplies the power necessary to operate the LTM8048. It must be locally bypassed with a low ESR capacitor of at least 4.7μF. Do not allow this pin voltage to rise above VIN. ( ) R ADJ1 = 28.4 VOUT1–0.879 kΩ SS (Pin H6): Place a soft-start capacitor here to limit inrush current and the output voltage ramp rate. Do not allow a negative voltage (relative to GND) on this pin. 8048fa 8 LTM8048 BLOCK DIAGRAM VOUT1 VIN VOUT2 t t 0.1μF 499k ADJ2 1μF LOW NOISE LDO BYP RUN BIAS* SS VOUT– CURRENT MODE CONTROLLER ADJ1 GND 8048 BD *DO NOT ALLOW BIAS VOLTAGE TO BE ABOVE VIN 8048fa 9 LTM8048 OPERATION The LTM8048 is a stand-alone isolated flyback switching DC/DC power supply that can deliver up to 440mA of output current. This module provides a regulated output voltage programmable via one external resistor from 2.5V to 13V. It is also equipped with a high performance linear post regulator. The input voltage range of the LTM8048 is 3.1V to 32V. Given that the LTM8048 is a flyback converter, the output current depends upon the input and output voltages, so make sure that the input voltage is high enough to support the desired output voltage and load current. The Typical Performance Characteristics section gives several graphs of the maximum load versus VIN for several output voltages. A simplified block diagram is given. The LTM8048 contains a current mode controller, power switching element, power transformer, power Schottky diode, a modest amount of input and output capacitance and a high performance linear post regulator. The LTM8048 has a galvanic primary to secondary isolation rating of 725VDC. This is verified by applying 725VDC between the primary to secondary for 1 second and then applying –725VDC for 1 second. For details please refer to the Isolation and Working Voltage section. An internal regulator provides power to the control circuitry. The bias regulator normally draws power from the VIN pin, but if the BIAS pin is connected to an external voltage higher than 3.1V, bias power will be drawn from the external source, improving efficiency. VBIAS must not exceed VIN. The RUN pin is used to turn on or off the LTM8048, disconnecting the output and reducing the input current to 1μA or less. The LTM8048 is a variable frequency device. For a fixed input and output voltage, the frequency increases as the load increases. For light loads, the current through the internal transformer may be discontinuous. The post regulator is a high performance 300mA low dropout regulator with micropower quiescent current and shutdown. The device is capable of supplying 300mA at a dropout voltage of 300mV. Output voltage noise can be lowered to 20μVRMS over a 100Hz to 100kHz bandwidth with the addition of a 0.01μF reference bypass capacitor. Additionally, this reference bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. The linear regulator is protected against both reverse input and reverse output voltages. 8048fa 10 LTM8048 APPLICATIONS INFORMATION For most applications, the design process is straight forward, summarized as follows: 1. Look at Table 1a (or Table 1b, if the post linear regulator is used) and find the row that has the desired input range and output voltage. 2. Apply the recommended CIN, COUT1, COUT2, RADJ1, RADJ2 and CBYP if required. 3. Connect BIAS as indicated, or tie to an external source up to 15V or VIN, whichever is less. While these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended system’s line, load and environmental conditions. Bear in mind that the maximum output current may be limited by junction temperature, the relationship between the input and output voltage magnitude and polarity and other factors. Please refer to the graphs in the Typical Performance Characteristics section for guidance. Capacitor Selection Considerations The CIN, COUT1 and COUT2 capacitor values in Table 1 are the minimum recommended values for the associated operating conditions. Applying capacitor values below those indicated in Table 1 is not recommended, and may result in undesirable operation. Using larger values is generally acceptable, and can yield improved dynamic response, if it is necessary. Again, it is incumbent upon the user to verify proper operation over the intended system’s line, load and environmental conditions. Ceramic capacitors are small, robust and have very low ESR. However, not all ceramic capacitors are suitable. X5R and X7R types are stable over temperature and applied voltage and give dependable service. Other types, including Y5V and Z5U have very large temperature and voltage coefficients of capacitance. In an application circuit they may have only a small fraction of their nominal capacitance resulting in much higher output voltage ripple than expected. A final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the LTM8048. A ceramic input capacitor combined with trace or cable inductance forms a high-Q (underdamped) tank circuit. If the LTM8048 circuit is plugged into a live supply, the input voltage can ring to much higher than its nominal value, possibly exceeding the device’s rating. This situation is easily avoided; see the Hot-Plugging Safely section. LTM8048 Table 1a. Recommended Component Values and Configuration for Specific VOUT1 Voltages (TA = 25°C) VIN VOUT1 VBIAS CIN COUT1 RADJ1 3.1V to 32V 2.5V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 12.4k 3.1V to 32V 3.3V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10k 3.1V to 29V 5V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 16V, 1210 7.15k 3.1V to 26V 8V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 10V, 1206 4.53k 3.1V to 24V 12V 3.1V to 15V or Open 2.2μF, 25V, 0805 10μF, 16V, 1210 3.16k 9V to 15V 2.5V VIN 2.2μF, 50V, 1206 100μF, 6.3V, 1210 12.4k 9V to 15V 3.3V VIN 2.2μF, 50V, 1206 47μF, 6.3V, 1210 10k 9V to 15V 5V VIN 2.2μF, 50V, 1206 22μF, 16V, 1210 7.15k 9V to 15V 8V VIN 2.2μF, 50V, 1206 22μF, 10V, 1206 4.53k 9V to 15V 12V VIN 2.2μF, 25V, 0805 10μF, 16V, 1210 3.16k 18V to 32V 2.5V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 12.4k 18V to 32V 3.3V 3.1V to 15V or Open 2.2μF, 50V, 1206 47μF, 6.3V, 1210 10k 18V to 29V 5V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 16V, 1210 7.15k 18V to 26V 8V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 10V, 1206 4.53k 18V to 24V 12V 3.1V to 15V or Open 2.2μF, 50V, 1206 10μF, 16V, 1210 3.16k Note: Do not allow BIAS to exceed VIN, a bulk input capacitor is required. 8048fa 11 LTM8048 APPLICATIONS INFORMATION LTM8048 Table 1b. Recommended Component Values and Configuration for Specific VOUT2 Voltages (TA = 25°C) VIN VOUT1 VOUT2 VBIAS CIN COUT1 COUT2 RADJ1 RADJ2 3.1V to 32V 1.71V 1.2V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 16.5k Open 3.1V to 32V 2.02V 1.5V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 14.7k 2.32M 3.1V to 32V 2.34V 1.8V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 13.3k 1.07M 3.1V to 32V 3.08V 2.5V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 10.5k 487k 3.1V to 32V 3.92V 3.3V 3.1V to 15V or Open 2.2μF, 50V, 1206 47μF, 6.3V, 1210 10μF, 6.3V, 1206 8.66k 294k 3.1V to 29V 5.7V 5V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 16V, 1210 10μF, 6.3V, 1206 6.19k 162k 3.1V to 26V 8.85V 8V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 10V, 1206 10μF, 10V, 1206 4.12k 88.7k 3.1V to 21V 13V 12V 3.1V to 15V or Open 2.2μF, 25V, 0805 10μF, 16V, 1210 10μF, 16V, 1206 2.94k 56.2k 9V to 15V 1.71V 1.2V VIN 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 16.5k Open 9V to 15V 2.02V 1.5V VIN 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 14.7k 2.32M 9V to 15V 2.34V 1.8V VIN 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 13.3k 1.07M 9V to 15V 3.08V 2.5V VIN 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 10.5k 487k 9V to 15V 3.92V 3.3V VIN 2.2μF, 50V, 1206 47μF, 6.3V, 1210 10μF, 6.3V, 1206 8.66k 294k 9V to 15V 5.7V 5V VIN 2.2μF, 50V, 1206 22μF, 16V, 1210 10μF, 6.3V, 1206 6.19k 162k 9V to 15V 8.85V 8V VIN 2.2μF, 50V, 1206 22μF, 10V, 1206 10μF, 10V, 1206 4.12k 88.7k 9V to 15V 13V 12V VIN 2.2μF, 25V, 0805 10μF, 16V, 1210 10μF, 16V, 1206 2.94k 56.2k 18V to 32V 1.71V 1.2V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 16.5k Open 18V to 32V 2.02V 1.5V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 14.7k 2.32M 18V to 32V 2.34V 1.8V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 13.3k 1.07M 18V to 32V 3.08V 2.5V 3.1V to 15V or Open 2.2μF, 50V, 1206 100μF, 6.3V, 1210 10μF, 6.3V, 1206 10.5k 487k 18V to 32V 3.92V 3.3V 3.1V to 15V or Open 2.2μF, 50V, 1206 47μF, 6.3V, 1210 10μF, 6.3V, 1206 8.66k 294k 18V to 29V 5.7V 5V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 16V, 1210 10μF, 6.3V, 1206 6.19k 162k 18V to 26V 8.85V 8V 3.1V to 15V or Open 2.2μF, 50V, 1206 22μF, 10V, 1206 10μF, 10V, 1206 4.12k 88.7k Note: Do not allow BIAS to exceed VIN, a bulk input capacitor is required. BIAS Pin Considerations The BIAS pin is the output of an internal linear regulator that powers the LTM8048’s internal circuitry. It is set to 3V and must be decoupled with a low ESR capacitor of at least 4.7μF. The LTM8048 will run properly without applying a voltage to this pin, but will operate more efficiently and dissipate less power if a voltage greater than 3.1V is applied. At low VIN, the LTM8048 will be able to deliver more output current if BIAS is 3.1V or greater. Up to 32V may be applied to this pin, but a high BIAS voltage will cause excessive power dissipation in the internal circuitry. For applications with an input voltage less than 15V, the BIAS pin is typically connected directly to the VIN pin. For input voltages greater than 15V, it is preferred to leave the BIAS pin separate from the VIN pin, either powered from a separate voltage source or left running from the internal regulator. This has the added advantage of keeping the physical size of the BIAS capacitor small. Do not allow BIAS to rise above VIN. Soft-Start For many applications, it is necessary to minimize the inrush current at start-up. The built-in soft-start circuit significantly reduces the start-up current spike and output voltage overshoot by applying a capacitor from SS to GND. When the LTM8048 is enabled, whether from VIN reaching a sufficiently high voltage or RUN being pulled high, the LTM8048 will source approximately 10μA out of the SS pin. As this current gradually charges the capacitor from SS to GND, the LTM8048 will correspondingly increase the power delivered to the output, allowing for a graceful turn-on ramp. 8048fa 12 LTM8048 APPLICATIONS INFORMATION Isolation and Working Voltage VOUT2 Post Regulator Bypass Capacitance and Low Noise Performance The LTM8048 isolation is tested by tying all of the primary pins together, all of the secondary pins together and subjecting the two resultant circuits to a differential of ±725VDC for one second. This establishes the isolation voltage rating, but it does not determine the working voltage rating, which is subject to the application board layout and possibly other factors. The metal to metal separation of the primary and secondary throughout the LTM8048 substrate is 0.44mm. The VOUT2 linear regulator may be used with the addition of a 0.01μF bypass capacitor from VOUT to the BYP pin to lower output voltage noise. A good quality low leakage capacitor, such as a X5R or X75 ceramic, is recommended. This capacitor will bypass the reference of the regulator, lowering the output voltage noise to as low as 20μVRMS. Using a bypass capacitor has the added benefit of improving transient response. VOUT2 Post Regulator PCB Layout VOUT2 is produced by a high performance low dropout 300mA regulator. At full load, its dropout is less than 430mV over temperature. Its output is set by applying a resistor from the RADJ2 pin to GND; the value of RADJ2 can be calculated by the equation: Most of the headaches associated with PCB layout have been alleviated or even eliminated by the high level of integration of the LTM8048. The LTM8048 is nevertheless a switching power supply, and care must be taken to minimize electrical noise to ensure proper operation. Even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. See Figure 1 for a suggested layout. Ensure that the grounding and heat sinking are acceptable. R ADJ2 = 608.78 kΩ VOUT2 – 1.22 VOUT1 to VOUT– Reverse Voltage The LTM8048 cannot tolerate a reverse voltage from VOUT1 to VOUT– during operation. If VOUT– raises above VOUT1 during operation, the LTM8048 may be damaged. To protect against this condition, a low forward drop power Schottky diode has been integrated into the LTM8048, anti-parallel to VOUT1/VOUT–. This can protect the output against many reverse voltage faults. Reverse voltage faults can be both steady state and transient. An example of a steady state voltage reversal is accidentally misconnecting a powered LTM8048 to a negative voltage source. An example of transient voltage reversals is a momentary connection to a negative voltage. It is also possible to achieve a VOUT1 reversal if the load is short-circuited through a long cable. The inductance of the long cable forms an LC tank circuit with the VOUT1 capacitance, which drive VOUT1 negative. Avoid these conditions. ADJ1 VOUT1 LTM8048 SS COUT1 BIAS GND VOUT– RUN ADJ2 BYP COUT2 CIN VOUT2 VIN THERMAL/INTERCONNECT VIAS 8048 F01 Figure 1. Layout Showing Suggested External Components, Planes and Thermal Vias 8048fa 13 LTM8048 APPLICATIONS INFORMATION A few rules to keep in mind are: 1. Place the RADJ1 and RADJ2 resistors as close as possible to their respective pins. 2. Place the CIN capacitor as close as possible to the VIN and GND connections of the LTM8048. 3. Place the COUT1 capacitor as close as possible to VOUT1 and VOUT–. Likewise, place the COUT2 capacitor as close as possible to VOUT2 and VOUT–. 4. Place the CIN and COUT capacitors such that their ground current flow directly adjacent or underneath the LTM8048. 5. Connect all of the GND connections to as large a copper pour or plane area as possible on the top layer. Avoid breaking the ground connection between the external components and the LTM8048. 6. Use vias to connect the GND copper area to the board’s internal ground planes. Liberally distribute these GND vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. Pay attention to the location and density of the thermal vias in Figure 1. The LTM8048 can benefit from the heat sinking afforded by vias that connect to internal GND planes at these locations, due to their proximity to internal power handling components. The optimum number of thermal vias depends upon the printed circuit board design. For example, a board might use very small via holes. It should employ more thermal vias than a board that uses larger holes. Hot-Plugging Safely The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of the LTM8048. However, these capacitors can cause problems if the LTM8048 is plugged into a live supply (see Linear Technology Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the VIN pin of the LTM8048 can ring to more than twice the nominal input voltage, possibly exceeding the LTM8048’s rating and damaging the part. A similar phenomenon can occur inside the LTM8048 module, at the output of the integrated EMI filter, with the same potential of damaging the part. If the input supply is poorly controlled or the user will be plugging the LTM8048 into an energized supply, the input network should be designed to prevent this overshoot. This can be accomplished by installing a small resistor in series to VIN, but the most popular method of controlling input voltage overshoot is adding an electrolytic bulk capacitor to the VIN or fIN net. This capacitor’s relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. The extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it can be a large component in the circuit. Thermal Considerations The LTM8048 output current may need to be derated if it is required to operate in a high ambient temperature. The amount of current derating is dependent upon the input voltage, output power and ambient temperature. The temperature rise curves given in the Typical Performance Characteristics section can be used as a guide. These curves were generated by the LTM8048 mounted to a 58cm2 4-layer FR4 printed circuit board. Boards of other sizes and layer count can exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended system’s line, load and environmental operating conditions. For increased accuracy and fidelity to the actual application, many designers use FEA to predict thermal performance. To that end, the Pin Configuration section of the data sheet typically gives four thermal coefficients: θJA: Thermal resistance from junction to ambient θJCbottom: Thermal resistance from junction to the bottom of the product case θJCtop: Thermal resistance from junction to top of the product case θJCboard: Thermal resistance from junction to the printed circuit board. While the meaning of each of these coefficients may seem to be intuitive, JEDEC has defined each to avoid confusion and inconsistency. These definitions are given in JESD 51-12, and are quoted or paraphrased as follows: 8048fa 14 LTM8048 APPLICATIONS INFORMATION θJA is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as still air although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. θJCbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical μModule converter, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJCtop is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical μModule converter are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJCboard is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the μModule converter and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two-sided, two-layer board. This board is described in JESD 51-9. Given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical operating condition of a μModule converter. Thus, none of them can be individually used to accurately predict the thermal performance of the product. Likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature vs load graphs given in the product’s data sheet. The only appropriate way to use the coefficients is when running a detailed thermal analysis, such as FEA, which considers all of the thermal resistances simultaneously. A graphical representation of these thermal resistances is given in Figure 2. The blue resistances are contained within the μModule converter, and the green are outside. The die temperature of the LTM8048 must be lower than the maximum rating of 125°C, so care should be taken in the layout of the circuit to ensure good heat sinking of the LTM8048. The bulk of the heat flow out of the LTM8048 is through the bottom of the module and the BGA pads into the printed circuit board. Consequently a poor printed circuit board design can cause excessive heating, resulting in impaired performance or reliability. Please refer to the PCB Layout section for printed circuit board design suggestions. JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD) JUNCTION-TO-CASE (TOP) RESISTANCE JUNCTION CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD (BOTTOM) RESISTANCE RESISTANCE AMBIENT BOARD-TO-AMBIENT RESISTANCE 8048 F02 μMODULE DEVICE Figure 2. 8048fa 15 LTM8048 TYPICAL APPLICATIONS VOUT2 Output Current vs VIN 3.3V Flyback Converter 340 LTM8048 VOUT1 RUN VOUT2 BIAS 4.7μF 8.66k ADJ1 SS 320 3.9V VOUT2 3.3V BYP 47μF ADJ2 294k 10μF OUTPUT CURRENT (mA) 2.2μF VIN ISOLATION BARRIER VIN 9V TO 15V 300 280 260 240 – VOUT GND 220 725VDC ISOLATION 8048 TA02 200 9 10 11 12 VIN (V) 14 13 15 8048 TA02b VOUT2 Output Current vs VIN 12V Flyback Converter with Low Noise Bypass 230 LTM8048 VOUT1 RUN VOUT2 BIAS 4.7μF 2.94k ADJ1 SS 13V 210 VOUT2 12V 0.01μF BYP 10μF ADJ2 10μF 56.2k OUTPUT CURRENT (mA) 5V VIN ISOLATION BARRIER VIN 5VDC TO 23VDC 250 170 150 130 110 90 VOUT– GND 190 70 8048 TA03 725VDC ISOLATION 50 5 10 15 VIN (V) 20 25 8048 TA03b Total Output Current vs VIN 500 3.3V and 2.5V Flyback Converter 450 2.2μF RUN BIAS 4.7μF 10k ADJ1 ISOLATION BARRIER VIN VOUT1 VOUT1 3.3V VOUT2 VOUT2 2.5V BYP 100μF ADJ2 GND 350 300 250 200 150 VOUT– 725VDC ISOLATION 400 10μF 487k SS OUTPUT CURRENT (mA) LTM8048 VIN 3.5VDC TO 32VDC 100 8048 TA04 0 8 16 VIN (V) 24 32 8048 TA04b 8048fa 16 LTM8048 PACKAGE DESCRIPTION Pin Assignment Table (Arranged by Pin Number) PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN B1 VOUT2 C1 D1 E1 GND F1 A1 VOUT2 A2 ADJ2 B2 BYP C2 D2 E2 GND F2 A3 VOUT– B3 VOUT– C3 D3 E3 GND F3 B4 VOUT– C4 D4 E4 GND F4 A4 VOUT– – B5 VOUT– C5 D5 E5 GND F5 A5 VOUT B6 VOUT1 C6 D6 E6 GND F6 A6 VOUT1 B7 VOUT1 C7 D7 E7 GND F7 A7 VOUT1 FUNCTION RUN GND GND GND GND PIN G1 G2 G3 G4 G5 G6 G7 FUNCTION PIN FUNCTION VIN H1 VIN VIN H2 VIN H3 GND H4 GND GND H5 BIAS GND H6 SS ADJ1 H7 GND PACKAGE PHOTO 8048fa 17 4 E 2.540 SUGGESTED PCB LAYOUT TOP VIEW 2.540 PACKAGE TOP VIEW 1.270 PIN “A1” CORNER 0.3175 0.000 0.3175 aaa Z 1.270 18 Y 4.445 3.175 1.905 0.635 0.000 0.635 1.905 3.175 4.445 D X 4.7625 4.1275 aaa Z SYMBOL A A1 A2 b b1 D E e F G aaa bbb ccc ddd eee NOM 4.92 0.60 4.32 0.78 0.63 11.25 9.0 1.27 8.89 7.62 DIMENSIONS 0.15 0.10 0.20 0.30 0.15 MAX 5.12 0.70 4.42 0.85 0.66 NOTES DETAIL B PACKAGE SIDE VIEW TOTAL NUMBER OF BALLS: 45 MIN 4.72 0.50 4.22 0.71 0.60 DETAIL A b1 0.27 – 0.37 SUBSTRATE ddd M Z X Y eee M Z DETAIL B MOLD CAP ccc Z A1 A2 A Z (Reference LTC DWG # 05-08-1869 Rev Ø) Øb (45 PLACES) 3.95 – 4.05 // bbb Z BGA Package 45-Lead (11.25mm × 9.00mm × 4.92mm) F e 7 5 4 3 2 1 DETAIL A PACKAGE BOTTOM VIEW 6 G H G F E D C B A PIN 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL COMPONENT PIN “A1” BGA 45 0510 REV Ø PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX μModule 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JESD MS-028 AND JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 b 3 SEE NOTES LTM8048 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 8048fa 3.810 3.810 LTM8048 REVISION HISTORY REV DATE DESCRIPTION A 6/12 Added storage temperature range PAGE NUMBER 2 Clarify VOUT2 and ADJ1 pin function description 8 Clarify RADJ2 equation 13 Updated Related Parts table 20 8048fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTM8048 TYPICAL APPLICATION Total Output Current vs VIN 400 5V Flyback Converter with Low Noise Bypass 380 LTM8048 VIN RUN BIAS 4.7μF 6.19k ADJ1 SS VOUT1 ISOLATION BARRIER 2.2μF 5.7V 360 VOUT2 5V VOUT2 0.01μF BYP 22μF ADJ2 162k 10μF 340 320 300 280 260 240 VOUT– GND OUTPUT CURRENT (mA) VIN 15VDC TO 30VDC 220 725VDC ISOLATION 8048 TA05 200 15 20 25 30 VIN (V) 8048 TA05b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM8031 Ultralow EMI 1A μModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 10V LTM8032 Ultralow EMI 2A μModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 10V LTM8033 Ultralow EMI 3A μModule Regulator EN55022 Class B Compliant, 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 24V LTM4612 Ultralow EMI 5A μModule Regulator EN55022 Class B Compliant, 5V ≤ VIN ≤ 36V; 3.3V ≤ VOUT ≤ 15V LTM8061 Li-Ion/Polymer μModule Battery Charger 4.95V ≤ VIN ≤ 32V, 2A Charge Current, 1-Cell and 2-Cell, 4.1V or 4.2V per Cell LTM4613 Ultralow EMI 8A μModule Regulator EN55022 Class B Compliant, 5V ≤ VIN ≤ 36V; 3.3V ≤ VOUT ≤ 15V LTM8047 725VDC Isolated μModule Converter 3.1V ≤ VIN ≤ 32V; 2.5V ≤ VOUT ≤ 12V 8048fa 20 Linear Technology Corporation LT 0612 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2011