AD AD9627-11 11-bit, 105 msps/150 msps, 1.8 v dual analog-to-digital converter Datasheet

11-Bit, 105 MSPS/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9627-11
FUNCTIONAL BLOCK DIAGRAM
B
SO
APPLICATIONS
O
Communications
Diversity radio systems
Multimode digital receivers (3G)
GSM, EDGE, WCDMA, CDMA2000,
WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
SDIO/ SCLK/
DCS DFS CSB
FD(0:3)A
FD BITS/THRESHOLD
DETECT
DRVDD
SPI
PROGRAMMING DATA
VIN+A
SHA
ADC
VIN–A
TE
SIGNAL
MONITOR
SENSE
CML
DIVIDE
1 TO 8
REF
SELECT
VIN–B
SHA
ADC
VIN+B
SIGNAL MONITOR
DATA
AD9627-11
MULTICHIP
SYNC
AGND
SYNC
FD BITS/THRESHOLD
DETECT
FD(0:3)B
CLK–
DCO
GENERATION
DUTY CYCLE
STABILIZER
RBIAS
D0A
CLK+
CMOS
OUTPUT BUFFER
VREF
D10A
DCOA
DCOB
D10B
D0B
SIGNAL MONITOR
INTERFACE
SMI
SMI
SMI DRGND
SDFS SCLK/ SDO/
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
07054-001
AVDD DVDD
LE
SNR = 65.8 dBc (66.8 dBFS) to 70 MHz @ 105 MSPS
SFDR = 85 dBc to 70 MHz @ 105 MSPS
Low power: 600 mW @ 105 MSPS
SNR = 65.7 dBc (66.7 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
CMOS
OUTPUT BUFFER
FEATURES
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Integrated dual, 11-bit, 105 MSPS/150 MSPS ADC.
Fast overrange detect and signal monitor with serial output.
Signal monitor block with dedicated serial output mode.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
Pin compatibility with the AD9640, AD9627, and AD9600
for a simple migration from 11 bits to 14 bits, 12 bits, or
10 bits.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD9627-11
TABLE OF CONTENTS
RMS/MS Magnitude Mode ....................................................... 33
Applications ....................................................................................... 1
Threshold Crossing Mode ......................................................... 34
Functional Block Diagram .............................................................. 1
Additional Control Bits ............................................................. 34
Product Highlights ........................................................................... 1
DC Correction ............................................................................ 34
Revision History ............................................................................... 3
Signal Monitor SPORT Output ................................................ 35
General Description ......................................................................... 4
Built-In Self-Test (BIST) and Output Test .................................. 36
Specifications..................................................................................... 5
Built-In Self-Test (BIST) ............................................................ 36
ADC DC Specifications—AD9627-11-105/AD9627-11-150. 5
Output Test Modes ..................................................................... 36
ADC AC Specifications—AD9627-11-105/AD9627-11-150 . 6
Channel/Chip Synchronization .................................................... 37
Digital Specifications ................................................................... 7
Serial Port Interface (SPI) .............................................................. 38
Switching Specifications—AD9627-11-105/AD9627-11-150 9
Configuration Using the SPI ..................................................... 38
Timing Specifications ................................................................ 10
Hardware Interface..................................................................... 38
Absolute Maximum Ratings.......................................................... 12
Configuration Without the SPI ................................................ 39
Thermal Characteristics ............................................................ 12
SPI Accessible Features .............................................................. 39
LE
TE
Features .............................................................................................. 1
Memory Map .................................................................................. 40
Pin Configurations and Function Descriptions ......................... 13
Reading the Memory Map Register Table............................... 40
Equivalent Circuits ......................................................................... 17
Memory Map Register Table ..................................................... 41
Typical Performance Characteristics ........................................... 18
Memory Map Register Descriptions ........................................ 44
Theory of Operation ...................................................................... 23
Applications Information .............................................................. 47
B
SO
ESD Caution ................................................................................ 12
Design Guidelines ...................................................................... 47
Analog Input Considerations.................................................... 23
Evaluation Board ............................................................................ 48
Voltage Reference ....................................................................... 25
Power Supplies ............................................................................ 48
Clock Input Considerations ...................................................... 26
Input Signals................................................................................ 48
Power Dissipation and Standby Mode ..................................... 28
Output Signals ............................................................................ 48
Digital Outputs ........................................................................... 28
Default Operation and Jumper Selection Settings ................. 49
Timing .......................................................................................... 29
Alternative Clock Configurations ............................................ 49
ADC Overrange and Gain Control .............................................. 30
Alternative Analog Input Drive Configuration...................... 50
Fast Detect Overview ................................................................. 30
Schematics ................................................................................... 51
O
ADC Architecture ...................................................................... 23
ADC Fast Magnitude ................................................................. 30
Evaluation Board Layouts ......................................................... 61
ADC Overrange (OR) ................................................................ 31
Bill of Materials ........................................................................... 69
Gain Switching ............................................................................ 31
Outline Dimensions ....................................................................... 71
Signal Monitor ................................................................................ 33
Ordering Guide .......................................................................... 71
Peak Detector Mode ................................................................... 33
Rev. B | Page 2 of 72
AD9627-11
REVISION HISTORY
O
B
SO
10/07—Revision 0: Initial Version
LE
9/09—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 9
Changes to Figure 3.........................................................................11
Changes to Figure 11, Figure 12, and Figure 14 ..........................17
Changes to Table 12 ........................................................................29
Changes to Configuration Using the SPI Section .......................38
Change to Table 22 ..........................................................................43
Change to Signal Monitor Period (Register 0x113
to Register 0x115) Section..............................................................46
Updated Outline Dimensions ........................................................71
TE
5/10—Rev. A to Rev. B
Deleted CP-64-3 Package .................................................. Universal
Added CP-64-6 Package .................................................... Universal
Changed AD9627BCPZ11-150 to AD9627-11-150 and
AD9627BCPZ11-105 to AD9627-11-105 Throughout................ 5
Changes to Figure 6.........................................................................13
Changes to Figure 7.........................................................................15
Updated Outline Dimensions ........................................................71
Changes to Ordering Guide ...........................................................71
Rev. B | Page 3 of 72
AD9627-11
GENERAL DESCRIPTION
The AD9627-11 is a dual, 11-bit, 105 MSPS/150 MSPS analog-todigital converter (ADC). The AD9627-11 is designed to support
communications applications where low cost, small size, and
versatility are desired.
the programmable threshold, the coarse upper threshold indicator
goes high. Because this threshold indicator has very low latency,
the user can quickly turn down the system gain to avoid an overrange condition.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold analog
input amplifiers supporting a variety of user-selectable input
ranges. An integrated voltage reference eases design considerations.
A duty cycle stabilizer is provided to compensate for variations
in the ADC clock duty cycle, allowing the converters to maintain
excellent performance.
The second AGC-related function is the signal monitor. This block
allows the user to monitor the composite magnitude of the
incoming signal, which aids in setting the gain to optimize the
dynamic range of the overall system.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-bit
SPI-compatible serial interface.
The AD9627-11 is available in a 64-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C.
O
B
SO
LE
In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits
of the ADC with very low latency. If the input signal level exceeds
TE
The AD9627-11 has several functions that simplify the automatic
gain control (AGC) function in the system receiver. The fast detect
feature allows fast overrange detection by outputting four bits of
input level information with very short latency.
The ADC output data can be routed directly to the two external
11-bit output ports. These outputs can be set from 1.8 V to 3.3 V
CMOS or 1.8 V LVDS.
Rev. B | Page 4 of 72
AD9627-11
SPECIFICATIONS
ADC DC SPECIFICATIONS—AD9627-11-105/AD9627-11-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 1.
25°C
25°C
Full
Full
Full
25°C
−3.6
AD9627-11-105
Typ
Max
Guaranteed
±0.3
±0.7
−2.2
−1.0
±0.3
±0.1
±0.5
±0.2
±0.3
±0.2
O
Min
11
−4.3
±0.7
±0.75
±15
±95
±5
7
B
SO
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
Supply Current
IAVDD1, 3
IDVDD1, 3
IDRVDD1 (3.3 V CMOS)
IDRVDD1 (1.8 V CMOS)
IDRVDD1 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD = 1.8 V)
Sine Wave Input1 (DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Full
Full
Full
Full
25°C
Full
25°C
Min
11
AD9627-11-150
Typ
Max
±16
Unit
Bits
Guaranteed
±0.2
±0.6
−3.0
−1.7
±0.4
±0.1
±0.7
±0.3
% FSR
% FSR
LSB
LSB
LSB
LSB
±0.2
±0.2
% FSR
% FSR
TE
Integral Nonlinearity (INL)1
Temperature
Full
LE
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
±0.7
±0.7
±15
±95
±5
7
ppm/°C
ppm/°C
±16
mV
mV
25°C
0.15
0.15
LSB rms
Full
Full
Full
2
8
6
2
8
6
V p-p
pF
kΩ
Full
Full
Full
1.7
1.7
1.7
1.8
3.3
1.8
Full
Full
Full
Full
Full
310
34
34
16
44
Full
Full
Full
Full
Full
600
645
730
68
2.5
1
1.9
3.6
1.9
365
650
6
1.7
1.7
1.7
1.8
3.3
1.8
419
50
42
29
46
820
895
1000
77
2.5
1.9
3.6
1.9
495
890
6
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
3
The maximum limit applies to the combination of IAVDD and IDVDD currents.
4
Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
2
Rev. B | Page 5 of 72
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
AD9627-11
ADC AC SPECIFICATIONS—AD9627-11-105/AD9627-11-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 2.
25°C
25°C
Full
25°C
25°C
fIN = 140 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.3 MHz
fIN = 70 MHz
O
fIN = 140 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 29.1 MHz, 32.1 MHz (−7 dBFS )
fIN = 169.1 MHz, 172.1 MHz (−7 dBFS )
CROSSTALK2
ANALOG INPUT BANDWIDTH
1
2
AD9627-11-105
Typ
Max
Min
AD9627-11-150
Typ
Max
65.9
65.8
65.8
65.7
65.3
65.5
65.2
65.9
65.7
65.7
65.6
64.9
65.4
65.1
dB
dB
dB
dB
dB
64.4
65.5
65.1
Unit
dB
dB
dB
dB
dB
65.0
65.6
65.2
25°C
25°C
25°C
25°C
10.8
10.8
10.8
10.7
10.8
10.8
10.7
10.7
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−87
−85
−86.5
−84
−84
−83
−83.5
−77
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
87
85
86.5
84
B
SO
fIN = 140 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.3 MHz
fIN = 70 MHz
25°C
25°C
Full
25°C
25°C
Min
TE
fIN = 140 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.3 MHz
fIN = 70 MHz
Temperature
LE
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz
fIN = 70 MHz
−73
73
−72
dBc
dBc
dBc
dBc
dBc
72
84
83
83.5
77
25°C
25°C
Full
25°C
25°C
−92
−88
−92
−88
−86
−86
−86
−86
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
85
82
−95
650
85
82
−95
650
dBc
dBc
dB
MHz
−82
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
Rev. B | Page 6 of 72
−80
AD9627-11
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 3.
Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
1.2
0.2
6
GND − 0.3
AVDD + 1.6
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
4
8
10
12
Full
Full
Full
Full
Full
Full
Full
Full
B
SO
O
Typ
Max
TE
Temperature
LE
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
GND − 0.3
1.2
0
−10
−10
8
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Full
Full
Full
Full
1.22
0
−90
−10
Rev. B | Page 7 of 72
CMOS
1.2
AVDD + 1.6
3.6
0.8
+10
+10
4
10
12
Unit
V
V p-p
V
V
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
3.6
0.6
+10
132
V
V
μA
μA
kΩ
pF
3.6
0.6
−135
+10
V
V
μA
μA
kΩ
pF
3.6
0.6
+10
128
V
V
μA
μA
kΩ
pF
3.6
0.6
−134
+10
V
V
μA
μA
26
2
26
2
26
5
AD9627-11
Full
Full
3.29
3.25
Pull up.
Pull down.
Typ
26
5
Full
Full
Full
Full
Full
Full
0.2
0.05
TE
Full
Full
Rev. B | Page 8 of 72
Max
1.79
1.75
250
1.15
150
1.15
Unit
kΩ
pF
V
V
Full
Full
B
SO
2
Min
O
1
Temperature
Full
Full
LE
Parameter
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
350
1.25
200
1.25
V
V
V
V
0.2
0.05
V
V
450
1.35
280
1.35
mV
V
mV
V
AD9627-11
SWITCHING SPECIFICATIONS—AD9627-11-105/AD9627-11-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 4.
Temperature
Min
AD9627-11-105
Typ
Max
Full
Full
Full
Full
Full
2.85
4.28
1.6
0.8
Full
Full
Full
Full
O
1
2
3
Full
Full
Full
Full
Full
Full
Full
AD9627-11-150
Typ
Max
105
105
4.75
4.75
6.65
5.23
MHz
150
150
MSPS
MSPS
ns
3.33
3.33
4.66
3.66
ns
ns
ns
ns
20
10
6.66
2.0
3.0
1.6
0.8
Unit
625
TE
20
10
9.5
LE
Full
Full
Full
Full
Full
Full
Full
Min
625
2.2
3.8
4.5
5.0
5.25
4.25
6.4
6.8
2.2
3.8
4.5
5.0
3.83
2.83
6.4
6.8
ns
ns
ns
ns
2.4
4.0
5.2
5.6
5.15
4.35
6.9
7.3
2.4
4.0
5.2
5.6
3.73
2.93
6.9
7.3
ns
ns
ns
ns
3.0
5.2
3.7
6.4
12
12/12.5
4.4
7.6
3.0
4.8
3.8
5.9
12
12/12.5
4.5
7.3
ns
ns
Cycles
Cycles
B
SO
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled1
DCS Disabled1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode, DCS Enabled
Divide-by-3 Mode Through Divide-by8 Mode, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
1.0
0.1
350
2
Conversion rate is the clock rate after the divider.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors.
Rev. B | Page 9 of 72
1.0
0.1
350
3
ns
ps rms
μs
Cycles
AD9627-11
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Test Conditions/Comments
Min
Typ
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Unit
ns
ns
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
3.2
−0.4
−0.4
TE
SPORT TIMING REQUIREMENTS
tCSSCLK
tSSCLKSDO
tSSCLKSDFS
0.24
0.40
LE
tDIS_SDIO
Max
B
SO
Timing Diagrams
4.5
0
0
N+2
N+1
N+3
N
N+4
tA
N+8
N+5
N+6
N+7
tCLK
CLK+
CLK–
N – 13
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
CH A/CH B FAST
DETECT
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
O
CH A/CH B DATA
tS
tH
tDCO
tCLK
DCOA/DCOB
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
Rev. B | Page 10 of 72
07054-002
tPD
6.2
0.4
0.4
ns
ns
ns
AD9627-11
N+1
N+2
N+3
N
N+4
N+8
tA
N+5
N+6
N+7
tCLK
CLK+
CLK–
tPD
A
CH A/CH B FAST
DETECT
A
B
N – 13
B
N–7
A
B
N – 12
A
B
N–6
A
B
N – 11
A
B
N–5
A
B
N – 10
A
B
N–4
A
B
N–9
A
B
A
B
N–8
A
B
A
B
A
N–7
A
B
B
A
N–6
A
B
B
N–5
A
B
A
N–4
A
TE
CH A/CH B DATA
N–3
N–2
tDCO
N
N+1
N+2
tCLK
07054-003
DCO+
N–1
DCO–
LE
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
tSSYNC
B
SO
SYNC
tHSYNC
07054-004
CLK+
Figure 4. SYNC Input Timing Requirements
CLK+
CLK–
tCSSCLK
SMI SCLK
tSSCLKSDO
O
tSSCLKSDFS
SMI SDO
DATA
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)
Rev. B | Page 11 of 72
DATA
07054-005
SMI SDFS
AD9627-11
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Rating
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-6)
1
Airflow
Velocity
(m/s)
0
1.0
2.0
−0.3 V to DRVDD + 0.3 V
θJA1, 2
18.8
16.5
15.8
θJC1, 3
0.6
θJB1, 4
6.0
Unit
°C/W
°C/W
°C/W
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown, airflow improves heat dissipation, which
reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
LE
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
ESD CAUTION
−0.3 V to DRVDD + 0.3 V
B
SO
Parameter
ELECTRICAL
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
D0A/D0B through D10A/D10B to
DRGND
FD0A/FD0B through FD3A/FD3B to
DRGND
DCOA/DCOB to DRGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
TE
Table 6.
−40°C to +85°C
150°C
−65°C to +150°C
O
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 12 of 72
AD9627-11
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
D2B
D1B
D0B (LSB)
DNC
DNC
DNC
DVDD
FD3B
FD2B
FD1B
FD0B
SYNC
CSB
CLK–
CLK+
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9627-11
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
TE
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
07054-006
LE
D2A
D3A
D4A
DRGND
DRVDD
D5A
D6A
DVDD
D7A
D8A
D9A
D10A (MSB)
FD0A
FD1A
FD2A
FD3A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B (MSB)
DCOB
DCOA
DNC
DNC
DNC
D0A (LSB)
D1A
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Type
Description
O
B
SO
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46
AVDD
0
AGND
12 to 14, 58 to 60 DNC
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
ADC Fast Detect Outputs
29
FD0A
30
FD1A
31
FD2A
32
FD3A
53
FD0B
54
FD1B
55
FD2B
56
FD3B
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Output
Output
Output
Output
Output
Output
Channel A Fast Detect Indicator. See Table 14 for details.
Channel A Fast Detect Indicator. See Table 14 for details.
Channel A Fast Detect Indicator. See Table 14 for details.
Channel A Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Rev. B | Page 13 of 72
AD9627-11
Description
Input
Digital Synchronization Pin. Slave mode only.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel A Data Clock Output.
Channel B Data Clock Output.
Input
Input/Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Input/Output
Output
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
LE
TE
Type
O
B
SO
Pin No.
Mnemonic
Digital Input
52
SYNC
Digital Outputs
15
D0A (LSB)
16
D1A
17
D2A
18
D3A
19
D4A
22
D5A
23
D6A
25
D7A
26
D8A
27
D9A
28
D10A (MSB)
61
D0B (LSB)
62
D1B
63
D2B
2
D3B
3
D4B
4
D5B
5
D6B
6
D7B
7
D8B
8
D9B
9
D10B (MSB)
11
DCOA
10
DCOB
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Signal Monitor Port
33
SMI SDO/OEB
35
SMI SDFS
34
SMI SCLK/PDWN
Rev. B | Page 14 of 72
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
DNC
DNC
FD3+
FD3–
FD2+
FD2–
DVDD
FD1+
FD1–
FD0+
FD0–
SYNC
CSB
CLK–
CLK+
AD9627-11
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9627-11
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
TE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LE
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
07054-007
D4+
D5–
D5+
DRGND
DRVDD
D6–
D6+
DVDD
D7–
D7+
D8–
D8+
D9–
D9+
D10– (MSB)
D10+ (MSB)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
DNC
DNC
DNC
DNC
D0– (LSB)
D0+ (LSB)
D1–
D1+
DCO–
DCO+
D2–
D2+
D3–
D3+
D4–
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Type
Description
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 14 for details.
Input
Digital Synchronization Pin. Slave mode only.
O
B
SO
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46 AVDD
0
AGND
2, 3, 4, 5, DNC
62, 63
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
ADC Fast Detect Outputs
54
FD0+
53
FD0−
56
FD1+
55
FD1−
59
FD2+
58
FD2−
61
FD3+
60
FD3−
Digital Input
52
SYNC
Rev. B | Page 15 of 72
AD9627-11
Description
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3 —True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
LE
TE
Type
B
SO
Pin No.
Mnemonic
Digital Outputs
7
D0+ (LSB)
6
D0− (LSB)
9
D1+
8
D1−
13
D2+
12
D2−
15
D3+
14
D3−
17
D4+
16
D4−
19
D5+
18
D5−
23
D6+
22
D6−
26
D7+
25
D7−
28
D8+
27
D8−
30
D9+
29
D9−
32
D10+ (MSB)
31
D10− (MSB)
11
DCO+
10
DCO−
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Signal Monitor Port
33
SMI SDO/OEB
35
SMI SDFS
34
SMI SCLK/PDWN
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Input/Output
Output
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
O
Input
Input/Output
Input
Rev. B | Page 16 of 72
AD9627-11
EQUIVALENT CIRCUITS
DVDD
VIN
1kΩ
SCLK/DFS
07054-012
07054-008
26kΩ
Figure 8. Equivalent Analog Input Circuit
Figure 12. Equivalent SCLK/DFS Input Circuit
TE
AVDD
1kΩ
1.2V
10kΩ
CLK+
Figure 9. Equivalent Clock Input Circuit
Figure 13. Equivalent SENSE Circuit
CSB
DVDD
26kΩ
DVDD
1kΩ
07054-010
B
SO
DRVDD
LE
07054-009
CLK–
07054-014
10kΩ
07054-013
SENSE
DRGND
Figure 10. Digital Output
Figure 14. Equivalent CSB Input Circuit
O
DRVDD
AVDD
DVDD
26kΩ
DVDD
VREF
1kΩ
SDIO/DCS
6kΩ
07054-011
07054-015
DRVDD
Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit
Figure 15. Equivalent VREF Circuit
Rev. B | Page 17 of 72
AD9627-11
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential
input, VIN = −1.0 dBFS; and 64k sample, TA = 25°C, unless otherwise noted.
0
0
150MSPS
2.3MHz @ –1dBFS
SNR = 65.8dB (66.8dBFS)
ENOB = 10.8 BITS
SFDR = 86.5dBc
–20
–40
–60
SECOND
HARMONIC
THIRD
HARMONIC
–80
–80
THIRD
HARMONIC
SECOND
HARMONIC
–100
0
10
20
30
40
50
60
–120
07054-016
–120
70
FREQUENCY (MHz)
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 19. AD9627-11-150 Single-Tone FFT with fIN = 140 MHz
LE
Figure 16. AD9627-11-150 Single-Tone FFT with fIN = 2.3 MHz
0
150MSPS
30.3MHz @ –1dBFS
SNR = 65.7dB (66.7dBFS)
ENOB = 10.8 BITS
SFDR = 85.7dBc
THIRD
HARMONIC
–80
–100
–120
0
10
20
30
40
50
SECOND
HARMONIC
60
70
FREQUENCY (MHz)
O
THIRD
HARMONIC
–80
20
30
40
50
60
70
Figure 20. AD9627-11-150 Single-Tone FFT with fIN = 220 MHz
0
AMPLITUDE (dBFS)
–60
10
FREQUENCY (MHz)
150MSPS
337MHz @ –1dBFS
SNR = 64.6dB (65.4dBFS)
ENOB = 10.6 BITS
SFDR = 76.0dBc
–20
–40
THIRD
HARMONIC
SECOND
HARMONIC
–80
0
150MSPS
70MHz @ –1dBFS
SNR = 65.7dB (66.7dBFS)
ENOB = 10.8 BITS
SFDR = 84.0dBc
–20
–60
–120
Figure 17. AD9627-11-150 Single-Tone FFT with fIN = 30.3 MHz
0
–40
–100
07054-017
–60
B
SO
–40
–20
AMPLITUDE (dBFS)
–20
150MSPS
220MHz @ –1dBFS
SNR = 65.2dB (66.2dBFS)
ENOB = 10.7 BITS
SFDR = 79.0dBc
07054-020
0
–40
–60
THIRD
HARMONIC
SECOND
HARMONIC
–80
SECOND
HARMONIC
–100
–120
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
07054-018
–100
Figure 18. AD9627-11-150 Single-Tone FFT with fIN = 70 MHz
–120
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 21. AD9627-11-150 Single-Tone FFT with fIN = 337 MHz
Rev. B | Page 18 of 72
07054-021
AMPLITUDE (dBFS)
–60
07054-019
–100
AMPLITUDE (dBFS)
–40
TE
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
150MSPS
140MHz @ –1dBFS
SNR = 65.5dB (66.5dBFS)
ENOB = 10.7 BITS
SFDR = 84.1dBc
AD9627-11
0
0
150MSPS
440MHz @ –1dBFS
SNR = 63.8dB (64.5dBFS)
ENOB = 10.2 BITS
SFDR = 71.0dBc
–20
AMPLITUDE (dBFS)
–40
SECOND
HARMONIC
–60
THIRD
HARMONIC
–80
–80
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 22. AD9627-11-150 Single-Tone FFT with fIN = 440 MHz
–120
0
10
20
30
40
50
FREQUENCY (MHz)
07054-025
0
Figure 25. AD9627-11-105 Single-Tone FFT with fIN = 72 MHz
0
105MSPS
2.3MHz @ –1dBFS
SNR = 65.9dB (66.9dBFS)
ENOB = 10.8 BITS
SFDR = 89.0dBc
AMPLITUDE (dBFS)
–40
–60
SECOND
HARMONIC
–100
–120
0
B
SO
THIRD
HARMONIC
10
20
30
40
50
FREQUENCY (MHz)
–60
THIRD
HARMONIC
–80
SECOND
HARMONIC
10
20
30
40
50
FREQUENCY (MHz)
Figure 26. AD9627-11-105 Single-Tone FFT with fIN = 141 MHz
0
105MSPS
337MHz @ –1dBFS
SNR = 64.5dB (65.5dBFS)
ENOB = 10.6 BITS
SFDR = 79.0dBc
–20
AMPLITUDE (dBFS)
O
–40
THIRD
HARMONIC
–80
0
105MSPS
30.3MHz @ –1dBFS
SNR = 65.8dB (66.8dBFS)
ENOB = 10.8 BITS
SFDR = 86dBc
–20
–60
–120
Figure 23. AD9627-11-105 Single-Tone FFT with fIN = 2.3 MHz
0
–40
–100
07054-023
–80
–20
LE
–20
105MSPS
141MHz @ –1dBFS
SNR = 65.6dB (66.6dBFS)
ENOB = 10.8 BITS
SFDR = 83dBc
07054-026
0
AMPLITUDE (dBFS)
SECOND
HARMONIC
THIRD
HARMONIC
TE
–120
–40
–60
THIRD
HARMONIC
SECOND
HARMONIC
–80
SECOND
HARMONIC
–100
–100
–120
0
10
20
30
40
50
FREQUENCY (MHz)
07054-024
AMPLITUDE (dBFS)
–60
–100
07054-022
–100
–40
Figure 24. AD9627-11-105 Single-Tone FFT with fIN = 30.3 MHz
–120
0
10
20
30
40
50
FREQUENCY (MHz)
Figure 27. AD9627-11-105 Single-Tone FFT with fIN = 337 MHz
Rev. B | Page 19 of 72
07054-027
AMPLITUDE (dBFS)
–20
105MSPS
72MHz @ –1dBFS
SNR = 65.8dB (66.8dBFS)
ENOB = 10.8 BITS
SFDR = 85dBc
AD9627-11
120
95
SFDR = +85°C
90
85
SFDR (dBFS)
80
SNR (dBFS)
40
SFDR = –40°C
75
70
65
85dB REFERENCE LINE
20
SNR = +25°C
SNR = +85°C
SNR = –40°C
60
SNR (dBc)
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
55
0
250
300
350
400
40
SFDR (dBc)
450
0.5
–2.5
0.4
LE
GAIN ERROR (%FSR)
SNR (dBFS)
–3.0
0.3
GAIN
–3.5
0.2
OFFSET
85dB REFERENCE LINE
B
SO
SNR/SFDR (dBc AND dBFS)
200
–2.0
SFDR (dBFS)
20
150
Figure 31. AD9627-11-150 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 1 V p-p Full Scale
100
60
100
INPUT FREQUENCY (MHz)
Figure 28. AD9627-11-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 2.4 MHz
80
50
TE
–80
07054-028
0
–90
07054-031
SFDR (dBc)
80
–4.0
OFFSET ERROR (%FSR)
60
SFDR = +25°C
SNR/SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
100
0.1
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
–4.5
–40
90
SFDR = –40°C
75
70
65
100
150
200
250
SFDR (dBc)
IMD3 (dBc)
–40
–60
SFDR (dBFS)
–80
IMD3 (dBFS)
300
350
400
450
INPUT FREQUENCY (MHz)
Figure 30. AD9627-11-150 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 2 V p-p Full Scale
–120
–90
07054-030
50
80
–100
55
0
60
–20
SNR = +25°C
SNR = +85°C
SNR = –40°C
60
40
0
SFDR/IMD3 (dBc AND dBFS)
O
SNR/SFDR (dBc)
SFDR = +25°C
80
20
Figure 32. AD9627-11-150 Gain and Offset vs. Temperature
SFDR = +85°C
85
0
TEMPERATURE (°C)
Figure 29. AD9627-11-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 98.12 MHz
95
0
–20
07054-032
–70
–78
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
07054-033
–80
07054-029
SNR (dBc)
0
–90
Figure 33. AD9627-11-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
Rev. B | Page 20 of 72
AD9627-11
0
0
–20
SFDR (dBc)
AMPLITUDE (dBFS)
SFDR/IMD3 (dBc AND dBFS)
–20
150MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 83.8dBc (90.8dBFS)
–40
IMD3 (dBc)
–60
SFDR (dBFS)
–80
–100
–40
–60
–80
–100
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
Figure 34. AD9627-11-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
0
0
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 37. AD9627-11-150 Two-Tone FFT with fIN1 = 169.1 MHz and
fIN2 = 172.1 MHz
NPR = 58.4dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz
AMPLITUDE (dBFS)
LE
–20
0
15.36
30.72
46.08
61.44
FREQUENCY (MHz)
–80
–100
–120
07054-035
–120
B
SO
–80
–60
0
–60
–80
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 36. AD9627-11-150 Two-Tone FFT with fIN1 = 29.1 MHz
and fIN2 = 32.1 MHz
70
SFDR - SIDE A
80
SNR - SIDE B
70
SNR - SIDE A
50
07054-036
10
60
90
60
0
50
SFDR - SIDE B
–100
–120
40
100
SNR/SFDR (dBc)
O
–40
30
Figure 38. AD9627-11 Noise Power Ratio (NPR)
150MSPS
29.1MHz @ –7dBFS
32.1MHz @ –7dBFS
SFDR = 86.1dBc (93.1dBFS)
–20
20
FREQUENCY (MHz)
Figure 35. AD9627-11-150, Two 64k WCDMA Carriers
with fIN = 170 MHz, fS = 122.88 MSPS
0
10
07054-038
–60
–40
0
25
50
75
100
SAMPLE RATE (MSPS)
125
150
07054-039
–40
–100
AMPLITUDE (dBFS)
10
0
–20
AMPLITUDE (dBFS)
–120
07054-037
–78
TE
–120
–90
07054-034
IMD3 (dBFS)
Figure 39. AD9627-11-150 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 2.3 MHz
Rev. B | Page 21 of 72
AD9627-11
12
100
0.15 LSB rms
95
90
8
SNR/SFDR (dBc)
NUMBER OF HITS (1M)
10
6
4
SFDR DCS ON
85
80
SFDR DCS OFF
75
SNR DCS ON
70
2
65
N–1
N
N+1
N+2
N+3
OUTPUT CODE
40
60
DUTY CYCLE (%)
Figure 40. AD9627-11 Grounded Input Histogram
Figure 43. AD9627-11 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz
0.2
95
SFDR
90
SNR/SFDR (dBc)
LE
85
0
80
75
70
0
256
512
768
1024
1280
1536
1792
2048
OUTPUT CODE
Figure 41. AD9627-11 INL with fIN = 10.3 MHz
0.15
0.10
O
0.05
0
–0.05
–0.15
0
256
512
768
1024
1280
1536
1792
OUTPUT CODE
2048
07054-042
–0.10
Figure 42. AD9627-11 DNL with fIN = 10.3 MHz
Rev. B | Page 22 of 72
SNR
65
60
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
INPUT COMMON-MODE VOLTAGE (V)
Figure 44. AD9627-11 SNR/SFDR vs. Input Common Mode (VCM)
with fIN = 30 MHz
07054-044
–0.2
B
SO
–0.1
07054-041
INL ERROR (LSB)
0.1
DNL ERROR (LSB)
80
TE
N–2
07054-040
N–3
60
20
07054-043
SNR DCS OFF
0
AD9627-11
THEORY OF OPERATION
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9627-11 are accomplished
using a 3-bit SPI-compatible serial interface.
B
SO
The AD9627-11 architecture consists of a dual front-end sampleand-hold amplifier (SHA), followed by a pipelined, switchedcapacitor ADC. The quantized outputs from each stage are
combined into a final 11-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
O
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, corrects errors, and passes
the data to the output buffers. The output buffers are powered from
a separate supply, allowing adjustment of the output voltage swing.
During power-down, the output buffers go into a high impedance
state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9627-11 is a differential switchedcapacitor SHA that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 45). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
CH
CS
VIN+
CPIN, PAR
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
S
S
LE
ADC ARCHITECTURE
In intermediate frequency (IF) undersampling applications,
any shunt capacitors should be reduced. In combination with
the driving source impedance, the shunt capacitors limit the
input bandwidth. See Application Note AN-742, Frequency
Domain Response of Switched-Capacitor ADCs; Application
Note AN-827, A Resonant Approach to Interfacing Amplifiers
to Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject.
S
H
CS
VIN–
CPIN, PAR
CH
S
07054-045
In nondiversity applications, the AD9627-11 can be used as a baseband or direct downconversion receiver, where one ADC is
used for I input data and the other is used for Q input data.
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
TE
The AD9627-11 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the
same carrier but from two separate antennae. The ADCs can also
be operated with independent analog inputs. The user can sample
any fS/2 frequency segment from dc to 200 MHz, using appropriate
low-pass or band-pass filtering at the ADC inputs with little loss
in ADC performance. Operation to 450 MHz analog input is
permitted but occurs at the expense of increased ADC noise and
distortion.
Figure 45. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 ×
VREF.
Input Common Mode
The analog inputs of the AD9627-11 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.55 × AVDD
is recommended for optimum performance, but the device
functions over a wider range with reasonable performance
(see Figure 44). An on-board common-mode voltage reference
is included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9627-11
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the ADC.
Rev. B | Page 23 of 72
AD9627-11
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential driver.
An example is shown in Figure 50. See the AD8352 data sheet
for more information.
The output common-mode voltage of the AD8138 is easily set
with the CML pin of the AD9627-11 (see Figure 46), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
499Ω
R
49.9Ω
VIN+
In any configuration, the value of Shunt Capacitor C is dependent
on the input frequency and source impedance and may need to
be reduced or removed. Table 10 displays recommended values to
set the RC network. However, these values are dependent on the
input signal and should be used only as a starting guide.
AVDD
499Ω
R
CML
VIN–
07054-046
523Ω
AD9627-11
C
AD8138
0.1µF
499Ω
Table 10. Example RC Network
Figure 46. Differential Input Configuration Using the AD8138
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 47. To bias the
analog input, the CML voltage can be connected to the center
tap of the secondary winding of the transformer.
VIN+
49.9Ω
C
Single-Ended Input Configuration
AD9627-11
R
A single-ended input can provide adequate performance in cost
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 48 shows a typical
single-ended input configuration.
CML
07054-047
LE
VIN–
0.1µF
Figure 47. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
B
SO
0.1µF
AVDD
10µF
1kΩ
R
49.9Ω
1V p-p
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9627-11. For applications
where SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 49).
0.1µF
0.1µF
AD9627-11
C
1kΩ
10µF
VIN+
1kΩ
AVDD
R
VIN–
1kΩ
Figure 48. Single-Ended Input Configuration
0.1µF
R
VIN+
2V p-p
25Ω
S
P
25Ω
0.1µF
AD9627-11
C
0.1µF
R
CML
VIN–
07054-049
S
O
PA
Figure 49. Differential Double Balun Input Configuration
VCC
0Ω
16
0.1µF
8, 13
1
11
0.1µF
CD
RD
RG
3
200Ω
AD8352
10
4
5
ANALOG INPUT
0.1µF
0Ω
R
VIN+
2
C
0.1µF
200Ω
R
AD9627-11
VIN–
CML
14
0.1µF
0.1µF
Figure 50. Differential Input Configuration Using the AD8352
Rev. B | Page 24 of 72
07054-050
0.1µF
ANALOG INPUT
C Differential (pF)
15
5
5
Open
TE
R
2V p-p
R Series
(Ω Each)
33
33
15
15
Frequency Range (MHz)
0 to 70
70 to 200
200 to 300
>300
07054-048
1V p-p
AD9627-11
A stable and accurate voltage reference is built into the
AD9627-11. The input range can be adjusted by varying the
reference voltage applied to the AD9627-11, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly. The various reference modes are summarized in the
sections that follow. The Reference Decoupling section describes
the best practices PCB layout of the reference.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN+A/VIN+B
VIN–A/VIN–B
ADC
CORE
VREF
Internal Reference Connection
1.0µF
VIN–A/VIN–B
ADC
CORE
VREF
0.1µF
TE
R1
Figure 52. Programmable Reference Configuration
If the internal reference of the AD9627-11 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 53 shows
how the internal reference voltage is affected by loading.
0
SELECT
LOGIC
SENSE
07054-051
0.5V
AD9627-11
0.5V
AD9627-11
B
SO
1.0µF
SELECT
LOGIC
SENSE
REFERENCE VOLTAGE ERROR (%)
VIN+A/VIN+B
R2
LE
A comparator within the AD9627-11 detects the potential at the
SENSE pin and configures the reference into four possible
modes, which are summarized in Table 11. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 51), setting VREF to 1.0 V. Connecting
the SENSE pin to VREF switches the reference amplifier output
to the SENSE pin, completing the loop and providing a 0.5 V
reference output.
0.1µF
07054-052
VOLTAGE REFERENCE
VREF = 0.5V
–0.25
VREF = 1.0V
–0.50
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
2.0
LOAD CURRENT (mA)
Figure 53. VREF Accuracy vs. Load
O
If a resistor divider is connected external to the chip, as shown
in Figure 52, the switch again sets to the SENSE pin. This puts
the reference amplifier in a noninverting mode with the VREF
output defined as follows:
R2 
VREF  0.5  1 

R1 

Table 11. Reference Configuration Summary
Selected Mode
External Reference
SENSE Voltage
AVDD
Resulting VREF (V)
N/A
Resulting Differential Span (V p-p)
2 × external reference
Internal Fixed Reference
VREF
0.5
1.0
Programmable Reference
0.2 V to VREF
Internal Fixed Reference
AGND to 0.2 V
R2 

0 .5   1 
 (see Figure 52)
R1 

1.0
Rev. B | Page 25 of 72
2 × VREF
2.0
07054-053
Figure 51. Internal Reference Configuration
AD9627-11
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
2.5
1.5
1.0
0.5
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
transformer/balun secondary limit clock excursions into the
AD9627-11 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9627-11 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
–1.0
–1.5
–2.0
0.1µF
0
20
40
60
80
TEMPERATURE (°C)
0.1µF
AVDD
CLK+
CLK–
1nF
0.1µF
CLOCK
INPUT
CLK+
ADC
AD9627-11
50Ω
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 57. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
CLK–
0.1µF
0.1µF
CLOCK
INPUT
2pF
07054-055
O
1.2V
ADC
AD9627-11
Figure 56. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9627-11 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
CLK+
SCHOTTKY
DIODES:
HSMS2822
0.1µF
B
SO
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
2pF
100Ω
50Ω
LE
Figure 54. Typical VREF Drift
CLOCK
INPUT
Figure 55. Equivalent Clock Input Circuit
0.1µF
CLOCK
INPUT
100Ω
0.1µF
ADC
AD9627-11
CLK–
50kΩ
Clock Input Options
The AD9627-11 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
CLK+
AD951x
PECL DRIVER
50kΩ
240Ω
240Ω
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
Rev. B | Page 26 of 72
07054-058
–20
07054-054
–2.5
–40
Mini-Circuits®
ADT1–1WT, 1:1Z
0.1µF
XFMR
07054-056
–0.5
07054-057
0
TE
REFERENCE VOLTAGE ERROR (mV)
2.0
Figure 56 and Figure 57 show two preferred methods for clocking
the AD9627-11 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
AD9627-11
Clock Duty Cycle
0.1µF
CLK+
AD951x
LVDS DRIVER
100Ω
0.1µF
CLOCK
INPUT
ADC
AD9627-11
07054-059
CLK–
50kΩ
50kΩ
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor in parallel with a 39 kΩ resistor (see Figure 60).
CLK+ can be driven directly from a CMOS gate. Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V, making the selection
of the drive logic voltage very flexible.
CLOCK
INPUT
1kΩ
OPTIONAL
0.1µF
100Ω
AD951x
CMOS DRIVER
CLK+
ADC
AD9627-11
1kΩ
50Ω1
150Ω
39kΩ
RESISTOR IS OPTIONAL.
07054-060
CLK–
0.1µF
B
SO
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
VCC
50Ω 1
1kΩ
AD951x
CMOS DRIVER
1kΩ
0.1µF
CLK+
ADC
AD9627-11
CLK–
150Ω RESISTOR IS OPTIONAL.
07054-061
0.1µF
CLOCK
INPUT
OPTIONAL 0.1µF
100Ω
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered where the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time period
that the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
LE
VCC
0.1µF
The AD9627-11 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the
performance of the AD9627-11. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 43.
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
Input Clock Divider
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low
frequency SNR (SNRLF) at a given input frequency (fINPUT) due
to jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 (  SNRLF /10) ]
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 62.
70
The AD9627-11 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized on every SYNC signal or only
on the first SYNC signal after the register is written. A valid
SYNC causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
0.05ps
65
MEASURED
SNR (dBc)
O
The AD9627-11 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
0.20ps
60
0.5ps
55
1.0ps
1.50ps
50
2.00ps
45
2.50ps
3.00ps
1
10
100
INPUT FREQUENCY (MHz)
Figure 62. SNR vs. Input Frequency and Jitter
Rev. B | Page 27 of 72
1000
07054-062
0.1µF
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
TE
0.1µF
CLOCK
INPUT
AD9627-11
1.00
0.3
TOTAL POWER
0.50
0.2
0.1
0.25
IDRVDD
0
0
0
25
50
75
100
SAMPLE RATE (MSPS)
TE
As shown in Figure 63 and Figure 64, the power dissipated by
the AD9627-11 is proportional to its sample rate. In CMOS
output mode, the digital power dissipation is determined
primarily by the strength of the digital drivers and the load on
each output bit.
Figure 64. AD9627-11-105 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9627-11 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD9627-11 to
its normal operating mode. Note that PDWN is referenced to
the digital output driver supply (DRVDD) and should not exceed
that supply voltage.
The maximum DRVDD current (IDRVDD) can be calculated as
LE
where N is the number of output bits (24, in the case of the
AD9627-11, with the fast detect output pins disabled).
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
B
SO
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency of fCLK/2. In practice, the DRVDD current
is established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 63 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
1.25
0.5
0.3
TOTAL POWER
0.2
0.50
IDRVDD
50
75
100
125
0
150
SAMPLE RATE (MSPS)
Figure 63. AD9627-11-150 Power and Current vs. Sample Rate
07054-063
0
25
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
0.1
IDVDD
0
The AD9627-11 output drivers can be configured to interface
with 1.8 V to 3.3 V CMOS logic families by matching DRVDD
to the digital supply of the interfaced logic. The AD9627-11 can
also be configured for LVDS outputs using a DRVDD supply
voltage of 1.8 V.
SUPPLY CURRENT (A)
O
0.4
0.75
0.25
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section for more details.
DIGITAL OUTPUTS
IAVDD
1.00
07054-064
IDVDD
POWER DISSIPATION AND STANDBY MODE
TOTAL POWER (W)
IAVDD
SUPPLY CURRENT (A)
Refer to Application Note AN-501 and Application Note AN-756
(see www.analog.com) for more information about jitter performance as it relates to ADCs.
IDRVDD = VDRVDD × CLOAD × fCLK × N
0.4
0.75
TOTAL POWER (W)
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9627-11. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or some other
method), it should be retimed by the original clock at the last step.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
Rev. B | Page 28 of 72
AD9627-11
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
When using the SPI interface, the data and fast detect outputs
of each channel can be independently three-stated by using the
output enable bar bit in Register 0x14.
As detailed in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
TIMING
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
The AD9627-11 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Voltage at Pin
AGND
AVDD
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9627-11.
These transients can degrade converter dynamic performance.
SDIO/DCS
DCS disabled
DCS enabled (default)
Digital Output Enable Function (OEB)
Table 13. Output Data Format
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
B
SO
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
The AD9627-11 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the DCO clock
polarity has been changed via the SPI. See Figure 2 and Figure 3
for a graphical timing description.
O
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Data Clock Output (DCO)
LE
The AD9627-11 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the SMI
SDO/OEB pin or through the SPI interface. If the SMI SDO/OEB
pin is low, the output data drivers are enabled. If the SMI SDO/OEB
pin is high, the output data drivers are placed in a high impedance
state. This OEB function is not intended for rapid access to the
data bus. Note that OEB is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
The lowest typical conversion rate of the AD9627-11 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
TE
SCLK/DFS
Offset binary (default)
Twos complement
Rev. B | Page 29 of 72
Twos Complement Mode
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
OR
1
0
0
0
1
AD9627-11
ADC OVERRANGE AND GAIN CONTROL
Fast Detect
Mode Select Bits
(Register 0x104[3:1])
000
001
010
011
100
101
1
Information Presented on
Fast Detect (FD) Pins of Each ADC1, 2
FD[3]
FD[2]
FD[1] FD[0]
ADC fast magnitude
(see Table 15)
OR
ADC fast magnitude
(see Table 16)
OR
F_LT
ADC fast magnitude
(see Table 17)
F_LT
ADC fast magnitude C_UT
(see Table 17)
OR
C_UT
F_UT
F_LT
OR
F_UT
IG
DG
The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode
configuration and FD0+/FD0− to FD9+/FD9− for the LVDS mode
configuration.
2
See the ADC Overrange (OR) and Gain Switching sections for more
information about OR, C_UT, F_UT, F_LT, IG, and DG.
LE
Using the SPI port, the user can provide a threshold above which
an overrange output is active. As long as the signal is below that
threshold, the output should remain low. The fast detect outputs
can also be programmed via the SPI port so that one of the pins
functions as a traditional overrange pin for customers who
currently use this feature. In this mode, all 11 bits of the converter
are examined in the traditional manner, and the output is high for
the condition normally defined as overflow. In either mode, the
magnitude of the data is considered in the calculation of the
condition (but the sign of the data is not considered). The
threshold detection responds identically to positive and negative
signals outside the desired range (magnitude).
Table 14. Fast Detect Mode Select Bits Settings
TE
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness.
Therefore, it is helpful to have a programmable threshold below
full scale that allows time to reduce the gain before the clip
actually occurs. In addition, because input signals can have
significant slew rates, latency of this function is of major concern.
Highly pipelined converters can have significant latency. A good
compromise is to use the output bits from the first stage of the
ADC for this function. Latency for these output bits is very low,
and overall resolution is not highly significant. Peak input signals
are typically between full scale and 6 dB to 10 dB below full
scale. A 3-bit or 4-bit output provides adequate range and
resolution for this function.
ADC FAST MAGNITUDE
B
SO
When the fast detect output pins are configured to output the ADC
fast magnitude (that is, when the fast detect mode select bits are
set to 0b000), the information presented is the ADC level from
an early converter stage with a latency of only two clock cycles
(when in CMOS output mode). Using the fast detect output pins in
this configuration provides the earliest possible level indication
information. Because this information is provided early in the
datapath, there is significant uncertainty in the level indicated.
The nominal levels, along with the uncertainty indicated by the
ADC fast magnitude, are shown in Table 15.
FAST DETECT OVERVIEW
O
The AD9627-11 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control implementations.
Each ADC has four fast detect (FD) output pins that are used to
output information about the current state of the ADC input
level. The function of these pins is programmable via the fast detect
mode select bits and the fast detect enable bits in Register 0x104,
allowing range information to be output from several points in
the internal datapath. These output pins can also be set up to
indicate the presence of overrange or underrange conditions,
according to programmable threshold levels. Table 14 shows the
six configurations available for the fast detect pins.
Table 15. ADC Fast Magnitude Nominal Levels
with Fast Detect Mode Select Bits = 000
ADC Fast
Magnitude on
FD[3:0] Pins
0000
0001
0010
0011
0100
0101
0110
0111
1000
Rev. B | Page 30 of 72
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to −0.56
−0.56 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to FS
−1.16 to 0
AD9627-11
Table 16. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 001
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to 0
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in
the coarse upper threshold register (Address 0x105[2:0]). This
value is compared with the ADC Fast Magnitude Bits[2:0]. The
coarse upper threshold output is output two clock cycles after
the level is exceeded at the input and, therefore, provides a fast
indication of the input signal level. The coarse upper threshold
levels are shown in Table 18. This indicator remains asserted for
a minimum of two ADC clock cycles or until the signal drops
below the threshold level.
Table 18. Coarse Upper Threshold Levels
Coarse Upper
Threshold Register
0x105[2:0]
000
001
010
011
100
101
110
111
LE
ADC Fast
Magnitude on
FD[3:1] Pins
000
001
010
011
100
101
110
111
Coarse Upper Threshold (C_UT)
TE
When the fast detect mode select bits are set to 0b001, 0b010, or
0b011, a subset of the fast detect output pins is available. In these
modes, the fast detect output pins have a latency of six clock cycles.
Table 16 shows the corresponding ADC input levels when the
fast detect mode select bits are set to 0b001 (that is, when ADC fast
magnitude is presented on the FD[3:1] pins).
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD[3:2]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 17.
Fine Upper Threshold (F_UT)
B
SO
Table 17. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 010 or 011
ADC Fast
Magnitude on
FD[2:1] Pins
00
01
10
11
Nominal Input
Magnitude
Below FS (dB)
<−14.5
−14.5 to −7
−7 to −3.25
−3.25 to 0
C_UT Is Active When Signal Magnitude
Below FS Is Greater Than (dB)
<−24
−24
−14.5
−10
−7
−5
−3.25
−1.8
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −12.04
−18.07 to −6.02
−8.52 to −2.5
−4.08 to 0
ADC OVERRANGE (OR)
O
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 12 ADC clock cycles. An overrange at the
input is indicated by this bit 12 clock cycles after it occurs.
GAIN SWITCHING
The AD9627-11 includes circuitry that is useful in applications
either where large dynamic ranges exist or where gain ranging
converters are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold
can be programmed. Fast detect mode select bit = 010 through fast
detect mode select bit = 101 support various combinations of the
gain switching options.
The fine upper threshold indicator is asserted if the input
magnitude exceeds the value programmed in the fine upper
threshold register located in Register 0x106 and Register 0x107.
The 13-bit threshold register is compared with the signal
magnitude at the output of the ADC. This comparison is subject to
the ADC clock latency but is accurate in terms of the converter
resolution. The fine upper threshold magnitude is defined by
the following equation:
dBFS = 20 log(Threshold Magnitude/213)
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input
magnitude is less than the value programmed in the fine lower
threshold register located at Register 0x108 and Register 0x109.
The fine lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to ADC clock latency but is accurate
in terms of the converter resolution. The fine lower threshold
magnitude is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
The operation of the fine upper threshold and fine lower
threshold indicators is shown in Figure 65.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Rev. B | Page 31 of 72
AD9627-11
Increment Gain (IG) and Decrement Gain (DG)
This comparison is subject to the ADC clock latency but allows
a finer, more accurate comparison. The fine upper threshold
magnitude is defined by the following equation:
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
gain control. The decrement gain indicator works in
conjunction with the coarse upper threshold bits, asserting when
the input magnitude is greater than the 3-bit value in the coarse
upper threshold register (Address 0x105). The increment gain
indicator, similarly, corresponds to the fine lower threshold bits,
except that it is asserted only if the input magnitude is less than
the value programmed in the fine lower threshold register after
the dwell time elapses. The dwell time is set by the 16-bit dwell
time value located at Address 0x10A and Address 0x10B and is
set in units of ADC input clock cycles ranging from 1 to 65,535.
The fine lower threshold register is a 13-bit register that is
compared with the magnitude at the output of the ADC.
dBFS = 20 log(Threshold Magnitude/213)
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
TE
The operation of the increment gain output and the decrement
gain output is shown in Figure 65.
LE
UPPER THRESHOLD (COARSE OR FINE)
DWELL TIME
F_LT
DG
IG
FINE LOWER THRESHOLD
DWELL TIME
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
O
Figure 65. Threshold Settings for C_UT, F_UT, IG, DG, and F_LT
Rev. B | Page 32 of 72
07054-065
C_UT OR F_UT*
B
SO
TIMER RESET BY
RISE ABOVE F_LT
AD9627-11
SIGNAL MONITOR
Figure 66 is a block diagram of the peak detector logic. The SMR
register contains the absolute magnitude of the peak detected by
the peak detector logic.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
B
SO
For each signal monitor measurement, a programmable signal
monitor period register (SMPR) controls the duration of the
measurement. This time period is programmed as the number of
input clock cycles in a 24-bit signal monitor period register
located at Address 0x113, Address 0x114, and Address 0x115.
This register can be programmed with a period from 128 samples
to 16.78 (224) million samples.
Because the dc offset of the ADC can be significantly larger
than the signal of interest (affecting the results from the signal
monitor), a dc correction circuit is included as part of the signal
monitor block to null the dc offset before measuring the power.
O
PEAK DETECTOR MODE
The magnitude of the input port signal is monitored over a
programmable time period (determined by SMPR) to give the
peak value detected. This function is enabled by programming a
Logic 1 in the signal monitor mode bits of the signal monitor
control register or by setting the peak detector output enable bit
in the signal monitor SPORT control register. The 24-bit SMPR
must be programmed before activating this mode.
After enabling this mode, the value in the SMPR is loaded into
a monitor period timer and the countdown is started. The magnitude of the input signal is compared with the value in the
internal peak level holding register (not accessible to the user),
and the greater of the two is updated as the current peak level.
The initial value of the peak level holding register is set to the
current ADC input signal magnitude. This comparison continues
until the monitor period timer reaches a count of 1.
DOWN
COUNTER
IS COUNT = 1?
LOAD
CLEAR
MAGNITUDE
STORAGE
REGISTER
LOAD
TO
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)
LOAD
COMPARE
A>B
07054-066
FROM
INPUT
PORTS
LE
The signal monitor result values can be obtained from the part by
reading back internal registers at Address 0x116 to Address 0x11B,
using the SPI port or the signal monitor SPORT output. The output
contents of the SPI-accessible signal monitor registers are set via
the two signal monitor mode bits of the signal monitor control
register. Both ADC channels must be configured for the same
signal monitor mode. Separate SPI-accessible, 20-bit signal monitor
result (SMR) registers are provided for each ADC channel. Any
combination of the signal monitor functions can also be output
to the user via the serial SPORT interface. These outputs are
enabled using the peak detector output enable, the rms magnitude output enable, and the threshold crossing output enable
bits in the signal monitor SPORT control register.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding register
(not accessible to the user), which can be read through the SPI port
or output through the SPORT serial interface. The monitor period
timer is reloaded with the value in the SMPR, and the countdown
is restarted. In addition, the magnitude of the first input sample is
updated in the peak level holding register, and the comparison
and update procedure, as explained previously, continues.
TE
The signal monitor block provides additional information about
the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the
number of samples by which the magnitude exceeds a particular
threshold. Together, these functions can be used to gain insight
into the signal characteristics and to estimate the peak/average
ratio or even the shape of the complementary cumulative
distribution function (CCDF) curve of the input signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
Figure 66. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE
In this mode, the root-mean-square (rms) or mean-square (ms)
magnitude of the input port signal is integrated (by adding an
accumulator) over a programmable time period (determined by
SMPR) to give the rms or ms magnitude of the input signal.
This mode is set by programming Logic 0 in the signal monitor
mode bits of the signal monitor control register or by setting the
rms magnitude output enable bit in the signal monitor SPORT
control register. The 24-bit SMPR, representing the period over
which integration is performed, must be programmed before
activating this mode.
After enabling the rms/ms magnitude mode, the value in the SMPR
is loaded into a monitor period timer, and the countdown is started
immediately. Each input sample is converted to floating-point
format and squared. It is then converted to 11-bit, fixed-point
format and added to the contents of the 24-bit accumulator. The
integration continues until the monitor period timer reaches a
count of 1.
When the monitor period timer reaches a count of 1, the square
root of the value in the accumulator is taken and transferred,
after some formatting, to the signal monitor holding register,
which can be read through the SPI port or output through the
SPORT serial port. The monitor period timer is reloaded with
the value in the SMPR, and the countdown is restarted. In
addition, the first input sample signal power is updated in
the accumulator, and the accumulation continues with the
subsequent input samples.
Rev. B | Page 33 of 72
AD9627-11
Figure 67 illustrates the rms magnitude monitoring logic.
IS COUNT = 1?
LOAD
CLEAR
ACCUMULATOR
TO
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)
LOAD
07054-067
FROM
INPUT
PORTS
Figure 67. ADC Input RMS Magnitude Monitoring Block Diagram
For rms magnitude mode, the value in the signal monitoring result
(SMR) register is a 20-bit fixed-point number. The following
equation can be used to determine the rms magnitude in dBFS
from the MAG value in the register. Note that if the signal monitor
period (SMP) is a power of 2, the second term in the equation
becomes 0.
MAG
SMP
RMS Magnitude = 20 log  20   10 log  ceil log 2 (SMP ) 
 2 
2

FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
FROM
MEMORY
MAP
CLEAR
A COMPARE
A>B
COMPARE
A>B
TO
LOAD
MEMORY
SIGNAL MONITOR MAP/SPORT
HOLDING
REGISTER (SMR)
B
UPPER
THRESHOLD
REGISTER
Figure 68. ADC Input Threshold Crossing Block Diagram
LE
For ms magnitude mode, the value in the SMR is a 20-bit fixedpoint number. The following equation can be used to determine
the ms magnitude in dBFS from the MAG value in the register.
Note that if the SMP is a power of 2, the second term in the
equation becomes 0.
The monitor period timer is reloaded with the value in the SMPR
register, and the countdown is restarted. The internal count
register is also cleared to a value of 0. Figure 68 illustrates the
threshold crossing logic. The value in the SMR register is the
number of samples that have a magnitude greater than the
threshold register.
07054-068
DOWN
COUNTER
TE
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
When the monitor period timer reaches a count of 1, the value
in the internal count register is transferred to the signal monitor
holding register, which can be read through the SPI port or
output through the SPORT serial port.
For additional flexibility in the signal monitoring process, two
control bits are provided in the signal monitor control register.
They are the signal monitor enable bit and the complex power
calculation mode enable bit.
B
SO
MAG
SMP
MS Magnitude = 10 log  20   10 log  ceil log 2 (SMP ) 
2
2




ADDITIONAL CONTROL BITS
THRESHOLD CROSSING MODE
O
In the threshold crossing mode of operation, the magnitude of
the input port signal is monitored over a programmable time
period (given by SMPR) to count the number of times it crosses a
certain programmable threshold value. This mode is set by
programming Logic 1x (where x is a don’t care bit) in the power
monitor mode bits of the signal monitor control register or by
setting the threshold crossing output enable bit in the signal
monitor SPORT control register. Before activating this mode,
the user needs to program the 24-bit SMPR and the 13-bit
upper threshold register for each individual input port. The
same upper threshold register is used for both signal
monitoring and gain control (see the ADC Overrange and Gain
Control section).
After entering this mode, the value in the SMPR is loaded into
a monitor period timer, and the countdown is started. The magnitude of the input signal is compared with the upper threshold
register (programmed previously) on each input clock cycle.
If the input signal has a magnitude greater than the upper threshold
register, the internal count register is incremented by 1.
The initial value of the internal count register is set to 0. This
comparison and incrementing of the internal count register
continues until the monitor period timer reaches a count of 1.
Signal Monitor Enable Bit
The signal monitor enable bit, located in Bit 0 of Register 0x112,
enables operation of the signal monitor block. If the signal monitor
function is not needed in a particular application, this bit should
be cleared (default) to conserve power.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is digitizing
the I data and Channel B is digitizing the Q data for a complex
input signal (or vice versa). In this mode, the power reported is
equal to
I 2  Q2
This result is presented in the Signal Monitor DC Value Channel A
register if the signal monitor mode bits are set to 00. The Signal
Monitor DC Value Channel B register continues to compute the
Channel B value.
DC CORRECTION
Because the dc offset of the ADC may be significantly larger
than the signal being measured, a dc correction circuit is included
to null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path, but this
may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
Rev. B | Page 34 of 72
AD9627-11
DC Correction Bandwidth
SIGNAL MONITOR SPORT OUTPUT
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing the 4-bit dc correction
register located at Register 0x10C, Bits[5:2].
The following equation can be used to compute the bandwidth
value for the dc correction circuit:
f
DC _ Corr _ BW  2 k  14  CLK
2 
The SPORT is a serial interface with three output pins:
SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync) and
SMI SDO (SPORT data output). The SPORT is the master and
drives all three SPORT output pins on the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the SMI
SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4, or 1/8
the ADC clock rate, based on the SPORT controls. The SMI SCLK
can also be gated off when not sending any data by using the
SPORT SMI SCLK sleep bit. Using this bit to disable the SMI SCLK
when it is not needed can reduce any coupling errors back into the
signal path, if these prove to be a problem in the system. Doing so,
however, has the disadvantage of spreading the frequency content
of the clock. If desired, the SMI SCLK can be left running to ease
frequency planning.
TE
where:
k is the 4-bit value programmed in Register 0x10C, Bits[5:2]
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
fCLK is the AD9627-11 ADC sample rate in hertz (Hz).
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and Register 0x10F and
Register 0x110 for Channel B. The dc correction value is an 11-bit
value that can span the entire input range of the ADC.
SMI SDFS
LE
The SMI SDFS is the serial data frame sync, and it defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
Setting Bit 6 of Register 0x10C freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
B
SO
DC Correction Enable Bits
SMI SDO
Setting Bit 0 of Register 0x10C enables dc correction for use in
the signal monitor calculations. The calculated dc correction
value can be added to the output data signal path by setting Bit 1
of Register 0x10C.
SMI SCLK
SMI SDFS
MSB
PK CH A
RMS/MS CH A LSB
O
SMI SDO
20 CYCLES
16 CYCLES
THR CH A
MSB
16 CYCLES
The SMI SDO is the serial data output of the block. The data
is sent MSB first on the next positive edge after the SMI SDFS.
Each data output block includes one or more rms magnitude, peak
level, and threshold crossing values from each datapath in the
stated order. If enabled, the data is sent, rms first, followed by peak
and threshold, as shown in Figure 69.
GATED, BASED ON CONTROL
RMS/MS CH B LSB
20 CYCLES
PK CH B
16 CYCLES
THR CH B
RMS/MS CH A
07054-069
DC Correction Freeze
16 CYCLES
Figure 69. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
GATED, BASED ON CONTROL
SMI SCLK
SMI SDFS
MSB
RMS/MS CH A LSB
20 CYCLES
THR CH A
16 CYCLES
MSB
RMS/MS CH B LSB
20 CYCLES
THR CH B
16 CYCLES
Figure 70. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
Rev. B | Page 35 of 72
RMS/MS CH A
07054-070
SMI SDO
AD9627-11
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
BUILT-IN SELF-TEST (BIST)
OUTPUT TEST MODES
The output test options are shown in Table 22. When an output
test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see
Application Note AN-877, Interfacing to High Speed ADCs via SPI.
O
B
SO
LE
The BIST is a thorough test of the digital portion of the selected
AD9627-11 signal path. When enabled, the test runs from an
internal pseudorandom noise (PN) source through the digital
datapath, starting at the ADC block output. The BIST sequence
runs for 512 cycles and then stops. The BIST signature value for
Channel A or Channel B is placed in Register 0x24 and
Register 0x25. If one channel is chosen, its BIST signature is written
to the two registers. If both channels are chosen, the results from
Channel A are placed in the BIST signature registers.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
TE
The AD9627-11 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9627-11.
Various output test options are also provided to place predictable
values on the outputs of the AD9627-11.
Rev. B | Page 36 of 72
AD9627-11
CHANNEL/CHIP SYNCHRONIZATION
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between multiple
parts, the SYNC input signal should be externally synchronized to
the input clock signal, meeting the setup and hold times shown
in Table 5. The SYNC input should be driven using a singleended CMOS-type signal.
O
B
SO
LE
TE
The AD9627-11 has a SYNC input that offers the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The signal monitor
block can also be synchronized using the SYNC input, allowing
properties of the input signal to be measured during a specific time
period. The input clock divider can be enabled to synchronize on a
single occurrence of the SYNC signal or on every occurrence. The
signal monitor block is synchronized on every SYNC input signal.
Rev. B | Page 37 of 72
AD9627-11
SERIAL PORT INTERFACE (SPI)
CONFIGURATION USING THE SPI
Table 19. Serial Port Interface Pins
SDIO
CSB
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see Application Note AN-877, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active-low control that gates the read
and write cycles.
The pins described in Table 19 comprise the physical interface
between the user programming device and the serial port of the
AD9627-11. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
B
SO
Pin
SCLK
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
LE
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 19). The SCLK/DFS
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent
and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active-low control that enables or
disables the read and write cycles.
All data is composed of 8-bit words. The first bit of the first byte
in a multibyte serial data transfer frame indicates whether a
read command or a write command is issued. This allows the
serial data input/output (SDIO) pin to change direction from an
input to an output.
TE
The AD9627-11 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
The SPI gives the user added flexibility and customization,
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port.
Memory is organized into bytes that can be further divided into
fields, which are documented in the Memory Map section. For
detailed operational information, see Application Note AN-877,
Interfacing to High Speed ADCs via SPI.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 71
and Table 5.
O
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in Application Note AN-812, MicrocontrollerBased Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9627-11 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to AVDD or ground
during device power-on, they are associated with a specific
function. The Digital Outputs section describes the strappable
functions supported on the AD9627-11.
Rev. B | Page 38 of 72
AD9627-11
CONFIGURATION WITHOUT THE SPI
SPI ACCESSIBLE FEATURES
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOScompatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 21 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in Application Note AN-877, Interfacing to High Speed ADCs
via SPI. The AD9627-11 part-specific features are described in
detail following Table 22, the external memory map register table.
Table 20. Mode Selection
Clock
Offset
SMI SDO/OEB
SMI SCLK/PDWN
AGND (default)
tHIGH
tS
CSB
Output Mode
Output Phase
Output Delay
VREF
tCLK
B
SO
tDS
Test I/O
tDH
tH
tLOW
SCLK DON’T CARE
R/W
W1
W0
O
SDIO DON’T CARE
A12
A11
A10
A9
A8
DON’T CARE
A7
D5
Figure 71. Serial Port Interface Timing Diagram
Rev. B | Page 39 of 72
D4
D3
D2
D1
D0
DON’T CARE
07054-071
SCLK/DFS
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or
standby
Normal operation
Description
Allows the user to set either power-down
mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
TE
Pin
SDIO/DCS
Feature Name
Mode
LE
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
Table 21. Features Accessible Using the SPI
AD9627-11
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the
chip configuration registers (Address 0x00 to Address 0x02);
the channel index and transfer registers (Address 0x05 and
Address 0xFF); the ADC functions registers, including setup,
control, and test (Address 0x08 to Address 0x25); and the digital
feature control registers (Address 0x100 to Address 0x11B).
An explanation of logic level terminology follows:
Open Locations
Transfer Register Map
TE
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these
cases, channel address locations are internally duplicated for
each channel. These registers and bits are designated in Table 22
as local. These local registers and bits can be accessed by setting
the appropriate Channel A or Channel B bits in Register 0x05. If
both bits are set, the subsequent write affects the registers of both
channels. In a read cycle, only Channel A or Channel B should be
set to read one of the two registers. If both bits are set during an
SPI read cycle, the part returns the value for Channel A. Registers
and bits designated as global in Table 22 affect the entire part or
the channel features where independent settings are not allowed
between channels. The settings in Register 0x05 do not affect
the global registers and bits.
B
SO
All address and bit locations that are not included in Table 22
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values

“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
LE
The memory map register table (see Table 22) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x18, the
VREF select register, has a hexadecimal default value of 0xC0.
This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s.
This setting is the default reference selection setting. The default
value uses a 2.0 V p-p reference. For more information on this
function and others, see Application Note AN-877, Interfacing to
High Speed ADCs via SPI. This document details the functions
controlled by Register 0x00 to Register 0xFF. The remaining
registers, from Register 0x100 to Register 0x11B, are documented
in the Memory Map Register Description section.

O
After the AD9627-11 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 22.
Rev. B | Page 40 of 72
AD9627-11
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 22 are not currently supported for this device.
Table 22. Memory Map Registers
Chip ID
(Global)
0x02
Chip Grade
(Global)
Open
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB first
Soft reset
1
1
Soft reset
LSB first
0
Open
Open
Open
B
SO
Transfer
Default
Notes/
Comments
0x18
The nibbles
are mirrored
so that
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
Read only
0x20
Open
Open
Open
Open
Data
Channel B
(default)
Data
Channel A
(default)
0x03
Transfer
0x00
Speed grade
ID used to
differentiate
devices; read
only
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers only
Synchronously
transfers data
from the
master shift
register to the
slave
Open
Open
Open
Open
Open
Open
Open
ADC Functions
0x08
Power Modes
Open
Open
Open
Open
Open
Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
0x00
0x09
Global Clock
(Global)
Open
Open
External
powerdown pin
function
(global)
0 = pdwn
1 = stndby
Open
Open
Open
Open
Open
Duty cycle
stabilizer
(default)
0x01
0x0B
Clock Divide
(Global)
Open
Open
Open
Open
Open
0x00
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active
0x0D
Test Mode
(Local)
Open
Open
Reset PN23
gen
Reset
PN9 gen
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN 23 sequence
110 = PN 9 sequence
111 = one/zero word toggle
0x00
When this
register is set,
the test data
is placed on
the output
pins in place of
normal data
O
0xFF
8-bit Chip ID[7:0]
(AD9627-11 = 0x20)
(default)
Speed grade ID
Open
00 = 150 MSPS
10 = 105 MSPS
Open
Channel Index and Transfer Registers
0x05
Open
Open
Channel
Index
Default
Value
(Hex)
TE
0x01
Bit 6
Bit 0
(LSB)
LE
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0x00
0
SPI Port
Configuration
(Global)
Rev. B | Page 41 of 72
Determines
various generic
modes of chip
operation
AD9627-11
0x16
Clock Phase
Control
(Global)
0x17
DCO Output
Delay
(Global)
0x18
VREF Select
(Global)
0x24
0x105
0x106
0x107
0x108
Open
Open
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS;
1 V to 1.8 V
CMOS or
reduced
LVDS
(global)
Invert
DCO clock
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Output
enable bar
(local)
Open
Open
Open
Open
Open
Open
Open
Open
Reference voltage
selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
Signal
monitor
sync
enable
Open
Open
Open
Bit 5
Open
Bit 4
Open
Bit 3
Open
Bit 2
Reset BIST
sequence
Bit 1
Open
Output
invert
(local)
Fast Detect
Control
(Local)
Coarse Upper
Threshold
(Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Open
Open
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Open
Open
Open
Open
0x00
Configures the
outputs and
the format of
the data
Allows
selection of
clock delays
into the input
clock divider
0x00
0xC0
Read only
BIST Signature[15:8]
0x00
Read only
Open
Open
Open
Open
Open
Open
Open
0x00
0x00
Open
Open
Default
Notes/
Comments
BIST Signature[7:0]
Open
Clock
Clock
divider
divider
next sync
sync
only
enable
Fast Detect Mode Select[2:0]
Open
Master
sync
enable
0x00
Fast detect
enable
0x00
Coarse Upper Threshold[2:0]
Fine Upper Threshold[7:0]
Open
Default
Value
(Hex)
0x00
0x00
Offset adjust in LSBs from +31 to −32
(twos complement format)
Open
O
BIST
Signature LSB
(Local)
0x25
BIST
Signature
MSB (Local)
Digital Feature Control
0x100
Sync Control
(Global)
0x104
Bit 6
Open
Bit 0
(LSB)
BIST enable
TE
0x14
Bit 7
(MSB)
Open
LE
0x10
Register
Name
BIST Enable
(Local)
Offset Adjust
(Local)
Output Mode
B
SO
Addr
(Hex)
0x0E
Fine Upper Threshold[12:8]
Fine Lower Threshold[7:0]
Rev. B | Page 42 of 72
0x00
0x00
0x00
0x00
AD9627-11
0x10C
0x10D
0x10E
0x10F
0x110
0x111
Signal Monitor
Control
(Global)
Bit 5
Open
Default
Notes/
Comments
Increase Gain Dwell Time[7:0]
0x00
In ADC clock
cycles
Increase Gain Dwell Time[15:8]
0x00
In ADC clock
cycles
Bit 4
Bit 3
Bit 2
Bit 1
Fine Lower Threshold[12:8]
DC Correction Bandwidth[3:0]
DC
correction
freeze
DC
correction
for signal
path
enable
DC
correction
for signal
monitor
enable
0x00
DC Value Channel A[7:0]
Open
Open
DC Value Channel A[13:8]
DC Value Channel B[7:0]
Open
Open
Open
RMS/MS
magnitude
output
enable
Peak
detector
output
enable
Complex
power
calculation
mode
enable
Open
Open
SPORT SMI
SPORT
SCLK divide
SMI SCLK
sleep
00 = undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
Open
Signal monitor mode
Signal
monitor
00 = rms/ms magnitude
rms/ms
01 = peak detector
select
10 = threshold crossing
0 = rms
11 = threshold crossing
1 = ms
Signal Monitor Period[7:0]
Read only
Read only
DC Value Channel B[13:8]
Threshold
crossing
output
enable
Read only
Read only
Signal
monitor
SPORT
output enable
0x04
Signal
monitor
enable
0x00
O
0x112
Open
Bit 6
Open
Default
Value
(Hex)
0x00
Bit 0
(LSB)
TE
0x10B
Bit 7
(MSB)
Open
LE
0x10A
Register
Name
Fine Lower
Threshold
Register 1
(Local)
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain
Dwell Time
Register 1
(Local)
Signal Monitor
DC
Correction
Control
(Global)
Signal Monitor
DC Value
Channel A
Register 0
(Global)
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Signal Monitor
DC Value
Channel B
Register 0
(Global)
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Signal Monitor
SPORT Control
(Global)
B
SO
Addr
(Hex)
0x109
0x40
In ADC clock
cycles
Signal Monitor Period[15:8]
0x00
In ADC clock
cycles
0x115
Signal Monitor Period[23:16]
0x00
In ADC clock
cycles
0x113
0x114
0x116
Signal Monitor
Period
Register 0
(Global)
Signal Monitor
Period
Register 1
(Global)
Signal Monitor
Period
Register 2
(Global)
Signal Monitor
Result
Channel A
Register 0
(Global)
Signal Monitor Result Channel A[7:0]
Rev. B | Page 43 of 72
Read only
AD9627-11
0x119
0x11A
0x11B
Bit 7
(MSB)
Bit 6
Bit 5
Open
Open
Open
Bit 4
Bit 3
Bit 2
Signal Monitor Result Channel A[15:8]
Open
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Signal Monitor Value Channel A[19:16]
Signal Monitor Result Channel B[7:0]
TE
0x118
Register
Name
Signal Monitor
Result
Channel A
Register 1
(Global)
Signal Monitor
Result
Channel A
Register 2
(Global)
Signal Monitor
Result
Channel B
Register 0
(Global)
Signal Monitor
Result
Channel B
Register 1
(Global)
Signal Monitor
Result
Channel B
Register 2
(Global)
Signal Monitor Result Channel B[15:8]
Open
Open
Open
MEMORY MAP REGISTER DESCRIPTIONS
Open
Read only
Read only
Read only
Read only
Bit 0—Fast Detect Enable
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see Application Note AN-877,
Interfacing to High Speed ADCs via SPI.
Bit 0 is used to enable the fast detect output pins. When the
fast detect output pins are disabled, the outputs go into a high
impedance state. In LVDS mode, when the outputs are interleaved, the outputs go high-Z only if both channels are turned
off (power-down/standby/output disabled). If only one channel is
turned off (power-down/standby/output disabled), the fast detect
output pins repeat the data of the active channel.
B
SO
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Signal Monitor Result Channel B[19:16]
Default
Notes/
Comments
Read only
LE
Addr
(Hex)
0x117
Bit 7 enables the sync pulse from the external SYNC input to
the signal monitor block. The sync signal is passed when Bit 7
and Bit 0 are high. This is continuous sync mode.
Bits[6:3]—Reserved
Coarse Upper Threshold (Register 0x105)
Bits[7:3]—Reserved
Bits[2:0]—Coarse Upper Threshold
Bit 2—Clock Divider Next Sync Only
O
If the master sync enable bit (Address 0x100, Bit 0) and the clock
divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to sync to the first sync pulse it receives
and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
These bits set the level required to assert the coarse upper
threshold indication (see Table 18).
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0]
Register 0x107, Bits[7:5]—Reserved
Bit 1—Clock Divider Sync Enable
Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]
Bit 1 gates the sync pulse to the clock divider. The sync signal is
passed when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
These registers provide the fine upper limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block.
If the ADC magnitude exceeds this threshold value, the F_UT
flag is set.
Bit 0—Master Sync Enable
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]
Register 0x109, Bits[7:5]—Reserved
Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8]
Bit 0 must be high to enable any of the sync functions.
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved
Bits[3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output pins (see Table 14).
These registers provide the fine lower limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block.
If the ADC magnitude is less than this threshold value, the F_LT
flag is set.
Rev. B | Page 44 of 72
AD9627-11
Increase Gain Dwell Time (Register 0x10A and
Register 0x10B)
Register 0x10A, Bits[7:0]—Increase Gain Dwell Time[7:0]
Register 0x10B, Bits[7:0]—Increase Gain Dwell Time[15:8]
These registers are programmed with the dwell time in ADC
clock cycles for which the signal must be below the fine lower
threshold value before the increase gain output is asserted.
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved
Bit 6—RMS/MS Magnitude Output Enable
These bits enable the 20-bit rms or ms magnitude measurement
as output on the SPORT.
Bit 5—Peak Detector Output Enable
Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved
Bit 6—DC Correction Freeze
Bit 5 enables the 13-bit peak measurement as output on the
SPORT.
When Bit 6 is set high, the dc correction is no longer updated
to the signal monitor block. It holds the last dc value it calculated.
Bit 4 enables the 13-bit threshold measurement as output on
the SPORT.
These bits set the averaging time of the power monitor dc
correction function. This 4-bit word sets the bandwidth of the
correction block according to the following equation:
Bit 1— SPORT SMI SCLK Sleep
where:
k is the 4-bit value programmed in Register 0x10C, Bits[5:2]
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
fCLK is the AD9627-11 ADC sample rate in hertz (Hz).
B
SO
Bit 1—DC Correction for Signal Path Enable
The values of these bits set the SPORT SMI SCLK divide ratio
from the input clock. A value of 0x01 sets divide by 2 (default),
a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.
Setting Bit 1 high causes the SMI SCLK to remain low when the
signal monitor block has no data to transfer.
LE
fCLK
2 
TE
Bits[3:2]—SPORT SMI SCLK Divide
Bits[5:2]—DC Correction Bandwidth
DC _ Corr _ BW  2 k  14 
Bit 4—Threshold Crossing Output Enable
Setting Bit 1 high causes the output of the dc measurement
block to be summed with the data in the signal path to remove
the dc offset from the signal path.
Bit 0—DC Correction for Signal Monitor Enable
Bit 0 enables the dc correction function in the signal monitor
block. The dc correction is an averaging function that can be
used by the signal monitor to remove dc offset in the signal.
Removing this dc offset from the measurement allows a more
accurate reading.
O
Signal Monitor DC Value Channel A (Register 0x10D and
Register 0x10E)
Register 0x10D, Bits[7:0]—DC Value Channel A[7:0]
Register 0x10E, Bits[7:6]—Reserved
Register 0x10E, Bits[5:0]—DC Value Channel A[13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel A.
Signal Monitor DC Value Channel B (Register 0x10F and
Register 0x110)
Register 0x10F, Bits[7:0]—DC Value Channel B[7:0]
Bit 0—Signal Monitor SPORT Output Enable
When set, Bit 0 enables the SPORT output of the signal monitor
to begin shifting out the result data from the signal monitor block.
Signal Monitor Control (Register 0x112)
Bit 7—Complex Power Calculation Mode Enable
This mode assumes I data is present on one channel and Q data
is present on the alternate channel. The result reported is the
complex power, measured as
I 2  Q2
Bits[6:4]—Reserved
Bit 3—Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting
Bit 3 high selects ms power measurement mode.
Bits[2:1]—Signal Monitor Mode
Bit 2 and Bit 1 set the mode of the signal monitor for data output
to Register 0x116 through Register 0x11B. Setting Bit 2 and Bit 1
to 0x00 selects rms/ms magnitude output; setting these bits to
0x01 selects peak detector output; and setting these bits to 0x10
or 0x11 selects threshold crossing output.
Bit 0—Signal Monitor Enable
Setting Bit 0 high enables the signal monitor block.
Register 0x110, Bits[7:6]—Reserved
Register 0x110, Bits[5:0]—DC Value Channel B[13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel B.
Rev. B | Page 45 of 72
AD9627-11
Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x113, Bits[7:0]—Signal Monitor Period[7:0]
Register 0x114, Bits[7:0]—Signal Monitor Period[15:8]
Register 0x115, Bits[7:0]—Signal Monitor Period[23:16]
This 24-bit value sets the number of clock cycles over which the
signal monitor performs its operation. Although this register
defaults to 64 (0x40), the minimum value for this register is 128
(0x80) cycles. Writing values less than 128 can cause inaccurate
results.
Signal Monitor Result Channel A (Register 0x116 to
Register 0x118)
Register 0x116, Bits[7:0]—Signal Monitor Result
Channel A[7:0]
Signal Monitor Result Channel B (Register 0x119 to
Register 0x11B)
Register 0x119, Bits[7:0]— Signal Monitor Result
Channel B[7:0]
Register 0x11A, Bits[7:0]—Signal Monitor Result
Channel B[15:8]
Register 0x11B, Bits[7:4]—Reserved
Register 0x11B, Bits[3:0]—Signal Monitor Result
Channel B[19:16]
TE
This 20-bit value contains the result calculated by the signal
monitoring block for Channel B. The result is dependent on the
settings in Register 0x112[2:1].
Register 0x117, Bits[7:0]—Signal Monitor Result
Channel A[15:8]
Register 0x118, Bits[3:0]—Signal Monitor Result
Channel A[19:16]
LE
Register 0x118, Bits[7:4]—Reserved
O
B
SO
This 20-bit value contains the result calculated by the signal
monitoring block for Channel A. The result is dependent on the
settings in Register 0x112[2:1].
Rev. B | Page 46 of 72
AD9627-11
APPLICATIONS INFORMATION
Before starting design and layout of the AD9627-11 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information
about packaging and PCB layout of chip scale packages, see
Application Note AN-772, A Design and Manufacturing Guide
for the Lead Frame Chip Scale Package (LFCSP).
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 47.
LE
When connecting power to the AD9627-11, it is recommended
that two separate 1.8 V supplies be used: one supply should be used
for analog (AVDD) and digital (DVDD), and a separate supply
should be used for the digital outputs (DRVDD). The AVDD
and DVDD supplies, while derived from the same source, should
be isolated with a ferrite bead or filter choke and separate
decoupling capacitors. The designer can employ several
different decoupling capacitors to cover both high and low
frequencies. These capacitors should be located close to the
point of entry at the PC board level and close to the pins of the
part, with minimal trace length.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow
through the bottom of the PCB. These vias should be filled or
plugged with nonconductive epoxy.
TE
DESIGN GUIDELINES
A single PCB ground plane should be sufficient when using the
AD9627-11. With proper decoupling and smart partitioning of
the PCB analog, digital, and clock sections, optimum
performance is easily achieved.
RBIAS
LVDS Operation
Reference Decoupling
B
SO
The AD9627-11 defaults to CMOS output mode on power-up.
If LVDS operation is desired, this mode must be programmed
using the SPI configuration registers after power-up. When the
AD9627-11 powers up in CMOS mode with LVDS termination
resistors (100 Ω) on the outputs, the DRVDD current can be
higher than the typical value until the part is placed in LVDS
mode. This additional DRVDD current does not cause damage
to the AD9627-11, but it should be taken into account when
considering the maximum DRVDD current for the part.
The VREF pin should be externally decoupled to ground with a
low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9627-11 to keep these signals from transitioning at the
converter inputs during critical sampling periods.
O
To avoid this additional DRVDD current, the AD9627-11
outputs can be disabled at power-up by taking the OEB pin high.
After the part is placed into LVDS mode via the SPI port, the
OEB pin can be taken low to enable the outputs.
The AD9627-11 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask), copper plane on the PCB should mate to the
AD9627-11 exposed paddle, Pin 0.
Rev. B | Page 47 of 72
AD9627-11
EVALUATION BOARD
The AD9627-11 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially through
a double balun configuration (default) or optionally through the
AD8352 differential driver. The ADC can also be driven in a
single-ended fashion. Separate power pins are provided to isolate
the DUT from the AD8352 drive circuitry. Each input
configuration can be selected by proper connection of various
components (see Figure 73 to Figure 82). Figure 72 shows the
typical bench characterization setup used to evaluate the ac
performance of the AD9627-11.
External supplies can be used to operate the evaluation board
by removing L1, L3, L4, and L13 to disconnect the voltage
regulators supplied from the switching power supply. This enables
the user to individually bias each section of the board. Use P3
and P4 to connect a different supply for each section. At least
one 1.8 V supply is needed with a 1 A current capability for
AVDD and DVDD; a separate 1.8 V to 3.3 V supply is recommended for DRVDD. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP_VDD) with
a 1 A current capability is needed. To operate the evaluation board
using the alternate SPI options, a separate 3.3 V analog supply
(VS) is needed, in addition to the other supplies. The 3.3 V
supply (VS) should have a 1 A current capability, as well. Solder
Jumper SJ35 allows the user to separate AVDD and DVDD,
if desired.
TE
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz
SMA100A signal generators or the equivalent. Use 1 m long,
shielded, RG-58, 50 Ω coaxial cable for making connections to
the evaluation board. Enter the desired frequency and amplitude
for the ADC. The AD9627-11 evaluation board from Analog
Devices, Inc., can accept a ~2.8 V p-p or 13 dBm sine wave input
for the clock. When connecting the analog input source, it is
recommended that a multipole, narrow-band, band-pass filter
with 50 Ω terminations be used. Band-pass filters of this type
are available from TTE, Allen Avionics, and K&L Microwave, Inc.
Connect the filter directly to the evaluation board, if possible.
LE
See Figure 73 to Figure 90 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
B
SO
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The output of the supply is a 2.1 mm inner diameter
circular jack that connects to the PCB at J16. Once on the PC
board, the 6 V supply is fused and conditioned before connection
to five low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog
Devices standard ADC data capture board (HSC-ADC-EVALCZ).
For more information on the ADC data capture boards and
their optional settings, visit www.analog.com/FIFO.
–
+
VCP
AD9627-11
EVALUATION BOARD
11-BIT
PARALLEL
CMOS
11-BIT
PARALLEL
CMOS
CLK
SPI
Figure 72. Evaluation Board Connection
Rev. B | Page 48 of 72
HSC-ADC-EVALCZ
FPGA BASED
DATA
CAPTURE BOARD
USB
CONNECTION
SPI
PC RUNNING
VISUAL ANALOG
AND SPI
CONTROLLER
SOFTWARE
07054-072
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
+
GND
AINB
3.3V
–
VS
BAND-PASS
FILTER
3.3V
+
GND
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
3.3V
–
DRVDD IN
AINA
–
GND
BAND-PASS
FILTER
+
AMP VDD
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
1.8V
+
–
GND
5.0V
SWITCHING
POWER
SUPPLY
GND
6V DC
2A MAX
AVDD IN
O
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
AD9627-11
The following is a list of the default and optional settings or
modes allowed on the AD9627-11 evaluation board.
POWER
Connect the switching power supply that is provided in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching from
70 MHz to 200 MHz. For more bandwidth response, the
differential capacitor across the analog inputs can be changed or
removed (see Table 10). The common mode of the analog
inputs is developed from the center tap of the transformer via
the CML pin of the ADC (see the Analog Input Considerations
section).
The CSB pin is internally pulled up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect J21, Pin 1 to J21, Pin 2.
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets
the data format of the outputs. If the pin is left floating, the pin is
internally pulled down, setting the default data format condition
to offset binary. Connecting J2, Pin 1 to J2, Pin 2 sets the format
to twos complement. If the SPI port is in serial pin mode,
connecting J2, Pin 2 to J2, Pin 3 connects the SCLK pin to the onboard SPI circuitry (see the Serial Port Interface (SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin
sets the duty cycle stabilizer. If the pin is left floating, the pin
is internally pulled up, setting the default condition to DCS
enabled. To disable the DCS, connect J1, Pin 1 to J1, Pin 2. If the
SPI port is in serial pin mode, connecting J1, Pin 2 to J1, Pin 3
connects the SDIO pin to the on-board SPI circuitry (see the
Serial Port Interface (SPI) section).
LE
VREF
CSB
TE
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
RBIAS
B
SO
VREF is set to 1.0 V by tying the SENSE pin to ground by adding
a jumper on Header J5 (Pin 1 to Pin 2). This causes the ADC to
operate in 2.0 V p-p full-scale range. To place the ADC in 1.0 V p-p
mode (VREF = 0.5 V), a jumper should be placed on Header J4.
A separate external reference option is also included on the evaluation board. To use an external reference, connect J6 (Pin 1 to Pin 2)
and provide an external reference at TP5. Proper use of the VREF
options is detailed in the Voltage Reference section.
RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.
CLOCK
O
The default clock input circuitry is derived from a simple baluncoupled circuit using a high bandwidth 1:1 impedance ratio balun
(T5) that adds a very low amount of jitter to the clock path. The
clock input is 50 Ω terminated and ac-coupled to handle singleended sine wave inputs. The transformer converts the single-ended
input to a differential signal that is clipped before entering the
ADC clock inputs. When the AD9627-11 input clock divider
is utilized, clock frequencies up to 625 MHz can be input into the
evaluation board through Connector S5.
ALTERNATIVE CLOCK CONFIGURATIONS
Two alternate clocking options are provided on the AD9627-11
evaluation board. The first option is to use an on-board crystal
oscillator (Y1) to provide the clock input to the part. To enable
this crystal, Resistor R8 (0 Ω) and Resistor R85 (10 kΩ) should
be installed, and Resistor R82 and Resistor R30 should be removed.
A second clock option is to use a differential LVPECL clock to
drive the ADC input using the AD9516 (U2). When using this
drive option, the AD9516 charge pump filter components need
to be populated (see Figure 77). Consult the AD9516 data sheet
for more information.
To configure the clock input from S5 to drive the AD9516
reference input instead of directly driving the ADC, the
following components need to be added, removed, and/or
changed.
1.
2.
PDWN
To enable the power-down feature, connect J7, shorting the
PDWN pin to AVDD.
Remove R32, R33, R99, and R101 in the default
clock path.
Populate C78 and C79 with 0.001 μF capacitors and
R78 and R79 with 0 Ω resistors in the clock path.
In addition, unused AD9516 outputs (one LVDS and one LVPECL)
are routed to optional Connector S8 through Connector S11 on
the evaluation board.
Rev. B | Page 49 of 72
AD9627-11
1.
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
This section provides a brief description of the alternative
analog input drive configuration using the AD8352. When
using this particular drive option, some additional components
need to be populated. For more details on the AD8352
differential driver, including how it works and its optional pin
settings, consult the AD8352 data sheet.
2.
3.
O
B
SO
LE
TE
To configure the analog input to drive the AD8352 instead of
the default transformer option, the following components need
to be added, removed, and/or changed for Channel A. For
Channel B the corresponding components should be changed.
Remove C1, C17, C18, and C117 in the default analog
input path.
Populate C8 and C9 with 0.1 μF capacitors in the analog
input path. To drive the AD8352 in the differential input
mode, populate the T10 transformer; the R1, R37, R39,
R126, and R127 resistors; and the C10, C11, and C125
capacitors.
Populate the optional amplifier output path with the
desired components including an optional low-pass filter.
Install 0 Ω resistors, R44 and R48. R43 and R47 should be
increased (typically to 100 Ω) to increase to 200 Ω the
output impedance seen by the AD8352.
Rev. B | Page 50 of 72
AIN+
AIN-
2
S2
1
R28
1
0 OHM
R121
RES0402
0 OHM
R120
57.6 OHM
R1
57.6 OHM
INA+
0.1U
C117
0.1U
C1
R2
INA+
0 OHM
0.1U
C47
INA-
0.1U
C9
T10
0 OHM
R54
P
1
3
S 2
DNP
R36
R29
5
4
5
4
S
ETC1-1-13
P
T1
1
2
3
1ADT1_1W
6T
2
3
T7
0 OHM
R110
CML
1
2
3
P
ETC1-1-13
S
T2
5
4
0.1U
C18
0.1U
C17
DEFAULT AMPLIFIER INPUT PAT H
4
5
ETC1-1-13
4.12K
0.1U
C11
0.1U
C10
DNP
R38
0 OHM
R37
R39
100 OHM
CML
RDN
RGN
RGP
5
16
VIP
RDP
R42
0 OHM
AMP+A
AMP-A
0 OHM
4
3
2
1
R40
6
ENB
15
B
W1
A
GND
Z1
VIN
8
VCC
9
10
C22
0.1U
GND
VON
11
12
C3
0.1U
33 OHM
R27
33 OHM
R26
C23
0.1U
C27
10U
0.001U
C16
0.001U
C12
AMPVDD
C2
0.1U
TE
7
GND
VOP
VCC
13
AMPVDD
AD8352
VCM
14
LE
0 OHM
R48
0 OHM
R44
C125
.3PF
B
SO
0 OHM
F
0.1U
R31
24.9 OHM
24.9 OHM
C8
R126
INA-
R127
10KOHM
R43
O
F
S1
2
33 OHM
R41
R5
OPTIONAL AMPL IFIER INPUT PATH
R4
10K OHM
57.6 OHM
R35
0 OHM
Figure 73. Evaluation Board Schematic, Channel A Analog Inputs
R47
F
33 OHM
Rev. B | Page 51 of 72
C5
4.7PF
120NH
DNP
120NH
DNP
2
2
L16
0 OHM
R49
180NH
DNP
180NH
DNP
0 OHM
R50
VIN+A
TP15
1
VIN-A
TP1
1 4
L17 1
IND0603
C4
18PF
DNP
1
IND0603
2
2
AVDD
AVDD
AMP+A
C139
12PF
DNP
AMP-A
Transformer/amp channel A
L15 1
IND0603
L14 1
IND0603
07054-073
AMPVDD
AD9627-11
SCHEMATICS
Figure 74. Evaluation Board Schematic, Channel B Analog Inputs
AIN+
AIN-
S4
S3
1
1
57.6 OHM
R52
57.6 OHM
R51
0 OHM
RES0402
R123
0 OHM
RES0402
R122
INB0.1U
C31
INB+
0.1U
C6
0.1U
C28
0 OHM
R67
INB-
4
5
S
3
2
1
0.1U
C38
0.1U
C39
.3PF
C128
0.1U
4
5
T8
4
5
6
P
T3
S
ETC1-1-13
3
2
1
3
2
1
ADT1_1WT
0 OHM
R111
CML
4
5
P
T4
S
ETC1-1-13
3
2
1
DNP
R133
0 OHM
R132
R6
0 OHM
0.1U
C82
0.1U
C7
100 OHM
4
3
2
1
VIN
RDN
RGN
RGP
RDP
5
16
VIP
R131
6
ENB
15
B
R94
A
GND
Z2
GND
R53
VCC
GND
VON
VOP
VCC
13
AD8352
VCM
14
AMPVDD
0 OHM
R95
CML
0 OHM
7
AMP+B
0 OHM
R96
AMP-B
8
10K OHM
9
10
11
12
C60
0.1U
C61
0.1U
C24
0.1U
C62
10U
AMPVDD
0.001U
C140
0.001U
C46
R73
L19 1
IND0603
L18 1
IND0603
C83
0.1U
33 OHM
R74
33 OHM
TE
LE
B
SO
DNP
DEFAULT AMPLIFIER INPUT PAT H
0 OHM
R55
T11
C51
P
ETC1-1-13
0 OHM
F
0.1U
R134
R135
INB+
24.9 OHM
24.9 OHM
R66
R128
C30
R129
OPTIONAL AMPL IFIER INPUT PATH
4.12K
R69
2
2
R70
R71
R68
F
R72
10KOHM
W2
57.6 OHM
O
F
0 OHM
33 OHM
33 OHM
Rev. B | Page 52 of 72
120NH
DNP
120NH
DNP
2
2
C84
4.7PF
L21 1
IND0603
C19
18PF
DNP
L20 1
IND0603
180NH
DNP
180NH
DNP
2
2
R80
R81
VIN+B
VIN-B
0 OHM
0 OHM
TP17
1
TP16
1
AMP-B
C29
12PF
DNP
AMP+B
AVDD
AVDD
07054-074
AMPVDD
AD9627-11
S6
SMA200U
P
ENC\
ENC
S5
SMA200U
P
1
1
R30
R7
R8
57.6 OHM
57.6 OHM
10K OHM
10K OHM
R85
R82
0 OHM
R3
0 OHM
R90
Figure 75. Evaluation Board Schematic, DUT Clock Input
0.001U
C77
4
5
0.1U
OPT_CLK-
3
S 2
T5
ETC1-1-13
P
1
6 T9
5
4
ADT1_1WT
1
2
3
C56
0.001U
C79
0 OHM
R33
0 OHM
R32
0.001U
C78
ALTCLK+
OPT_CLK-
ALTCLK-
OPT_CLK+
TE
LE
0.001U
C94
0.001U
C63
0.001U
OPT_CLK+
0.1U
0 OHM
R79
0 OHM
R101
0 OHM
R99
0 OHM
R78
R83
0.1U
C21
24.9 OHM
R84
0.1U
C20
24.9 OHM
C145
1
C64
B
SO
2
2
F
Rev. B | Page 53 of 72
2
O
TP2
CLK-
CLK+
07054-075
VS
AD9627-11
DNP
R34
0 OHM
1
S7
0 OHM
RES040 2
0 OHM
R12 5
RES040 2
VS_OUT_DR
C10 1
0.1U
C10 0
0.1U
0 OHM
R12 4
VCXO_CLK +
VCXO_CLK -
1
CLK IN
AD9516
0.1U
C10 4
R1 0
0.1U
C98
0.1U
C14 3
0.1U
C14 2
18PF
C80
VS
0.1U
C99
VS
SCL K
VCP
BYPASS_LD O
9
LF
CLKB
NC1
SCL K
14
15
16
0.1U
0.1U
C97
CLK
C96
VS_CLK_DIS T
12
VS_VC O
11
13
BYPASS_LD O
10
LF
SYNC B
REF_SE L
8
STATU S
CP
6
5
SYNC B
STATU S
VCP
LD
4
3
REFMO N
VS_PLL_ 1
2
7
CP
VCP
REFMO N
REF_SE L
TEST
1
TP18
TEST
1
TP19
1
R12
AGN D
VS
VS_OUT_D R
VS
OUT 6
GND_REF 59
39
38
OUT3 B
R88
200
36
35
34
33
OUT9 B
OUT 9
OUT8 B
OUT 8
VS
37
GND_OUT89_DI V
AGN D
VS
R92
200
R91
200
40
OUT 3
VS_OUT23_DI V
41
VS_OUT23_DR V
R86
200
ALTCLK +
42
OUT2 B
VS_OUT_D R
ALTCLK -
43
LVPECL
TO ADC
44
AGN D
1TP8
SYN C
OUT 2
45
46
47
0.001 U
C14 1
OUT6 N
GND_ES D
OUT7 B
OUT 7
OUT6 B
48
R9
TE
LE
U2
AD9516_64LFCS P
RSET_CLOCK 58
OPT_CLK-
OPT_CLK+
B
SO
O
VS
OUT0 56
OUT4
25
TES T
2
OUT0B 55
OUT4B
26
TP20
R89
OUT1 53
OUT5
28
LD
49.9 OHM
OUT1B 52
OUT5B
29
R11
REFINB 63
NC2
VS_OUT67_ 250
VS_OUT45_DI V
30
5.1K
18
REFIN 64
CSB
17
CSB_2
CP_RSET 62
NC3
19
VS_PLL_ 261
NC4
20
VS_PRESCALER 60
SDO
21
SDO
SDIO
22
SDI
VS_OUT01_DI V51
VS_OUT89_ 1
100 OHM
4.12K
VS_REF 57
PDB
24
PDB
RESETB
23
VS_OUT01_DRV 54
VS_OUT45_DRV
27
VS_OUT_DR
Figure 76. Evaluation Board Schematic, Optional AD9516 Clock Circuit
RESETB
VS_OUT67_ 149
VS_OUT89_ 2
Rev. B | Page 54 of 72
31
0.1U
C86
0.1U
C85
0.1U
C87
0.1U
C88
1
1
1
1
S8
S9
S10
S11
2
32
2
PAD
2
LVDS
LVPECL
OUTPUT
OUTPUT
07054-076
OUT6 P
AD9627-11
2
100 OHM
R75
CP
Figure 77. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input
BYPASS_LDO
VAL
R136
SYNC
S12
SMA200U P
2
1
R45
R98
VAL
C90
SEL
RES060 3
57.6 OH M
C89
SEL
R93
VAL
VAL
R137
SEL
C91
C144
SEL
LD
Charge Pump Filter
0.1U
C25
VAL
R97
3
2
A2
GND
A1
NL27WZ0
C92
SEL
4
Y1
Y2
VCC
R116
0 OH M
RES040 2
0 OH M
R117
RES040 2
4
5
RES040 2
LF
TP1
1
24.9 OH M
R87
6
VCC
OSCVECTRON_VS500
4
OUT2
3
GND
VS-500
5
OUT1
2
OUT_DISABLE
U25
SYNC
VS
10K OH M
RES040 2
0 OH M
RES040 2
R139
0 OH M
VCP
R114
VCP
RES040 2
REF_SEL
TE
LE
RES040 2
0 OH M
R104
1
FREQ_CTRL_V
33 OH M
R46
B
SO
6
R106
R108
1
10K OH M
10K OH M
C26
0.1U
R107
R109
U3
R100
10K OH M
VS
RES040 2
R76
200
RES040 2
RES040 2
Rev. B | Page 55 of 72
10K OH M
AC
RES040 2
O
10K OH M
R102
VCXO_CLK-
VCXO_CLK+
VS
PDB
VS
SYNCB
VS
RESETB
07054-077
VS
AD9627-11
RES040 2
10K OH M
R105
RES040 2
10K OH M
R103
RES040 2
Rev. B | Page 56 of 72
Figure 78. Evaluation Board Schematic, DUT
0 OHM
FD2B
D10A_MSB_
FD0B
SYNC
SPI_CSB
CLK-
CLK+
52
51
50
49
C137
0.001U
FD3B
57
C121
0.1U
C120
0.1U
TE
DVDD2
U1
SPI_SCLK/DFS
SPI_SDIO/DCS
AVDD3
NC
C109
0.1U
C40
0.1U
48
47
46
NC
C122
0.001U
C126
0.001U
SPI_SCLK
SPI_SDIO
AVDD
AVDD2
VIN+B
NC
C127
0.001U
R64
0 OHM
45
44
D0B_LSB
D1A
63
62
61
60
59
58
56
55
54
53
R57
22 ohm
9
10
11
12
13
14
15
16
RPAK8
DRVDD
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B_MSB
DCOB
DCOA
NC
NC
NC
D0A_LSB
64
AVDD
1
AVDD
VIN+B
D1B
DVDD
TP6
10KOHM
43
FD1B
PWR_SDFS
LE
AD9627-11
D5A
VIN-B
RBIAS
CML
DRVDD1
RES040
2
VIN-B
42
41
40
0.001U
DRGND1
R63
RES040
2
0.1U
CML
D7A
SENSE
VREF
VIN-A
C36
0.1U
C35
DRVDD
D4A
AVDD
C32
39
38
DVDD1
TP5
R112
VIN+A
TP3
D6A
1
VIN-A
37
FD3A
VIN+A
FD2A
AVDD1
FD1A
36
32
FD0A
35
31
AVDD
30
D9A
SMI_SDFS
29
D8A
J6 - INSTALL FOR EXTERNAL REFERENCE MODE
28
SMI_SCLK/PDWN
27
SMI_SDO/OEB
1
25
34
26
J5 - INSTALL FOR IV VREF/2V INPUT SPAN
RES0402
0 OHM
24
J4 - INSTALL FOR 0.5V VREF/IV INPUT SPAN
R62
23
C14
0.1U
33
RES040
2
B
SO
J8 - INSTALL FOR OUTPUT DISABLE
PWR_SCLK
PWR_SDO
FD3A
FD2A
FD1A
FD0A
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
R115
22
C15
1U
O
J7 - INSTALL FOR PDWN
RES040
2
RPAK8
0 OHM
22 ohm
R113
21
D2B
CLK+
DVDD
20
DRGND
CLK-
19
D3A
SPI_CSB
D2A
SYNC
18
3
4
5
6
7
8
9
8
7
6
5
4
3
2
1
1
DRVDD
10
11
12
13
14
15
16
2
DVDD
17
5
6
7
8
RPAK4
22 ohm
SPARE2
SPARE1
FD3B
FD2B
FD1B
FD0B
R58
C34
R59
RPAK8
4
3
2
1
0.001U
9
10
11
12
13
14
15
16
22 ohm
R60
RPAK8
22 ohm
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
0.1U
R61
RPAK8
22 ohm
C33
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
D2B
D1B
D0B
SPARE3
1
1
1
1
D10A
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D10B
D9B
D8B
D7B
D6B
D5B
D4B
D3B
D2A
D1A
D0A
SPARE6
SPARE5
SPARE4
DCOA
DCOB
07054-078
DRVDD
AD9627-11
Figure 79. Evaluation Board Schematic, Digital Output Interface
D4A
D3A
FD1B
FD0B
V_DIG
SPARE2
SPARE1
FD3B
FD2B
D2B
D1B
V_DIG
D0B
SPARE3
D4B
D3B
D6B
D5B
D10B
D9B
V_DIG
D8B
D7B
SPARE5
SPARE4
DCOA
DCOB
D2A
D1A
V_DIG
D0A
SPARE6
D6A
D5A
D10A
D9A
V_DIG
D8A
D7A
FD3A
FD2A
FD1A
FD0A
V_DIG
PWR_SDO
PWR_SDFS
PWR_SCLK
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U17
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
74VCX162244MTD
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
74VCX162244MTD
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
U16
74VCX162244MTD
V_DIG
V_DIG
V_DIG
OUT6P
OUT6N
J11
R140
VS
SDO
RESET B
SDI
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
RES040 2
0 OHM
R145
RES040 2
0 OHM
R144
OUT6N
R143
0 OHM
R142
RES040 2
10K OHM
A1
D1
C1
B2
A2
D2
C2
B3
A3
D3
C3
B4
A4
D4
C4
B5
A5
D5
C5
B10
A10
B6
A6
D6
C6
B7
A7
D7
C7
B8
A8
D8
C8
B9
A9
D9
C9
D10
C10
B1
J12
DG10
DG9
DG8
DG7
DG6
DG5
DG4
DG3
DG2
DG1
BG10
BG9
BG8
BG7
BG6
BG5
BG4
BG3
BG2
BG1
TYCO_HM-ZD
V_DIG
TE
SDO_OUT
SDFS_OUT
RES040 2
TP22
TEST
1
TP23 TEST
1
TP24 TEST
1
OUT6P
SYNC
SCLK_OUT
RES040 2
0 OHM
R141
VS
0 OHM
RES040 2
0 OHM
R119
RES040 2
TP21
TEST
1
LE
CSB
TYCO_HM-ZD
CHANNELB
B1
C10
D10
C9
D9
A9
B9
C8
D8
A8
B8
C7
D7
A7
B7
C6
D6
A6
B6
A10
B10
C5
D5
A5
B5
C4
D4
A4
B4
C3
D3
A3
B3
C2
D2
A2
B2
C1
D1
A1
CSB_ 2
SCLK
TYCO_HM-ZD
J10
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
B
SO
O
V_DIG
SDO_OUT
SDFS_OUT
SCLK_OU T
R118
CHANNELA
B1
C10
D10
C9
D9
A9
B9
C8
D8
A8
B8
C7
D7
A7
B7
C6
D6
A6
B6
A10
B10
C5
D5
A5
B5
C4
D4
A4
B4
C3
D3
A3
B3
C2
D2
A2
B2
C1
D1
A1
V_DIG
C65
0.1U
C66
0.1U
C72
0.1U
C67
0.1U
C73
0.1U
C68
0.1U
C74
0.1U
C69
0.1U
C75
0.1U
C70
0.1U
C76
0.1U
C71
0.1U
07054-079
DIGITAL/HSC-ADC-EVALCZ INTERFACE
10K OHM
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RES040 2
U15
R130
VAL
R77
Rev. B | Page 57 of 72
100 OHM
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AD9627-11
Figure 80. Evaluation Board Schematic, SPI Circuitry
CSB
SDO
SDI
SCLK
CSB
SCL K
CSB_2
V_DI G
R65
3
2
1
RES0402
A2
Y1
U8
A2
Y2
4
5
6
Y1
4
5
6
V_DIG
V_DI G
C81
0.1U
Y2
VCC
NC7WZ07P6X
RES0603
GND
A1
VCC
NC7WZ16P6X
GND
A1
10K OHM
R24
C13
0.1U
3
2
1
U7 1K OHM
R19
RES0603
1K OHM
R21
SPI_CSB
VS
J2 - JUMPER PINS 2 TO 3 FOR SPI OPERATION
JUMPER PINS 1 TO 2 FOR TWOS COMPLEMENT OUTPUT
J1 - JUMPER PINS 2 TO 3 FOR SPI OPERATION
JUMPER PINS 1 TO 2 FOR DCS ENABLE
3
J2
1
J1
RES0603
100K OHM
TE
R23
RES0603
100K OHM
R22
3
SPI_SCLK
SPI_SDI O
1
V_DI G
J21 - INSTALL JUMPER FOR SPI OPERATION
V_DIG
LE
R17
RES0603
1K OHM
R20
RES0603
100K OHM
V_DIG
SDO
V_DIG
B
SO
10K OHM
RES0402
10K OHM
Rev. B | Page 58 of 72
RES0402
R18
SDI
07054-080
O
AD9627-11
1
3
SMDC110F
C41
10U
Figure 81. Evaluation Board Schematic, Power Supply
Rev. B | Page 59 of 72
P4
P3
P2
P1
VCP
VS
DRVDDIN
SJ35
P4
6
P6
5
P5
4
P4
3
P3
2
P2
P3
P11
1
1
AVDDIN
CR7
OPTIONAL POWER SUPPLY INPUT S
POWER_JACK
2
2
1
L6
IND1210
10UH
10uh
L10
IND1210
L9
IND1210
10UH
1
2
2
2
C53
10U
C102
10U
C52
10U
C58
0.1U
C103
0.1U
C57
0.1U
CG6
CG5
CG 4
CB 2
1
1
2
PWR_IN
L11
10uh
IND1210
2
DRVDD
DVDD
AVDD
CR10
2
1
CR11
S2A_REC
T
2
C54
10U
C59
0.1U
1
1
TP13
1
TP12
1
TP10
1
1TP9
1TP4
GND TEST POINT S
V_DIG
C42
1U
SD
6
8 IN
7 IN2
ADP3334
C44
1U
CR12
2
3
VR3
PAD
GND
OUT
VR1
OUT 1
OUT2 2
FB 3
IN
5
TE
1
S2A_REC
T
LE
1
S2A_REC
T
B
SO
BNX-0 16
3 PSG
1 BIAS
CR8
R16
SHOT_RECT
261 OHM
F2
RES0603
F1
TP25
1
4
GND
1
J16
C43
1U
1
1.8
2.5
3.3
DR VDD
R1 3
76.8 K
107 K
140 K
2
147 K
94.0 K
78.7 K
R1 4
C93
0.001U
L3
IND1210
10uh
DRVDD SETTIN G
ADP3339
R13
R14
POWER INPU T
6V, 2A MA X
140 KOHM
S2A_REC
T
78.7 KOHM
AC
C45
1U
AVDDIN
1
L4
IND1210
10uh
2
DRVDDIN
07054-081
O
AD9627-11
PWR_IN
PWR_IN
Figure 82. Evaluation Board Schematic, Power Supply (Continued)
Rev. B | Page 60 of 72
VC P
SD
6
PA D
ADP333 9
VC P
5
C12 4
10 U
10 U
VS_OUT_DR
C11 9
GN D
OUT 1
OUT2 2
FB 3
VR2
1U
C13 6
1U
C13 4
VS
10 U
C11 8
0.001 U
C9 5
1
1
1U
10UH
2
VS
VC P
VS
VS_OUT_D R
L8
IND121 0
0.1 U
0.1 U
0.1 U
C10 8
1U
C12 9
3
IN
PA D
ADP333 9
0.1 U
C11 1
VR 4
TE
C11 2
C11 0
PWR_IN
LE
1
2
2
C13 1
L1 3
IND121 0
10uh
L1 2
IND121 0
10uh
B
SO
OU T
Power Supply ByPass Capacitors
1U
C13 2
8 IN
7 IN2
ADP3334
1U
IN
VR 6
C13 5
3
OU T
O
1U
C13 3
PA D
ADP333 9
4
GN D
1
4
GN D
1
IN
R2 5
R1 5
VR 5
140 KOH M
SJ36
78.7 KOH M
4
GN D
1
3
0.1 U
C11 5
OU T
0.1 U
C11 4
0.1 U
C11 3
1U
C13 0
1
2
0.1 U
C10 7
L1
IND121 0
10UH
0.1 U
C11 6
0.1 U
C10 5
AMPVD D
07054-082
PWR_IN
AD9627-11
SJ37
AD9627-11
07054-083
O
B
SO
LE
TE
EVALUATION BOARD LAYOUTS
Figure 83. Evaluation Board Layout, Primary Side
Rev. B | Page 61 of 72
07054-084
O
B
SO
LE
TE
AD9627-11
Figure 84. Evaluation Board Layout, Ground Plane
Rev. B | Page 62 of 72
07054-085
O
B
SO
LE
TE
AD9627-11
Figure 85. Evaluation Board Layout, Power Plane
Rev. B | Page 63 of 72
07054-086
O
B
SO
LE
TE
AD9627-11
Figure 86. Evaluation Board Layout, Power Plane
Rev. B | Page 64 of 72
07054-087
O
B
SO
LE
TE
AD9627-11
Figure 87. Evaluation Board Layout, Ground Plane
Rev. B | Page 65 of 72
07054-088
O
B
SO
LE
TE
AD9627-11
Figure 88. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. B | Page 66 of 72
07054-089
O
B
SO
LE
TE
AD9627-11
Figure 89. Evaluation Board Layout, Silkscreen, Primary Side
Rev. B | Page 67 of 72
07054-090
O
B
SO
LE
TE
AD9627-11
Figure 90. Evaluation Board Layout, Silkscreen, Secondary Side
Rev. B | Page 68 of 72
AD9627-11
BILL OF MATERIALS
Table 23. Evaluation Board Bill of Materials (BOM)1, 2
Item
1
2
Qty
1
55
3
1
Reference
Designator
AD9627-11CE_REVB
C1 to C3, C6, C7, C13,
C14, C17, C18, C20 to
C26, C32, C57 to C61,
C65 to C76, C81 to
C83, C96 to C101,
C103, C105, C107,
C108, C110 to C116,
C145
C80
4
2
C5, C84
5
10
6
13
7
10
8
1
C33, C35, C63, C93
to C95, C122, C126,
C127, C137
C15, C42 to C45,
C129 to C136
C27, C41, C52 to C54,
C62, C102, C118,
C119, C124
CR5
9
10
2
4
11
Package
PCB
C0402SM
Manufacturer
Analog Devices
Murata
GRM155R71C104KA88D
18 pF, COG, 50 V, 5% ceramic
capacitor, SMT 0402
4.7 pF, COG, 50 V, 5% ceramic
capacitor, SMT 0402
0.001 μF, X7R, 25 V, 10%
ceramic capacitor, SMT 0402
C0402SM
Murata
GJM1555C1H180JB01J
C0402SM
Murata
GJM1555C1H4R7CB01J
C0402SM
Murata
GRM155R71H102KA01D
1 μF, X5R, 25 V, 10% ceramic
capacitor, SMT 0805
10 μF, X5R, 10 V, 10% ceramic
capacitor, SMT 1206
C0805
Murata
GR4M219R61A105KC01D
Murata
GRM31CR61C106KC31L
SOT23
Avago Technologies
HSMS-2822-BLKG
CR6, CR9
CR7, CR10 to CR12
Schottky diode HSMS2822,
SOT23
LED RED, SMT, 0603, SS-type
50 V, 2 A diode
LED0603
DO_214AA
LNJ208R8ARA
S2A-TP
1
CR8
30 V, 3 A diode
DO_214AB
12
13
1
1
F1
F2
FLTHMURATABNX01
L1206
Panasonic
Micro Commercial
Components
Micro Commercial
Components
Murata
Tyco Raychem
14
2
J1, J2
HDR3
Samtec
TWS-1003-08-G-S
15
16
17
9
3
1
J4 to J9, J18, J19, J21
J10 to J12
J14
HDR2
TYCO_HM_ZD
CNBERG2X4H350LD
Samtec
Tyco
Samtec
TWS-102-08-G-S
6469169-1
TSW-104-08-T-D
18
19
20
21
22
1
10
1
1
3
J16
L1, L3, L4, L6, L8 to L13
P3
P4
R7, R30, R45
PWR_JACK1
1210
PTMICRO6
PTMICRO4
R0603
Cui Stack
Panasonic
Weiland Electric, Inc.
Weiland Electric, Inc.
NIC Components
PJ-002A
EXC-CL3225U1
Z5.531.3625.0
Z5.531.3425.0
NRC06F57R6TRF
23
27
R0402SM
NIC Components
NRC04ZOTRF
24
2
R2, R3, R4, R32, R33,
R42, R64, R67, R69,
R90, R96, R99, R101,
R104, R110 to R113,
R115, R119, R121,
R123, R141 to R145
R13, R25
R0603
NIC Components
NRC06F1403TRF
25
2
R14, R15
R0603
NIC Components
NRC06F7872TRF
26
1
R16
R0603
NIC Components
NRC06F2610TRF
27
3
R17, R22, R23
R0603
NIC Components
NRC06F1003TRF
28
7
R18, R24, R63, R65,
R82, R118, R140
R0402SM
NIC Components
NRC04F1002TRF
O
B
SO
LE
C1206
EMI filter
6.0 V, 3.0 A, trip current
resettable fuse
3-pin, male, single row,
straight header
2-pin, male, straight header
Interface connector
8-pin, male, double row,
straight header
DC power jack connector
10 μH, 2 A bead core, 1210
6-terminal connector
4-terminal connector
57.6 Ω, 0603, 1/10 W,
1% resistor
0 Ω, 1/16 W, 5% resistor
140 kΩ, 0603, 1/10 W,
1% resistor
78.7 kΩ, 0603, 1/10 W,
1% resistor
261 Ω, 0603, 1/10 W,
1% resistor
100 kΩ, 0603, 1/10 W,
1% resistor
10 kΩ, 0402, 1/16 W,
1% resistor
Mfg. Part Number
TE
Description
PCB
0.1 μF, 16 V ceramic
capacitor, SMT 0402
Rev. B | Page 69 of 72
SK33-TP
BNX016-01
NANOSMDC150F-2
AD9627-11
9
31
5
R26, R27, R43, R46,
R47, R70, R71, R73,
R74
R57, R59 to R62
32
1
R58
33
1
R76
34
4
S2, S3, S5, S12
35
36
37
38
39
40
1
5
1
1
1
1
SJ35
T1 to T5
U1
U2
U3
U7
41
42
43
44
45
46
47
48
1
3
2
1
1
2
1
2
U8
U15 to U17
VR1, VR2
VR3
VR4
VR5, VR6
Y1
Z1, Z2
2
Manufacturer
NIC Components
Mfg. Part Number
NRC06F1001TRF
R0402SM
NIC Components
NRC04J330TRF
R_742
CTS Corporation
742C163220JPTR
RES_ARRY
CTS Corporation
742C083220JPTR
R0402SM
NIC Components
NCR04F2000TRF
SMA_EDGE
Emerson Network Power
142-0701-201
SLDR_PAD2MUYLAR
TRAN6B
LFCSP64-9X9-9E
LFCSP64-9X9
SC70_6
SC70_6
NIC Components
M/A-COM
Analog Devices
Analog Devices
Fairchild Semiconductor
Fairchild Semiconductor
NRC10ZOTRF
MABA-007159-000000
AD9627BCPZ11
AD9516-4BCPZ
NC7WZ04P6X_NL
NC7WZ07P6X_NL
SC70_6
TSOP48_8_1MM
LFCSP8-3X3
SOT223-HS
SOT223-HS
SOT223-HS
OSC-CTS-CB3
LFCSP16-3X3-PAD
Fairchild Semiconductor
Fairchild Semiconductor
Analog Devices
Analog Devices
Analog Devices
Analog Devices
Valpey Fisher
Analog Devices
NC7WZ16P6X_NL
74VCX16244MTDX_NL
ADP3334ACPZ
ADP3339AKCZ-1.8
ADP3339AKCZ-5.0
ADP3339AKCZ-3.3
VFAC3-BHL
AD8352ACPZ
This bill of materials is RoHS compliant.
The bill of materials lists only those items that are normally installed in the default condition. Items that are not installed are not included in the BOM.
O
1
22 Ω, 16-pin, 8-resistor,
resistor array
22 Ω, 8-pin, 4-resistor,
resistor array
200 Ω, 0402, 1/16 W,
1% resistor
SMA, inline, male,
coaxial connector
0 Ω, 1/8 W, 1% resistor
Balun
IC, AD9627-11
Clock distribution, PLL IC
Dual inverter IC
Dual buffer IC,
open-drain circuits
UHS dual buffer IC
16-bit CMOS buffer IC
Adjustable regulator
1.8 V high accuracy regulator
5.0 V high accuracy regulator
3.3 V high accuracy regulator
Oscillator clock, VFAC3
High speed IC, op amp
Package
R0603
TE
30
Description
1 kΩ, 0603, 1/10 W,
1% resistor
33 Ω, 0402, 1/16 W,
5% resistor
B
SO
Qty
3
LE
Reference
Designator
R19, R20, R21
Item
29
Rev. B | Page 70 of 72
AD9627-11
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
64 1
49
PIN 1
INDICATOR
48
PIN 1
INDICATOR
8.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
0.22 MIN
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
02-23-2010-B
0.05 MAX
0.02 NOM
TE
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
16
17
33
32
TOP VIEW
1.00
0.85
0.80
7.55
7.50 SQ
7.45
EXPOSED PAD
(BOTTOM VIEW)
ORDERING GUIDE
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
O
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
B
SO
Model1
AD9627ABCPZ11-150
AD9627ABCPZ11-105
AD962711-150EBZ
AD962711-105EBZ
LE
Figure 91. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-6)
Dimensions shown in millimeters
Rev. B | Page 71 of 72
Package Option
CP-64-6
CP-64-6
AD9627-11
O
B
SO
LE
TE
NOTES
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07054-0-5/10(B)
Rev. B | Page 72 of 72