ESMT M24L48512SA-70BIG 4-mbit (512k x 8) pseudo static ram Datasheet

ESMT
PSRAM
M24L48512SA
4-Mbit (512K x 8)
Pseudo Static RAM
Features
•
•
•
•
•
•
Advanced low power architecture
High speed: 55 ns, 60 ns and 70 ns
Wide voltage range: 2.7V to 3.6V
Typical active current: 1mA @ f = 1 MHz
Low standby power
Automatic power-down when deselected
Functional Description
The M24L48512SA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 8 bits. Easy
memory expansion is provided by an active LOW Chip
Enable( CE ) and active LOW Output Enable ( OE ).This device
has an automatic power-down feature that reduces power
consumption dramatically when deselected. Writing to the
device is accomplished by taking Chip Enable ( CE ) and Write
Enable ( WE ) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).Reading from the device is
accomplished by asserting the Chip Enable ( CE ) and Output
Enable ( OE ) inputs LOW while forcing Write Enable ( WE )
HIGH . Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O
pins. The eight input/output pins (I/O0 through I/O7) are placed
in a high-impedance state when the device is deselected ( CE
HIGH), the outputs are disabled ( OE HIGH), or during write
operation ( CE LOW and WE LOW). See the Truth Table
for a complete description of read and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
1/12
ESMT
M24L48512SA
Pin Configuration[2]
Product Portfolio
Power Dissipation
VCC Range(V)
Product
Min.
Typ.
Speed
(ns)
Max.
Operating, ICC (mA)
f = 1 MHz
Typ.[3]
Max.
1
5
55
M24L48512SA
2.7
3.0
3.6
60
70
Standby, ISB2 (µA)
f = fMAX
Typ.[3]
Max.
14
22
8
15
Typ.[3]
Max.
17
40
Notes:
2. NC “no connect”—not connected internally to the die.
3.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ)
and TA = 25°C.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
2/12
ESMT
M24L48512SA
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to Ground Potential ................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[4, 5, 6] .......................................−0.4V to 3.7V
DC Input Voltage[4, 5, 6] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Ambient Temperature (TA)
VCC
Extended
−25°C to +85°C
2.7V to 3.6V
Industrial
−40°C to +85°C
2.7V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter
VCC
VOH
VOL
VIH
VIL
IIX
IOZ
ICC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Test Conditions
IOH = −0.1 mA
-55, 60, 70
Typ.[3]
3.0
Min.
2.7
Max.
3.6
VCC – 0.4
Unit
V
V
IOL = 0.1 mA
0.4
V
0.8 * VCC
VCC + 0.4
V
-0.4
0.4
V
GND ≤ VIN ≤ Vcc
-1
+1
µA
GND ≤ VOUT ≤ Vcc, Output
Disabled
-1
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V,
IOUT = 0 mA,
CMOS level
+1
µA
14 for 55ns speed
14 for 60 ns speed
8 for 70 ns speed
22 for 55 ns speed
22 for 60 ns speed
15 for 70 ns speed
mA
1 for all speed
5 for all speeds
ISB1
Automatic CE
Power-down
Current —CMOS
Inputs
CE ≥ VCC − 0.2V, VIN ≥ VCC
− 0.2V, VIN ≤ 0.2V, f =
fMAX(Address and Data Only),
f = 0, VCC = 3.6V
150
250
µA
ISB2
Automatic CE
Power-down
Current —CMOS
Inputs
CE ≥ VCC − 0.2V, VIN ≥ VCC
− 0.2V or VIN ≤ 0.2V, f = 0, VCC
= 3.6V
17
40
µA
Capacitance[7]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Max.
8
8
Unit
pF
pF
Notes:
4.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.
5.VIL(MIN) = –0.5V for pulse durations less than 20 ns.
6.Overshoot and undershoot specifications are characterized and are not 100% tested.
7.Tested initially and after design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
3/12
ESMT
M24L48512SA
Thermal Resistance[7]
Parameter
Description
θJA
Thermal Resistance (Junction to Ambient)
θJC
Thermal Resistance (Junction to Case)
Test Conditions
VFBGA
Unit
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
55
°C/W
17
°C/W
AC Test Loads and Waveforms
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics (Over the Operating Range)[8]
Parameter
Description
Read Cycle
tRC
tAA
tOHA
tACE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
tDOE
OE LOW to Data Valid
–55
Min.
55[12]
OE LOW to Low Z[9, 10]
tHZOE
OE HIGH to High Z[9, 10]
tLZCE
CE LOW
Min.
5
10
70
25
5
25
2
70
60
25
Max.
70
8
5
Min.
60
55
tHZCE
–70
Max.
60
55
CE LOW
tLZOE
–60
Max.
35
5
25
2
Unit
ns
ns
ns
ns
ns
ns
25
5
ns
ns
25
25
25
ns
0
0
10
ns
CE HIGH
tSK
Address Skew
Write Cycle[11]
tWC
Write Cycle Time
tSCE
CE LOW
55
45
60
45
70
60
ns
ns
tAW
tHA
45
0
45
0
55
0
ns
ns
[12]
Address Set-up to Write End
Address Hold from Write End
Notes:
8. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V
to V CC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance.
9. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
10. High-Z and Low-Z parameters are characterized and are not 100% tested.
11. The internal write time of the memory is defined by the overlap of WE , CE = VIL. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be
referenced to the edge of the signal that terminates write.
12. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
4/12
ESMT
M24L48512SA
Switching Characteristics (Over the Operating Range)[8] (continued)
Parameter
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
Max.
25
0
Min.
0
40
5
–70
Max.
25
0
25
WE LOW to High Z[9, 10]
WE HIGH to Low Z[9, 10]
–60
–55
Min.
0
40
Min.
0
45
25
5
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [12, 13, 14]
Read Cycle 2 ( OE Controlled) [12, 14]
Notes:
13.Device is continuously selected. OE , CE = VIL.
14. WE is HIGH for Read Cycle.
Elite Semiconductor Memory Technology Inc.
Unit
ns
ns
25
0
25
5
Max.
Publication Date: Jul. 2008
Revision: 1.1
5/12
ns
ns
ns
ns
ESMT
M24L48512SA
Switching Waveforms (continued)
Write Cycle No. 1( WE Controlled) [10, 11, 15, 16, 17]
Switching Waveforms (continued)
Write Cycle 2 ( CE Controlled) [10, 11, 15, 16, 17]
Notes:
15.Data I/O is high impedance if OE ≥ VIH.
16.If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state.
17.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
6/12
ESMT
M24L48512SA
Switching Waveforms (continued)
Write Cycle 3 ( WE Controlled, OE LOW)[16, 17]
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
7/12
ESMT
M24L48512SA
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during
15μs shown as in Avoidable timing 1 or toggle CE to high (≧tRC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
≧15μ s
CE
WE
＜ tRC
Address
Avoidable Timing 1
≧15μ s
CE
WE
≧ tRC
Address
Avoidable Timing 2
≧15μ s
CE
≧ tRC
WE
＜ tRC
Address
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
8/12
ESMT
M24L48512SA
Truth Table[18]
CE
H
X
L
L
L
OE
X
X
L
X
H
WE
X
X
H
L
H
I/O0–I/O7
Mode
High Z
High Z
Data Out
Data in
High Z
Power-down
Power-down
Read
Write
Selected, Outputs Disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Ordering Information
Speed (ns)
55
60
70
55
60
70
Ordering Code
M24L48512SA-55BEG
M24L48512SA -60BEG
M24L48512SA -70BEG
M24L48512SA-55BIG
M24L48512SA-60BIG
M24L48512SA-70BIG
Package Type
36-Lead VFBGA (6 x 8 x 1 mm) (pb-free)
36-Lead VFBGA (6 x 8 x 1 mm) (pb-free)
36-Lead VFBGA (6 x 8 x 1 mm) (pb-free)
36-Lead VFBGA (6 x 8 x 1 mm) (pb-free)
36-Lead VFBGA (6 x 8 x 1 mm) (pb-free)
36-Lead VFBGA (6 x 8 x 1 mm) (pb-free)
Operating Range
Extended
Extended
Extended
Industrial
Industrial
Industrial
Note:
18.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
9/12
ESMT
M24L48512SA
Package Diagram
36-Lead VFBGA (6 x 8 x 1 mm)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
10/12
ESMT
M24L48512SA
Revision History
Revision
Date
1.0
2007.07.19
Original
2008.07.04
1. Move Revision History to the last
2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V
3. Add Industrial grade
4. Add Avoid timing
1.1
Elite Semiconductor Memory Technology Inc.
Description
Publication Date: Jul. 2008
Revision: 1.1
11/12
ESMT
M24L48512SA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time of
publication. ESMT assumes no responsibility for any error in this document, and
reserves the right to change the products or specification in this document without
notice.
The information contained herein is presented only as a guide or examples for the
application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but not
limited to, life support devices or system, where failure or abnormal operation may
directly affect human lives or cause physical injury or property damage. If products
described here are to be used for such kinds of application, purchaser must do its
own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
12/12