bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
SBS 1.1-Compliant Gas Gauge and Protection Enabled With Impedance Track™ and
External Battery Heater Control
Check for Samples: bq34z651
FEATURES
APPLICATIONS
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Next Generation Patented Impedance Track™
Technology Accurately Measures Available
Charge in Li-Ion and Li-Polymer Batteries
– Better Than 1% Error Over the Lifetime of
the Battery
Supports the Smart Battery Specification
SBS v1.1
Flexible Configuration for 2-Series to 4-Series
Li-Ion and Li-Polymer Cells
Battery Temperature Heater Control
Powerful 8-Bit RISC CPU with Ultralow Power
Modes
Full Array of Programmable Protection
Features
– Voltage, Current, and Temperature
Satisfies JEITA Guidelines
Added Flexibility to Handle More Complex
Charging Profiles
Lifetime Data Logging
Drives 3-, 4-, and 5-Segment LED Display for
Battery-Pack Conditions
Supports SHA-1 Authentication
Complete Battery Protection and Gas Gauge
Solution in One Package
Available in a 44-Pin TSSOP (DBT) package
Notebook PCs
Medical and Test Equipment
Portable Instrumentation
DESCRIPTION
The bq34z651 SBS-compliant gas gauge and
protection IC, incorporating patented Impedance
Track™ technology, is a single IC solution designed
for battery-pack or in-system installation. The
bq34z651 measures and maintains an accurate
record of available charge in Li-Ion or Li-Polymer
batteries using its integrated high-performance
analog peripherals. The bq34z651 monitors capacity
change, battery impedance, open-circuit voltage, and
other critical parameters of the battery pack, which
reports the information to the system host controller
over a serial-communication bus. Together with the
integrated analog front-end (AFE) short-circuit and
overload protection, the bq34z651 maximizes
functionality and safety while minimizing external
component count, cost, and size in smart battery
circuits.
The implemented Impedance Track gas gauging
technology continuously analyzes the battery
impedance, resulting in superior gas-gauging
accuracy. This enables remaining capacity to be
calculated with discharge rate, temperature, and cell
aging—all accounted for during each stage of every
cycle with high accuracy.
Table 1. AVAILABLE OPTIONS
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE (1)
44-PIN TSSOP (DBT) Tube
44-PIN TSSOP (DBT) Tape and Reel
bq34z651DBT (2)
bq34z651DBTR (3)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
A single tube quantity is 40 units.
A single reel quantity is 2000 units.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
THERMAL INFORMATION
bq34z651
THERMAL METRIC (1)
TSSOP
UNITS
44 PINS
θJA, High K
Junction-to-ambient thermal resistance (2)
60.9
(3)
θJC(top)
Junction-to-case(top) thermal resistance
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
θJC(bottom)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
15.3
(4)
30.2
(5)
Junction-to-case(bottom) thermal resistance
0.3
(6)
(7)
°C/W
27.2
n/a
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SYSTEM PARTITIONING DIAGRAM
PACK+
VSS
VCC
BAT
PACK
PRES
CHG
DSG
GPOD
PMS
ZVCHG
SAFE
PFIN
LED5
LED3
LED4
LED1
LED2
HEATER
RBI
DISP
LED Display
Fuse Blow
Detection & Logic
Oscillator
PreCharge FET
& GPOD Drive
N Channel FET
Drive
Power Mode
Control
MSRT
RESET
SMBD
SMB 1.1
System Control
AFE HW Control
Watchdog
ALERT
SMBC
Voltage
Measurement
Data Flash
Memory
Cell Voltage
Multiplexer
VCELL+
+
VC1
VC2
JEITA and
Enhanced
Charging
Algorithm
SHA-1
Authentication
Over
Temperature
Protection
Over & Under
Voltage
Protection
VC3
Impedance
Track™ Gas
Gauging
Cell Balancing
+
+
VC4
+
VC1
VDD
VC2
OUT
VC3
CD
VC4
GND
bq294xx
VC5
Temperature
Measurement
Over Current
Protection
HW Over
Current & Short
Circuit Protection
Coulomb
Counter
REG33
Regulators
PACK–
Copyright © 2011, Texas Instruments Incorporated
ASRP
ASRN
GSRN
GSRP
TS2
TS1
TOUT
REG25
RSNS
5 mΩ – 20 mΩ typ
3
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
PACKAGE PINOUT DIAGRAM
DBT PACKAGE
(TOP VIEW)
4
DSG
1
44
CHG
PACK
2
43
BAT
VCC
3
42
VC1
ZVCHG
4
41
VC2
GPOD
5
40
VC3
PMS
6
39
VC4
VSS
7
38
VC5
REG33
8
37
ASRP
TOUT
9
36
ASRN
VCELL+
10
35
RESET
ALERT
11
34
VSS
NC
12
33
RBI
TS1
13
32
REG25
TS2
14
31
VSS
PRES
15
30
MRST
PFIN
16
29
GSRN
SAFE
17
28
GSRP
SMBD
18
27
LED5
NC
19
26
LED4
SMBC
20
25
LED3
DISP
21
24
LED2
VSS
22
23
LED1
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
(1)
I/O (1)
DESCRIPTION
NO.
NAME
1
DSG
O
2
PACK
IA, P
3
VCC
P
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
ensure device supply either from battery stack or battery pack input.
4
ZVCHG
O
P-channel pre-charge FET gate drive
5
GPOD
OD
6
PMS
I
Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET
connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at
CHG pin.
7
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
8
REG33
P
3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS.
9
TOUT
P
Thermistor bias supply output
10
VCELL+
—
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
VSS.
11
ALERT
I/OD
12
NC
—
Not used—leave floating.
13
TS1
IA
1st thermistor voltage input connection to monitor temperature
14
TS2
IA
2nd thermistor voltage input connection to monitor temperature
15
PRES
I
Active low input to sense system insertion. Typically requires additional ESD protection.
16
PFIN
I
Active low input to detect secondary protector status, and to allow the bq34z651 to report the status
of the 2nd-level protection input
17
SAFE
O
Active high output to enforce additional level of safety protection; e.g., fuse blow
18
SMBD
I/OD
High-side N-channel discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown
mode.
High voltage general purpose open drain output. It can be configured to be used in pre-charge
condition.
Alert output. In case of short circuit condition, overload condition and watchdog timeout, this pin will
be triggered.
SMBus data open-drain bidirectional pin used to transfer address and data to and from the
bq34z651
19
NC
—
20
SMBC
I/OD
SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the bq34z651
21
DISP
I/OD
Display control for the LEDs. This pin is typically connected to VCC via a 100-kΩ resistor and a
push button switch connected to VSS.
22
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
23
LED1
I
LED1 display segment that drives an external LED depending on the firmware configuration
24
LED2
I
LED2 display segment that drives an external LED depending on the firmware configuration
25
LED3
I
LED3 display segment that drives an external LED depending on the firmware configuration
26
LED4
I
LED4 display segment that drives an external LED depending on the firmware configuration
27
LED5
I
LED5 display segment that drives an external LED depending on the firmware configuration
28
GSRP
IA
Coulomb counter differential input. Connect to one side of the sense resistor.
29
GSRN
IA
Coulomb counter differential input. Connect to one side of the sense resistor.
30
MRST
I
Master reset input that forces the device into reset when held low. Must be held high for normal
operation. Connect to RESET for correct operation of device.
31
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
32
REG25
P
2.5-V regulator output. Connect at least a 1-mF capacitor to REG25 and VSS.
33
RBI
P
RAM/Register backup input. Connect a capacitor to this pin and VSS to protect loss of
RAM/Register data in case of short circuit condition.
Not used—leave floating.
34
VSS
P
Negative supply voltage input. Connect all VSS pins together for operation of device.
35
RESET
O
Reset output. Connect to MSRT.
36
ASRN
IA
Short circuit and overload detection differential input. Connect to sense resistor.
37
ASRP
IA
Short circuit and overload detection differential input. Connect to sense resistor.
I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
Copyright © 2011, Texas Instruments Incorporated
5
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O (1)
DESCRIPTION
NO.
NAME
38
VC5
IA, P
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell
stack.
39
VC4
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
negative voltage of the second lowest cell in cell stack.
40
VC3
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in
cell stack and the negative voltage of the second highest cell in 4-series cell applications.
41
VC2
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell
and the negative voltage of the highest cell in 4-series cell applications. Connect to VC3 in 2-series
cell stack applications.
42
VC1
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell
stack in 4-series cell applications. Connect to VC2 in 3-series or 2-series cell stack applications.
43
BAT
I, P
44
CHG
O
Battery stack voltage sense input
High-side N-channel charge FET gate drive
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature (unless otherwise noted)
(1)
PIN
VSS
Supply voltage range
VIN
Input voltage range
UNIT
BAT, VCC
–0.3 V to 34 V
PACK, PMS
–0.3 V to 34 V
VC(n) – VC(n+1); n = 1, 2, 3, 4
–0.3 V to 8.5 V
VC1, VC2, VC3, VC4
–0.3 V to 34 V
VC5
–0.3 V to 1 V
PFIN, SMBD, SMBC. LED1, LED2, LED3, LED4,
LED5, DISP
–0.3 V to 6 V
TS1, TS2, SAFE, VCELL+, PRES, ALERT
–0.3 V to V(REG25) + 0.3 V
MRST, GSRN, GSRP, RBI
–0.3 V to V(REG25) + 0.3 V
–1 V to 1 V
ASRN, ASRP
VOUT
Output voltage range
DSG, CHG, GPOD
–0.3 V to 34 V
ZVCHG
–0.3 V to V(BAT)
–0.3 V to 6 V
TOUT, ALERT, REG33
RESET
–0.3 V to 7 V
REG25
–0.3 V to 2.75 V
ISS
Maximum combined sink current for input
pins
TA
Operating free-air temperature range
–40°C to 85°C
TF
Functional temperature
–40°C to 100°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
PRES, PFIN, SMBD, SMBC, LED1, LED2, LED3,
LED4, LED5
50 mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
PIN
MIN
VSS
Supply voltage
VCC, BAT
4.5
V(STARTUP)
Minimum startup voltage
VCC, BAT, PACK
5.5
6
NOM
MAX
UNIT
25
V
V
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued)
Over operating free-air temperature range (unless otherwise noted)
PIN
VIN
Input Voltage Range
MIN
NOM
MAX
UNIT
VC(n) – VC(n+1); n = 1,2,3,4
0
5
V
VC1, VC2, VC3, VC4
0
VSUP
V
VC5
0
0.5
V
–0.5
0.5
V
V
ASRN, ASRP
PACK, PMS
0
25
V(GPOD)
Output Voltage Range
GPOD
0
25
V
A(GPOD)
Drain Current (1)
GPOD
1
mA
C(REG25)
2.5-V LDO Capacitor
REG25
1
µF
C(REG33)
3.3-V LDO Capacitor
REG33
2.2
µF
C(VCELL+)
Cell Voltage Output Capacitor
VCELL+
0.1
µF
1
kΩ
C(PACK)
(1)
(2)
PACK input block resistor
(2)
PACK
Use an external resistor to limit the current to GPOD to 1 mA in high voltage application.
Use an external resistor to limit the in-rush current PACK pin required.
Copyright © 2011, Texas Instruments Incorporated
7
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
I(NORMAL)
Firmware running
I(SLEEP)
Sleep Mode
I(SHUTDOWN)
550
µA
CHG FET on; DSG FET on
124
µA
CHG FET off; DSG FET on
90
µA
CHG FET off; DSG FET off
52
µA
1
µA
1
µA
1.25
10
mV
V (WAKE) = 1 mV;
I(WAKE)= 0, RSNS1 = 0, RSNS0 = 1;
–0.7
0.7
V(WAKE) = 2.25 mV;
I(WAKE) = 1, RSNS1 = 0, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
–0.8
0.8
V(WAKE) = 4.5 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
–1.0
1.0
V(WAKE) = 9 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
–1.4
1.4
Shutdown Mode
0.1
SHUTDOWN WAKE; TA = 25°C (unless otherwise noted)
I(PACK)
Shutdown exit at VSTARTUP threshold
SRx WAKE FROM SLEEP; TA = 25°C (unless otherwise noted)
V(WAKE)
V(WAKE_ACR)
Positive or negative wake threshold
with 1.00 mV, 2.25 mV, 4.5 mV and 9
mV programmable options
Accuracy of V(WAKE)
mV
V(WAKE_TCO)
Temperature drift of V(WAKE) accuracy
0.5
%/°C
t(WAKE)
Time from application of current and
wake of bq34z651
1
10
ms
WATCHDOG TIMER
tWDTINT
Watchdog start up detect time
250
500
1000
ms
tWDWT
Watchdog detect time
50
100
150
µs
2.41
2.5
2.59
V
2.5V LDO; I(REG33OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG25)
Regulator output voltage
4.5 < VCC or BAT < 25 V;
I(REG25OUT) ≤ 16 mA;
TA = –40°C to 100°C
ΔV(REG25TEMP)
Regulator output change with
temperature
I(REG25OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG25LINE)
Line regulation
5.4 < VCC or BAT < 25 V;
I(REG25OUT) = 2 mA
ΔV(REG25LOAD)
Load Regulation
I(REG25MAX)
Current Limit
±0.2
%
3
10
0.2 mA ≤ I(REG25OUT) ≤ 2 mA
7
25
0.2 mA ≤ I(REG25OUT) ≤ 16 mA
25
50
5
40
75
mA
3
3.3
3.6
V
Drawing current until
REG25 = 2 V to 0 V
mV
mV
3.3V LDO; I(REG25OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG33)
Regulator output voltage
4.5 < VCC or BAT < 25 V;
I(REG33OUT) ≤ 25 mA;
TA = –40°C to 100°C
ΔV(REG33TEMP)
Regulator output change with
temperature
I(REG33OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG33LINE)
Line regulation
5.4 < VCC or BAT < 25 V;
I(REG33OUT) = 2 mA
ΔV(REG33LOAD)
Load Regulation
I(REG33MAX)
Current Limit
±0.2
3
%
10
0.2 mA ≤ I(REG33OUT) ≤ 2 mA
7
17
0.2 mA ≤ I(REG33OUT) ≤ 25 mA
40
100
100
145
Drawing current until REG33 = 3 V
25
Short REG33 to VSS, REG33 = 0 V
12
65
mV
mV
mA
THERMISTOR DRIVE
V(TOUT)
RDS(on)
8
Output voltage
I(TOUT) = 0 mA; TA = 25°C
TOUT pass element resistance
I(TOUT) = 1 mA; RDS(on) = (V(REG25) –
V(TOUT) )/ 1 mA; TA = –40°C to 100°C
V(REG25)
50
V
100
Ω
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.4
V
LED OUTPUTS
VOL
Output low voltage
LED1, LED2, LED3, LED4, LED5
VCELL+ HIGH VOLTAGE TRANSLATION
V(VCELL+OUT)
V(VCELL+REF)
Translation output
VC(n) – VC(n+1) = 0 V;
TA = –40°C to 100°C
0.950
0.975
1
VC(n) – VC(n+1) = 4.5 V;
TA = –40°C to 100°C
0.275
0.3
0.375
Internal AFE reference voltage;
TA = –40°C to 100°C
0.965
0.975
0.985
V(VCELL+PACK)
Voltage at PACK pin;
TA = –40°C to 100°C
0.98 ×
V(PACK)/18
V(PACK)/18
1.02 ×
V(PACK)/18
V(VCELL+BAT)
Voltage at BAT pin;
TA = –40°C to 100°C
0.98 ×
V(BAT)/18
V(BAT)/18
1.02 ×
V(BAT)/18
CMMR
K
Common mode rejection ratio
Cell scale factor
VCELL+
40
V
dB
K= {VCELL+ output (VC5=0 V; VC4=4.5
V) – VCELL+ output (VC5 = 0 V; VC4 =0
V)}/4.5
0.147
0.150
0.153
K= {VCELL+ output (VC2 = 13.5 V; VC1
= 18 V) – VCELL+ output
(VC5 = 13.5 V; VC1 = 13.5 V)}/4.5
0.147
0.150
0.153
I(VCELL+OUT)
Drive Current to VCELL+ capacitor
VC(n) – VC(n+1) = 0 V; VCELL+ = 0 V;
TA = –40°C to 100°C
12
18
V(VCELL+O)
CELL offset error
CELL output (VC2 = VC1 = 18 V) – CELL
output (VC2 = VC1 = 0 V)
–18
–1
18
mV
IVCnL
VC(n) pin leakage current
VC1, VC2, VC3, VC4, VC5 = 3 V
–1
0.01
1
μA
RDS(on) for internal FET switch at
VDS = 2 V; TA = 25°C
200
400
600
Ω
μA
CELL BALANCING
RBAL
Internal cell balancing FET resistance
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
V(OL)
V(SCC)
V(SCD)
OL detection threshold voltage
accuracy
SCC detection threshold voltage
accuracy
SCD detection threshold voltage
accuracy
tda
Delay time accuracy
tpd
Protection circuit propagation delay
VOL = 25 mV (min)
15
25
35
VOL = 100 mV; RSNS = 0, 1
90
100
110
VOL = 205 mV (max)
185
205
225
V(SCC) = 50 mV (min)
30
50
70
V(SCC) = 200 mV; RSNS = 0, 1
180
200
220
V(SCC) = 475 mV (max)
428
475
523
V(SCD) = –50 mV (min)
–30
–50
–70
V(SCD) = –200 mV; RSNS = 0, 1
–180
–200
–220
V(SCD) = –475 mV (max)
–428
–475
–523
mV
mV
mV
±15.25
μs
50
μs
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON)
DSG pin output on voltage
V(DSGON) = V(DSG) – V(PACK);
V(GS) = 10 MΩ; DSG and CHG on;
TA = –40°C to 100°C
8
12
16
V
V(CHGON)
CHG pin output on voltage
V(CHGON) = V(CHG) – V(BAT);
V(GS) = 10 MΩ; DSG and CHG on;
TA = –40°C to 100°C
8
12
16
V
V(DSGOFF)
DSG pin output off voltage
V(DSGOFF) = V(DSG) – V(PACK)
0.2
V
V(CHGOFF)
CHG pin output off voltage
V(CHGOFF) = V(CHG) –V(BAT)
0.2
V
Rise time
CL= 4700 pF; V(PACK) ≤ DSG ≤ V(PACK) +
4V
400
1000
CL= 4700 pF; V(BAT) ≤ CHG ≤ V(BAT) + 4 V
400
1000
CL= 4700 pF; V(PACK) + V(DSGON) ≤ DSG ≤
V(PACK) + 1 V
40
200
CL= 4700 pF; V(BAT) + V(CHGON) ≤ CHG ≤
V(BAT) + 1 V
40
200
tr
tf
Fall time
Copyright © 2011, Texas Instruments Incorporated
μs
μs
9
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SLUSAL7 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
V(ZVCHG)
ZVCHG clamp voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3
3.5
3.7
V
ALERT
60
100
200
RESET
1
3
6
BAT = 4.5 V
LOGIC; TA = –40°C to 100°C (unless otherwise noted)
R(PULLUP)
VOL
Internal pullup resistance
Logic low output voltage level
ALERT
0.2
RESET; V(BAT) = 7 V; V(REG25) = 1.5 V; I
(RESET) = 200 μA
0.4
GPOD; I(GPOD) = 50 μA
0.6
kΩ
V
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT, DISP
VIH
High-level input voltage
VIL
Low-level input voltage
2.0
VOH
Output voltage high (1)
IL = –0.5 mA
VOL
Low-level output voltage
PRES, PFIN, ALERT, DISP; IL = 7 mA;
CI
Input capacitance
I(SAFE)
SAFE source currents
SAFE active, SAFE = V(REG25) – 0.6 V
Ilkg(SAFE)
SAFE leakage current
SAFE inactive
Ilkg
Input leakage current
V
0.8
VREG25 – 0.5
V
V
0.4
5
V
pF
–3
mA
–0.2
0.2
µA
1
µA
ADC (2)
Input voltage range
TS1, TS2, using Internal Vref
–0.2
Conversion time
1
31.5
Resolution (no missing codes)
16
Effective resolution
14
bits
15
Offset error drift (4)
bits
±0.03
Integral nonlinearity
Offset error (4)
TA = 25°C to 85°C
Full-scale error (5)
Full-scale error drift
%FSR (3)
140
250
µV
2.5
18
μV/°C
±0.1%
±0.7%
50
Effective input resistance (6)
V
ms
PPM/°C
8
MΩ
COULOMB COUNTER
–0.20
Input voltage range
Conversion time
Single conversion
Effective resolution
Single conversion
Integral nonlinearity
Offset error
(7)
bits
±0.007
–0.20 V to –0.1 V
±0.007
TA = 25°C to 85°C
%FSR
µV
0.7
µV/°C
±0.35%
Full-scale error drift
Effective input resistance (10)
±0.034
10
0.4
(9)
V
ms
15
–0.1 V to 0.20 V
Offset error drift
Full-scale error (8)
0.20
250
150
TA = 25°C to 85°C
2.5
PPM/°C
MΩ
INTERNAL TEMPERATURE SENSOR
(1)
(2)
(3)
(4)
(5)
(6)
RC[0:7] bus
Unless otherwise specified, the specification limits are valid at all measurement speed modes.
Full-scale reference
Post-calibration performance and no I/O changes during conversion with SRN as the ground reference
Uncalibrated performance. This gain error can be eliminated with external calibration.
The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
(7) Post-calibration performance
(8) Reference voltage for the coulomb counter is typically Vref/3.969 at V(REG25) = 2.5 V, TA = 25°C.
(9) Uncalibrated performance. This gain error can be eliminated with external calibration.
(10) The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
10
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
V(TEMP)
TEST CONDITIONS
MIN
Temperature sensor voltage (11)
TYP
MAX
–2.0
UNIT
mV/°C
VOLTAGE REFERENCE
Output voltage
1.215
Output voltage drift
1.225
1.230
65
V
PPM/°C
HIGH FREQUENCY OSCILLATOR
f(OSC)
Operating frequency
f(EIO)
Frequency error
t(SXO)
Start-up time (14)
4.194
(12) (13)
TA = 20°C to 70°C
MHz
–3%
0.25%
3%
–2%
0.25%
2%
2.5
5
ms
LOW FREQUENCY OSCILLATOR
f(LOSC)
Operating frequency
f(LEIO)
Frequency error (13)
t(LSXO)
Start-up time (14)
(11)
(12)
(13)
(14)
(15)
32.768
(15)
TA = 20°C to 70°C
kHz
–2.5%
0.25%
2.5%
–1.5%
0.25%
1.5%
500
µs
–53.7 LSB/°C
The frequency error is measured from 4.194 MHz.
The frequency drift is included and measured from the trimmed frequency at V(REG25) = 2.5 V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
The frequency error is measured from 32.768 kHz.
Copyright © 2011, Texas Instruments Incorporated
11
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SLUSAL7 – AUGUST 2011
www.ti.com
POWER-ON RESET
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
VIT–
Negative-going voltage input
VHYS
Power-on reset hysteresis
tRST
TEST CONDITIONS
Active low time after power up or watchdog
reset
RESET active low time
MIN
TYP
MAX
UNIT
1.7
1.8
1.9
V
5
125
200
mV
100
250
560
µs
POWER ON RESET BEHAVIOR
VS
FREE-AIR TEMPERATURE
Power-On Reset Negative-Going Voltage - V
1.81
1.8
1.79
1.78
1.77
1.76
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND
SUPPLY VOLTAGE
Typical values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Data retention
Flash programming write-cycles
t(ROWPROG)
Row programming time
TYP
MAX
10
20k
See
UNIT
Years
Cycles
(1)
t(MASSERASE) Mass-erase time
t(PAGEERASE) Page-erase time
2
ms
200
ms
20
ms
I(DDPROG)
Flash-write supply current
5
10
mA
I(DDERASE)
Flash-erase supply current
5
10
mA
RAM/REGISTER BACKUP
I(RB)
RB data-retention input current
V(RB)
RB data-retention input voltage (1)
(1)
V(RBI) > V(RBI)MIN, VREG25 < VIT–, TA = 85°C
1000 2500
V(RBI) > V(RBI)MIN, VREG25 < VIT–, TA = 25°C
90
220
1.7
nA
V
Specified by design. Not production tested.
SMBus TIMING CHARACTERISTICS
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
f(SMB)
12
SMBus operating frequency
TEST CONDITIONS
MIN
Slave mode, SMBC 50% duty cycle
10
TYP
MAX
UNIT
100
kHz
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
SMBus TIMING CHARACTERISTICS (continued)
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
f(MAS)
SMBus master clock frequency
t(BUF)
Bus free time between start and stop
(See Figure 1.)
t(HD:STA)
Hold time after (repeated) start (See Figure 1.)
t(SU:STA)
Repeated start setup time (See Figure 1.)
t(SU:STO)
Stop setup time (See Figure 1.)
t(HD:DAT)
Data hold time (See Figure 1.)
t(SU:DAT)
Data setup time (See Figure 1.)
t(TIMEOUT)
Error signal/detect (See Figure 1.)
t(LOW)
Clock low period (See Figure 1.)
t(HIGH)
TEST CONDITIONS
Master mode, No clock low slave
extend
MAX
51.2
UNIT
kHz
4.7
µs
4
µs
µs
4
µs
Receive mode
0
ns
Transmit mode
300
250
(1)
Clock high period (See Figure 1.)
See
(2)
t(LOW:SEXT)
Cumulative clock low slave extend time
See
t(LOW:MEXT)
Cumulative clock low master extend time
(See Figure 1.)
25
ns
35
µs
µs
4.7
50
µs
(3)
25
ms
See
(4)
10
ms
300
ns
1000
ns
tf
Clock/data fall time
See
(5)
tr
Clock/data rise time
See
(6)
(3)
(4)
(5)
(6)
TYP
4.7
See
(1)
(2)
MIN
4
The bq34z651 times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq34z651 that is
in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tf = 0.9VDD to (VILMAX – 0.15)
Copyright © 2011, Texas Instruments Incorporated
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SLUSAL7 – AUGUST 2011
www.ti.com
tR
tSU(STO)
tF
tF
tHD(STA)
tBUF
tHIGH
SMBC
SMBC
SMBD
SMBD
P
tR
S
tLOW
tHD(DAT)
Start and Stop condition
tSU(DAT)
Wait and Hold condition
tSU(STA)
tTIMEOUT
SMBC
SMBC
SMBD
SMBD
S
Timeout condition
A.
Repeated Start condition
SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
14
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
FEATURE SET
Primary (1st Level) Safety Features
The bq34z651 supports a wide range of battery and system protection features that can be easily configured.
The primary safety features include:
•
•
•
•
•
Cell over/undervoltage protection
Charge and discharge overcurrent
Short circuit protection
Charge and discharge overtemperature with independent alarms and thresholds for each thermistor
AFE Watchdog
Secondary (2nd Level) Safety Features
The secondary safety features of the bq34z651 can be used to indicate more serious faults via the SAFE pin.
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. The secondary safety protection features include:
•
•
•
•
•
•
•
•
•
•
•
Safety overvoltage
Safety undervoltage
2nd-level protection IC input
Safety overcurrent in charge and discharge
Safety over-temperature in charge and discharge with independent alarms and thresholds for each thermistor
Charge FET and zero-volt charge FET fault
Discharge FET fault
Cell imbalance detection (active and at rest)
Open thermistor detection
Fuse blow detection
AFE communication fault
Charge Control Features
The bq34z651 charge control features include:
•
•
•
•
•
•
•
•
Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range
Handles more complex charging profiles. Allows for splitting the standard temperature range into two
sub-ranges, and for varying the charging current according to the cell voltage
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts
Determines the chemical state of charge of each battery cell using Impedance Track, and can reduce the
charge difference of the battery cells in a fully charged state of the battery pack, gradually using the cell
balancing algorithm during charging. This prevents fully charged cells from overcharging and causing
excessive degradation and also increases the usable pack energy by preventing premature charge
termination.
Supports pre-charging/zero-volt charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicate charge status via charge and discharge alarms
Battery heater control to allow battery charging in low ambient temperatures
Gas Gauging
The bq34z651 uses the Impedance Track Technology to measure and calculate the available charge in battery
cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full charge
discharge learning cycle required.
Copyright © 2011, Texas Instruments Incorporated
15
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note (SLUA364)
for further details.
16
Copyright © 2011, Texas Instruments Incorporated
bq34z651
www.ti.com
SLUSAL7 – AUGUST 2011
Lifetime Data Logging Features
The bq34z651 offers lifetime data logging, where important measurements are stored for warranty and analysis
purposes. The data monitored include:
• Lifetime maximum temperature
• Lifetime maximum temperature count
• Lifetime maximum temperature duration
• Lifetime minimum temperature
• Lifetime maximum battery cell voltage
• Lifetime maximum battery cell voltage count
• Lifetime maximum battery cell voltage duration
• Lifetime minimum battery cell voltage
• Lifetime maximum battery pack voltage
• Lifetime minimum battery pack voltage
• Lifetime maximum charge current
• Lifetime maximum discharge current
• Lifetime maximum charge power
• Lifetime maximum discharge power
• Lifetime maximum average discharge current
• Lifetime maximum average discharge power
• Lifetime average temperature
Authentication
The bq34z651 supports authentication by the host using SHA-1.
Power Modes
The bq34z651 supports three different power modes to reduce power consumption:
•
•
•
In Normal Mode, the bq34z651 performs measurements, calculations, protection decisions and data updates
in 1-second intervals. Between these intervals, the bq34z651 is in a reduced power stage.
In Sleep Mode, the bq34z651 performs measurements, calculations, protection decisions, and data updates
in adjustable time intervals. Between these intervals, the bq34z651 is in a reduced power stage. The
bq34z651 has a wake function that enables exit from Sleep mode when current flow or failure is detected.
In Shutdown Mode, the bq34z651 is completely disabled.
Copyright © 2011, Texas Instruments Incorporated
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bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
CONFIGURATION
Oscillator Function
The bq34z651 fully integrates the system oscillators; therefore, no external components are required for this
feature.
System Present Operation
The bq34z651 periodically verifies the PRES pin and detects that the battery is present in the system via a low
state on a PRES input. When this occurs, the bq34z651 enters normal operating mode. When the pack is
removed from the system and the PRES input is high, the bq34z651 enters the battery-removed state, disabling
the charge, discharge, and ZVCHG FETs. The PRES input is ignored and can be left floating when non-removal
mode is set in the data flash.
BATTERY PARAMETER MEASUREMENTS
The bq34z651 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from –0.25 V to 0.25 V. The bq34z651 detects charge activity when VSR = V(SRP) – V(SRN) is positive, and
discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq34z651 continuously integrates the signal over
time using an internal counter. The fundamental rate of the counter is 0.65 nVh.
Voltage
The bq34z651 updates the individual series cell voltages at one second intervals. The internal ADC of the
bq34z651 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate
the impedance of the cell for the Impedance Track gas-gauging.
Current
The bq34z651 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5-mΩ to 20-mΩ typ. sense resistor.
Wake Function
The bq34z651 can exit sleep mode, if enabled, by the presence of a programmable level of current signal across
SRP and SRN.
Auto Calibration
The bq34z651 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq34z651 performs auto-calibration when the SMBus lines stay
low continuously for a minimum of a programmable amount of time.
Temperature
The bq34z651 has an internal temperature sensor and two external temperature sensor inputs, TS1 and TS2,
used in conjunction with two identical NTC thermistors (default is Semitec 103AT) to sense the battery
environmental temperature. The bq34z651 can be configured to use the internal temperature sensor or up to two
external temperature sensors.
18
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
COMMUNICATIONS
The bq34z651 uses SMBus v1.1 with Master Mode and packet error checking (PEC) options per the SBS
specification.
SMBus On and Off State
The bq34z651 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this
state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.
SBS Commands
Table 2. SBS COMMANDS
SBS
Cmd
Mode
Format
Size in
Bytes
Min
Value
0x00
R/W
0x01
R/W
ManufacturerAccess
Hex
2
0x0000
0xffff
—
—
RemainingCapacityAlarm
Integer
2
0
700 or 1000
300 or 432
mAh or 10 mWh
0x02
R/W
RemainingTimeAlarm
Unsigned
integer
2
0
30
10
min
0x03
R/W
0x04
R/W
BatteryMode
Hex
2
0x0000
0xffff
—
—
AtRate
Integer
2
–32,768
32,767
—
mA or 10 mW
0x05
R
AtRateTimeToFull
Unsigned
integer
2
0
65,535
—
min
0x06
R
AtRateTimeToEmpty
Unsigned
integer
2
0
65,535
—
min
0x07
R
AtRateOK
Unsigned
integer
2
0
65,535
—
—
0x08
R
Temperature
Unsigned
integer
2
0
65,535
—
0.1°K
0x09
R
Voltage
Unsigned
integer
2
0
20,000
—
mV
0x0a
R
Current
Integer
2
–32,768
32767
—
mA
0x0b
R
AverageCurrent
Integer
2
–32,768
32,767
—
mA
0x0c
R
MaxError
Unsigned
integer
1
0
100
—
%
0x0d
R
RelativeStateOfCharge
Unsigned
integer
1
0
100
—
%
0x0e
R
AbsoluteStateOfCharge
Unsigned
integer
1
0
100+
—
%
0x0f
R/W
RemainingCapacity
Unsigned
integer
2
0
65,535
—
mAh or 10 mWh
0x10
R
FullChargeCapacity
Unsigned
integer
2
0
65,535
—
mAh or 10 mWh
0x11
R
RunTimeToEmpty
Unsigned
integer
2
0
65,534
—
min
0x12
R
AverageTimeToEmpty
Unsigned
integer
2
0
65,534
—
min
0x13
R
AverageTimeToFull
Unsigned
integer
2
0
65,534
—
min
0x14
R
ChargingCurrent
Unsigned
integer
2
0
65,534
—
mA
0x15
R
ChargingVoltage
Unsigned
integer
2
0
65,534
—
mV
0x16
R
BatteryStatus
Hex
2
0x0000
0xdbff
—
—
0x17
R/W
CycleCount
Unsigned
integer
2
0
65,535
0
—
0x18
R/W
DesignCapacity
Integer
2
0
32,767
4400 or 6336
mAh or 10 mWh
0x19
R/W
DesignVoltage
Integer
2
7000
18,000
14,400
mV
Name
Copyright © 2011, Texas Instruments Incorporated
Max
Value
Default Value
Unit
19
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SLUSAL7 – AUGUST 2011
www.ti.com
Table 2. SBS COMMANDS (continued)
SBS
Cmd
Mode
0x1a
R/W
0x1b
R/W
Format
Size in
Bytes
Min
Value
SpecificationInfo
Hex
2
ManufactureDate
Unsigned
integer
2
Name
Max
Value
Default Value
Unit
0x0000
0xffff
0x0031
—
0
65,535
0
—
0x1c
R/W
SerialNumber
Hex
2
0x0000
0xffff
0x0000
—
0x20
R/W
ManufacturerName
String
20+1
—
—
Texas
Instruments
—
0x21
R/W
DeviceName
String
20+1
—
—
bq34z651
—
0x22
R/W
DeviceChemistry
String
4+1
—
—
LION
—
0x23
R
ManufacturerData
String
14+1
—
—
—
—
0x2f
R/W
Authenticate
String
20+1
—
—
—
—
0x3c
R
CellVoltage4
Unsigned
integer
2
0
65,535
—
mV
0x3d
R
CellVoltage3
Unsigned
integer
2
0
65,535
—
mV
0x3e
R
CellVoltage2
Unsigned
integer
2
0
65,535
—
mV
0x3f
R
CellVoltage1
Unsigned
integer
2
0
65,535
—
mV
Table 3. EXTENDED SBS COMMANDS
SBS Cmd
20
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default
Value
Unit
0x45
R
AFEData
String
11+1
—
—
—
—
0x46
R/W
FETControl
Hex
2
0x00
0xff
—
—
0x4f
R
StateOfHealth
Hex
2
0x0000
0xffff
—
%
0x51
R
SafetyStatus
Hex
2
0x0000
0xffff
—
—
0x52
R
PFAlert
Hex
2
0x0000
0xffff
—
—
0x53
R
PFStatus
Hex
2
0x0000
0xffff
—
—
0x54
R
OperationStatus
Hex
2
0x0000
0xffff
—
—
0x55
R
ChargingStatus
Hex
2
0x0000
0xffff
—
—
0x57
R
ResetData
Hex
2
0x0000
0xffff
—
—
0x58
R
WDResetData
Unsigned
integer
2
0
65,535
—
—
0x5a
R
PackVoltage
Unsigned
integer
2
0
65,535
—
mV
0x5d
R
AverageVoltage
Unsigned
integer
2
0
65,535
—
mV
0x5e
R
TS1Temperature
Integer
2
–400
1200
—
0.1°C
0x5f
R
TS2Temperature
Integer
2
–400
1200
—
0.1°C
0x60
R/W
UnSealKey
Hex
4
0x00000000
0xffffffff
—
—
0x61
R/W
FullAccessKey
Hex
4
0x00000000
0xffffffff
—
—
0x62
R/W
PFKey
Hex
4
0x00000000
0xffffffff
—
—
0x63
R/W
AuthenKey3
Hex
4
0x00000000
0xffffffff
—
—
0x64
R/W
AuthenKey2
Hex
4
0x00000000
0xffffffff
—
—
0x65
R/W
AuthenKey1
Hex
4
0x00000000
0xffffffff
—
—
0x66
R/W
AuthenKey0
Hex
4
0x00000000
0xffffffff
—
—
0x68
R
SafetyAlert2
Hex
2
0x0000
0x000f
—
—
0x69
R
SafetyStatus2
Hex
2
0x0000
0x000f
—
—
0x6a
R
PFAlert2
Hex
2
0x0000
0x000f
—
—
0x6b
R
PFStatus2
Hex
2
0x0000
0x000f
—
—
Copyright © 2011, Texas Instruments Incorporated
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
Table 3. EXTENDED SBS COMMANDS (continued)
SBS Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default
Value
Unit
0x6c
R
ManufBlock1
String
20
—
—
—
—
0x6d
R
ManufBlock2
String
20
—
—
—
—
0x6e
R
ManufBlock3
String
20
—
—
—
—
—
0x6f
R
ManufBlock4
String
20
—
—
—
0x70
R/W
ManufacturerInfo
String
31+1
—
—
—
—
0x71
R/W
SenseResistor
Unsigned
integer
2
0
65,535
—
μΩ
0x72
R
TempRange
Hex
2
—
—
—
—
0x73
R
LifetimeData1
String
32+1
—
—
—
—
0x74
R
LifetimeData2
String
8+1
—
—
—
—
0x77
R/W
DataFlashSubClassID
Hex
2
0x0000
0xffff
—
—
0x78
R/W
DataFlashSubClassPage1
Hex
32
—
—
—
—
0x79
R/W
DataFlashSubClassPage2
Hex
32
—
—
—
—
0x7a
R/W
DataFlashSubClassPage3
Hex
32
—
—
—
—
0x7b
R/W
DataFlashSubClassPage4
Hex
32
—
—
—
—
0x7c
R/W
DataFlashSubClassPage5
Hex
32
—
—
—
—
0x7d
R/W
DataFlashSubClassPage6
Hex
32
—
—
—
—
0x7e
R/W
DataFlashSubClassPage7
Hex
32
—
—
—
—
0x7f
R/W
DataFlashSubClassPage8
Hex
32
—
—
—
—
Copyright © 2011, Texas Instruments Incorporated
21
bq34z651
SLUSAL7 – AUGUST 2011
www.ti.com
APPLICATION SCHEMATIC
22
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ34Z651DBT
NRND
TSSOP
DBT
44
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-250C-1 YEAR
-40 to 85
BQ34Z651
BQ34Z651DBTR
NRND
TSSOP
DBT
44
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ34Z651
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ34Z651DBTR
Package Package Pins
Type Drawing
TSSOP
DBT
44
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
6.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
11.7
1.6
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ34Z651DBTR
TSSOP
DBT
44
2000
367.0
367.0
45.0
Pack Materials-Page 2
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