Burr-Brown BUF07702 Multi channel lcd gamma correction buffer Datasheet

SLOS359F − MARCH 2001 − REVISED MAY 2004
FEATURES
D Gamma Correction Channels: 10, 6
D Integrated VCOM Buffer
D Excellent Output Current Drive:
D
D
D
D
D
D
D
DESCRIPTION
The BUFxx702 are a series of multi-channel buffers
targeted towards gamma correction in high-resolution
LCD panels. The number of gamma correction
channels required depends on a variety of factors and
differs greatly from design to design. Therefore, various
channel options are offered. For additional space and
cost savings, a VCOM channel with higher current drive
capability is integrated in the BUF11702 and
BUF07702.
− Gamma Channels: > 30mA at
0.5V Swing to Rails(1)
− VCOM: > 150mA at
5V Swing to Rails(1)
Large Capacitive Load Drive Capability
Rail-to-Rail Output
PowerPAD Package
The various buffers within the BUFxx702 are carefully
matched to the voltage I/O requirements for the gamma
correction application. Each buffer is capable of driving
heavy capacitive loads and offers fast load current
switching. The VCOM channel has increased output
drive of > 100mA and can handle even larger capacitive
loads.
Low-Power/Channel: < 340µA
Wide Supply Range: 4.5V to 16V
Specified for 0°C to 85°C
High ESD Rating: 4kV
(1) See typical characteristic curves for detail.
MODEL
BUF11702
BUF07702(1)
GAMMA
CHANNELS
VCOM CHANNELS
10
1
6
The BUF07702 and BUF11702 is available in the
TSSOP-PowerPAD package for dramatically
increased power dissipation capability. This way, a
large number of channels can be handled safely in one
package.
1
(1) The BUF07702 is not recommended for new designs. Information is provided for reference only. For new designs, the pin-compatible BUF07703 is recommended; more information can be
found at www.ti.com.
A flow-through pinout has been adopted to allow simple
PCB routing and maintain the cost-effectiveness of this
solution. All inputs and outputs of the BUFxx702
incorporate internal ESD protection circuits that prevent
functional failures at voltages up to 4kV (HBM) as
tested under MIL-STD-883C Method 3015.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.
Copyright  2001−2004, Texas Instruments Incorporated
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SLOS359F − MARCH 2001 − REVISED MAY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PARAMETERS
Supply, VDD(2)
Input Voltage Range, VI
BUFXX702
UNIT
16.5
V
VDD
See Dissipation
Rating Table
V
0 to 85
°C
Maximum Junction Temperature, TJ
150
°C
Storage Temperature Range, TSTG
−65 to 150
°C
Continuous Total Power Dissipation
Operating Free-Air Temperature Range, TA
Lead Temperature 1.6mm (1/16 inch) from case for 10s
260
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
ORDERING INFORMATION
PRODUCT
PACKAGE−LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
BUF11702
TSSOP−28
PWP
0°C to +85°C
BUF11702PWP
Tube, 50
BUF11702
BUF07702(2)
TSSOP−28
PWP
0°C to +85°C
BUF11702PWPR
Reels, 2000
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
TSSOP−20
PWP
0°C to +85°C
BUF07702PWP
Tube, 70
BUF07702(2)
TSSOP−20
PWP
0°C to +85°C
BUF07702PWPR
Reels, 2000
(1) For the most current specification and package information, refer to the Package Option Addendum at the end of this data sheet.
(2) The BUF07702 is not recommended for new designs. For new designs, the pin-compatible BUF07703 is recommended.
DISSIPATION RATING TABLE
PACKAGE TYPE
PACKAGE
DESIGNATOR
qJC
(°C/W)
qJA(1)
(°C/W)
TA ≤ 25°C(2)
POWER RATING
PWP (28)
0.72
27.9
3.5 W
PWP (20)
1.40
26.1
3.8 W
TSSOP−28
TSSOP−20(3)
(1) With 2oz trace and PowerPAD soldered to copper landing pad.
(2) TJ = 125°C.
(3) The BUF07702 is not recommended for new designs. For new designs, the pin-compatible BUF07703 is recommended.
RECOMMENDED OPERATING CONDITIONS
MIN
2
NOM
MAX
UNIT
Supply Voltage, VDD
4.5
16
V
Operating Free-Air Temperature, TA
0
85
°C
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SLOS359F − MARCH 2001 − REVISED MAY 2004
EQUIVALENT SCHEMATICS OF INPUTS AND OUTPUTS
INPUT STAGE OF BUFFERS
INPUT STAGE OF BUFFERS
BUF11702: 1 to 5 and VCOM
BUF07702: 1 to 3 and VCOM
BUF11702: 6 to 10
BUF07702: 4 to 6
OUTPUT STAGE OF ALL BUFFERS
VS
VS
VS
Next
Stage
Buffer
Input
Buffer
Input
Buffer
Output
Internal to
BUF11702
Inverting
Input
Buffer
Output
Next Stage
Buffer
Output
GND
Previous
Stage
Previous
Stage
GND
GND
Internal to
BUF11702
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, VDD = 4.5V to 16V, TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VI = VDD/2, RS = 50 Ω
IIB
Input bias current
VI = VDD/2
kSVR
Supply voltage rejection ratio (∆VDD/∆VIO)
VDD = 4.5 V to 16 V
Buffer gain
VI = 5 V
TA
25°C
MIN
BW_3dB
3dB bandwidth
SR
Slew rate
Transient load regulation
Transient load response
1.5
15
mV
1
Full
Range(1)
200
25°C
62
Full
Range(1)
60
pA
80
dB
25°C
0.9995
V/V
CL = 100 pF, RL = 2 kΩ
25°C
1
0.6
MHz
CL = 100 pF, RL = 2 kΩ
VIN = 2V to 8V
25°C
1
0.7
V/µs
25°C
900
mV
25°C
160
mV
Full
Range(1)
1
µs
Full
Range(1)
2
µs
6
4.6
µs
5.8
5.6
µs
IO = 0 to ±5 mA, VO = 5 V
CL = 100 pF tT = 0.1 µs
See Figure 2
Gamma buffers
VCOM buffer
VI = 5 V f = 1 kHz
25°C
45
40
nV/Hz
VIP−P = 6 V, f = 1 kHz
25°C
85
dB
tS (I−src)
Settling time-current
tS
Settling timevoltage
Crosstalk
(1) Full Range is 0°C to 85°C.
12
VCOM buffer
Settling time-current
Noise voltage
UNIT
IO = 0 to −5 mA VO = 5 V
CL = 100 pF RL = 2 kΩ
IO = 0 to +5 mA VO = 5 V
CL = 100 pF RL = 2 kΩ
VI = 4.5 V to 5.5 V 0.1%
VI = 5.5 V to 4.5 V 0.1%
VI = 4.5 V to 5.5 V 0.1%
VI = 5.5 V to 4.5 V 0.1%
tS (I−sink)
Vn
MAX
Full
Range(1)
25°C
Gamma buffers
VCOM buffer
Gamma buffers
VCOM buffer
TYP
Gamma buffers
25°C
3
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SLOS359F − MARCH 2001 − REVISED MAY 2004
ELECTRICAL CHARACTERISTICS: BUF11702
Over operating free-air temperature range, VDD = 4.5V to 16V, TA = 25°C, unless otherwise noted.
PARAMETER
IDD
Supply current
ALL
TEST CONDITIONS
VO = VDD/2, VI = VDD/2,
VDD = 10 V
TA(1)
25°C
25°C
25
C
VCOM buffer
VCOM buffer sinking
VDD = 10 V,
IO = 1 mA to 30 mA
VCOM buffer sourcing
VDD = 10 V,
IO = −1 mA to −30 mA
Buffers 1−10 sinking
VDD = 10 V,
IO = 1 mA to 10 mA
Full Range
VDD = 16 V,
VI = 0 V
IO = 5 mA,
VOH1
Buffer 1
VDD = 10 V,
VI = 9.8 V
IO = −10 mA,
VOH2/3/4/5
Buffer 2/3/4/5
VDD = 10 V,
VI = 9.5 V
IO = −10 mA,
Buffer 6/7/8/9
VDD = 10 V,
VI = 8 V
IO = −10 mA,
VOH10
Buffer 10
VDD = 10 V,
VI = 8 V
IO = −10 mA,
VOHCOM
VCOM buffer
VDD = 10 V,
VI = 8 V
IO = −30 mA,
VOL1
Buffer 1
VDD = 10 V,
VI = 2 V
IO = 10 mA,
0.85
Full Range
VOL2/3/4/5
Buffer 2/3/4/5
VDD = 10 V,
VI = 2 V
IO = 10 mA,
0.85
Buffer 6/7/8/9
VDD = 10 V,
VI = 0.5 V
IO = 10 mA,
VOL10
Buffer 10
VDD = 10 V,
VI = 0.2 V
IO = 10 mA,
VOLCOM
VCOM buffer
VDD = 10 V,
VI = 2 V
IO = 30 mA,
25°C
9.75
9.7
25°C
9.45
Full range
9.4
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
V
V
8
V
8
V
8
2
V
2.05
2.1
2
2.05
2.1
0.5
Full range
0.55
0.6
0.2
Full range
0.25
0.3
2
V
V
9.5
Full range
25°C
0.15
9.8
Full range
Full range
mV/mA
1
0.2
25°C
25°C
1
15.9
0.1
Full range
25°C
1.2
1.5
Full range
25°C
V
1.5
25°C
25°C
mA
1.2
2.5
25°C
15.8
Buffer 10
4
1
15.85
Low-level
saturated output
voltage
UNIT
2.5
25°C
25°C
VOSL10
(1) Full Range is 0°C to 85°C.
Full Range
Full range
IO = −5mA,
Low-level output
voltage
1
Full Range
VDD = 16V,
VI = 16V
VOL6/7/8/9
25°C
VDD = 10 V,
IO = −1 mA to −10 mA
Buffer 1
High-level output
voltage
VDD
VDD−1
VDD
0
Buffers 1−10 sourcing
High-level
saturated output
voltage
3.7
5.5
1
VOSH1
VOH6/7/8/9
MAX
2.5
1
Buffers 6−10
Load regulation
TYP
Full Range
Buffers 1−5
Common-mode input range
MIN
V
V
V
V
2.05
2.1
V
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SLOS359F − MARCH 2001 − REVISED MAY 2004
ELECTRICAL CHARACTERISTICS: BUF07702
Over operating free-air temperature range, VDD = 4.5V to 16V, TA = 25°C, unless otherwise noted.
PARAMETER
IDD
Supply current
ALL
TEST CONDITIONS
VO = VDD/2, VI = VDD/2
VDD= 10V
TA(1)
25°C
25°C
25
C
VCOM buffer
VCOM buffer sinking
VDD = 10 V,
IO = 1 mA to 30 mA
VCOM buffer sourcing
VDD = 10 V,
IO = −1 mA to −30 mA
Buffers 1−6 sinking
VDD = 10 V,
IO = 1 mA to 10 mA
Full Range
1
Full Range
0.85
Full Range
0.85
15.85
15.8
Low-level
saturated output
voltage
Buffer 6
VDD = 16 V,
VI = 0 V
IO = 5 mA,
VOH1
Buffer 1
VDD = 10 V,
VI = 9.8 V
IO = −10 mA,
VOH2/3
Buffer 2/3
VDD = 10 V,
VI = 9.5 V
IO = −10 mA,
Buffer 4/5
VDD = 10 V,
VI = 8 V
IO = −10 mA,
VOH6
Buffer 6
VDD = 10 V,
VI = 8 V
IO = −10 mA,
VOHCOM
VCOM buffer
VDD = 10 V,
VI = 8 V
IO = −30 mA,
VOL1
Buffer 1
VDD = 10 V,
VI = 2 V
IO = 10 mA,
VOL2/3
Buffer 2/3
VDD = 10 V,
VI = 2 V
IO = 10 mA,
Buffer 4/5
VDD = 10 V,
VI = 0.5 V
IO = 10 mA,
VOL6
Buffer 6
VDD = 10 V,
VI = 0.2 V
IO = 10 mA,
VOLCOM
VCOM buffer
VDD = 10 V,
VI = 2 V
IO = 30 mA,
25°C
9.75
9.7
25°C
9.45
Full range
9.4
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
V
V
8
V
8
V
2.05
2.1
2
2.05
2.1
0.5
Full range
0.55
0.6
0.2
Full range
25°C
V
8
2
0.25
0.3
2
V
V
9.5
Full range
Full range
0.15
9.8
Full range
25°C
mV/mA
1
0.2
25°C
25°C
1
15.9
0.1
Full range
25°C
1.2
1.5
Full range
25°C
V
VDD
1.2
1.5
25°C
25°C
VOSL6
mA
2.5
25°C
Full range
IO = −5 mA,
mA
5.5
2.5
25°C
Full Range
VDD = 16 V,
VI = 16 V
Low-level output
voltage
1
VDD = 10 V,
IO = −1 mA to −10 mA
Buffer 1
VOL4/5
25°C
Buffers 1−6 sourcing
High-level
saturated output
voltage
High-level output
voltage
0
UNIT
3.7
VDD
VDD−1
1
VOSH1
VOH4/5
MAX
2.5
1
Buffers 4−6
Load regulation
TYP
Full Range
Buffers 1−3
Common-mode input range
MIN
V
V
V
V
2.05
2.1
V
(1) Full Range is 0°C to 85°C.
5
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SLOS359F − MARCH 2001 − REVISED MAY 2004
BUF11702 Pin Configuration
BUF07702 Pin Configuration
\
6
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SLOS359F − MARCH 2001 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
Buffer
RNULL
CL
RL
Figure 1. Bandwidth and Phase Shift Test Circuit
Buffer
VO
RS
5V
CS
5V
LCD Driver
CL
Equivalent Load
RL
VTL
tT
V1
Source
Ch1−Ch10
V1
0V
VTL
2V
tT
0.1 µs
CS
100 pF
RS
100 Ω
CL
100 pF
RL
1 kΩ
Sink
Ch1−Ch10
10 V
2V
0.1 µs
100 pF
100 Ω
100 pF
1 kΩ
Test
Figure 2. Transient Load Response Test Circuit
Buffer
tT
VO
5V
RNULL
RL
CL
10 V
5V
0V
VTL
VTL
Figure 3. Transient Load Regulation Test Circuit
7
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SLOS359F − MARCH 2001 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
DC CURVES
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
20
20
20
15
5
0
−5
−10
−15
−20
10
5
0
−5
−10
−15
−20
1
2
3 4
5 6 7
VI − Input Voltage − V
8
9
10
Figure 4
V OH − High-Level Output Voltage − V
I IB − Input Bias Current − pA
200
150
100
50
0
10 20 30 40 50 60 70
TA − Free-Air Temperature − °C
TA = 0°C
TA = +25°C
7
TA = +85°C
6.5
6
BUF07702
VDD = 10 V
Channels 2 to 3
5.5
5
0
25
50
75
100
125 150
IOH − High-Level Output Current − mA
Figure 10
−15
8
10
0
2
4
6
VI − Input Voltage − V
TA = 0°C
8
TA = +25°C
TA = +85°C
7
8
10
Figure 6
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
6
VDD = 10 V
Channel 1
9.9
9.8
TA = 0°C
9.7
TA = +25°C
9.6
9.5
9.4
TA = +85°C
9.3
9.2
9.1
9
0
0
50
100
150
200
250
IOH − High-Level Output Current − mA
10
BUF11702
VDD = 10 V
Channels 6 to 10
9
8
7
TA = 0°C
TA = +25°C
6
TA = +85°C
5
4
3
2
BUF07702
VDD = 10 V
Channels 4 to 6
1
0
0
5 10 15 20 25 30 35 40 45 50
IOH − High-Level Output Current − mA
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V OH − High-Level Output Voltage − V
8.5
7.5
−10
Figure 8
BUF11702
VDD = 10 V
Channels 2 to 5
8
0
−5
10
9
5
80 85
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
9
4
6
VI − Input Voltage − V
VDD = 10 V
Channel 1
Figure 7
9.5
2
10
VDD = 10 V
10
5
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
250
0
10
Figure 5
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 10 V
VCOM Buffer
15
−20
0
V OH − High-Level Output Voltage − V
0
V OH − High-Level Output Voltage − V
BUF07702
VDD = 10 V
Channels 4 to 6
V IO − Input Offset Voltage − mV
BUF11702
VDD = 10 V
Channels 6 to 10
25
50
75
100
125
150
IOH − High-Level Output Current − mA
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
10
V OH − High-Level Output Voltage − V
V IO − Input Offset Voltage − mV
10
BUF07702
VDD = 10 V
Channels 1 to 3
V IO − Input Offset Voltage − mV
BUF11702
VDD = 10 V
Channels 1 to 5
15
8
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
VDD = 10 V
VCOM Buffer
9
8
TA = 0°C
7
6
5
TA = +25°C
4
3
TA = +85°C
2
1
0
0
50
100
150
200
250
IOH − High-Level Output Current − mA
Figure 12
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SLOS359F − MARCH 2001 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
DC CURVES (CONTINUED)
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
BUF11702
VDD = 10 V
Channels 1 to 5
8
7
BUF07702
VDD = 10 V
Channels 1 to 3
6
5
4
TA = 0°C
3
TA = +25°C
TA = +85°C
2
1
0
0
4
BUF07702
VDD = 10 V
Channels
4 to 5
3.5
3
2.5
2
TA = 0°C
1.5
TA = +25°C
1
TA = +85°C
0.5
0.5
0.4
TA = 0°C
0.3
TA = +25°C
0.2
TA = +85°C
0.1
V OL− Low-Level Output Voltage − V
0.6
0
0
2
1
BUF07702
VDD = 10 V
Channel 6
0
50
100
150
200
250
IOL − Low-Level Output Current − mA
Figure 15
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
4
TA = 0°C
VDD = 10 V
VCOM Buffer
9
3.5
8
7
6
5
TA = +25°C
4
3
TA = +85°C
2
3
TA = +25°C
TA = +70°C
2.5
2
TA = +85°C
1.5
1
0.5
TA = 0°C
1
0
0
10 15 20 25 30 35 40 45 50
IOL − Low-Level Output Current − mA
5
0
50
100
150
200
IOL − Low-Level Output Current − mA
250
Figure 17
Figure 16
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VDD − Supply Voltage − V
Figure 18
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4
15 V
3.5
I DD − Supply Current − mA
V OL − Low-Level Output Voltage − V
BUF07702
VDD = 10 V
Channel 6
TA = +85°C
1.5
0
10
BUF11702
VDD = 10 V
Channel 10
0.7
3
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1
TA = 0°C
TA = +25°C
2.5
Figure 14
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.8
4
3.5
25
75
125
50
100
150
IOL − Low-Level Output Current − mA
0
BUF11702
VDD = 10 V
Channel 10
4.5
0.5
0
125
25
50
75
100
150
IOL − Low-Level Output Current − mA
Figure 13
0.9
5
BUF11702
VDD = 10 V
Channels 6 to 9
4.5
I DD − Supply Current − mA
9
V OL− Low-Level Output Voltage − V
V OL − Low-Level Output Voltage − V
10
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
V OL− Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
10 V
3
5V
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
TA − Free-Air Temperature − °C
Figure 19
9
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TYPICAL CHARACTERISTICS
AC CURVES
−3 dB BANDWIDTH
vs
SUPPLY VOLTAGE
−3 dB BANDWIDTH
vs
FREE-AIR TEMPERATURE
1.2
BUF07702
Channel 5
0.75
VCOM Buffer
0.5
RL = 2 kΩ
CL = 100 pF
TA = +25°C
0
5V
1
10, 15 V
0.8
VCOM Buffer
0.6
5, 10, 15 V
0.4
0.2
RL = 2 kΩ
CL = 100 pF
0
0
2
4
6
8
10 12
VDD − Supply Voltage − V
14
0
10 V
0.7
15 V
0.6
0.5
0.4
0.3
0.2
0
1000
3
2
1.5
RNULL = 50
1
80
15 V
60
40
0
200
400
600
800
CL − Load Capacitance − pF
0 100 200 300 400 500 600 700 800 900 1000
CL − Load Capacitance − pF
1000
Figure 25
RNULL = 50
40
RL = 2 kΩ
VCOM Buffer
f = −3 dB BW
50
45
40
VDD = 5 V
35
30
25
VDD = 10 V
20
VDD = 15 V
15
10
20
5
0
0
100 200 300 400 500 600 700 800 900 1000
CL − Load Capacitance − pF
0
100 200 300 400 500 600 700 800 900 1000
CL − Load Capacitance − pF
Figure 27
PSRR − Power Supply Rejection Ratio − dB
55
Input-Output Phase Shift
60
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
INPUT-OUTPUT PHASE SHIFT
vs
LOAD CAPACITANCE
RNULL = 0
5V
10 V
Figure 24
80
Figure 26
100
20
60
0
RL = 2 kΩ
Channel 1
f = −3 dB BW
120
2.5
0
140
1000
140
INPUT-OUTPUT PHASE SHIFT
vs
LOAD CAPACITANCE
100
200
400
600
800
CL − Load Capacitance − pF
INPUT-OUTPUT PHASE SHIFT
vs
LOAD CAPACITANCE
VDD = 10 V
RL = 2 kΩ
Channel 1
RNULL = 0
Figure 23
120
0.5
Figure 22
0
200
400
600
800
CL − Load Capacitance − pF
VDD = 10 V
RL = 2 kΩ
Channel 1
f = −3 dB BW
1
0
0.5
0.1
0
15 V
1.5
80
Input-Output Phase Shift
BW − −3 dB Bandwidth − MHz
BW − −3 dB Bandwidth − MHz
10 20 30 40 50 60 70
TA − Free-Air Temperature − °C
3.5
RL = 2 kΩ
VCOM Buffer
0.8
10
V
2
−3 dB BANDWIDTH
vs
LOAD CAPACITANCE
1.1
0.9
2.5
Figure 21
−3 dB BANDWIDTH
vs
LOAD CAPACITANCE
1
RL = 2 kΩ
Channel 1
3
0
16
Figure 20
Input-Output Phase Shift
BW − −3 dB Bandwidth − MHz
1
0.25
3.5
Gamma Channels
BUF11702
Channel 9
BW − −3 dB Bandwidth − MHz
BW − −3 dB Bandwidth − MHz
1.25
10
−3 dB BANDWIDTH
vs
LOAD CAPACITANCE
VDD = 10 V
RL = 2 kΩ
CL = 100 pF
80
70
60
50
Gamma Channels
VCOM Buffer
40
30
20
10
0
10
100
1k
10 k 100 k
f − Frequency − Hz
Figure 28
1M
10 M
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
AC CURVES (CONTINUED)
CROSSTALK
vs
FREQUENCY
NOISE VOLTAGE
vs
FREQUENCY
0
120
−40
−50
−60
−70
−80
5V
−90
10 V
−100
15 V
−110
−120
1000
100
80
Zo − Output Impedance − Ω
−30
V n − Noise Voltage − nV/
−20
Hz
RL = 1 kΩ
CL = 100 pF
VI = 60% VDD
Adjacent Channels
−10
Crosstalk − dB
OUTPUT IMPEDANCE
vs
FREQUENCY
VCOM Buffer
60
40
Gamma Channels
20
0
10
1k
10 k
100
f − Frequency − Hz
Figure 29
100 k
10
100
1k
10 k
f − Frequency − Hz
Figure 30
100 k
100
VCOM Buffer
10
1
Gamma Channels
0.1
0.01
0.1 k
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 31
11
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TRANSIENT CURVES
SUPPLY VOLTAGE, OUTPUT VOLTAGE
AND SUPPLY CURRENT
16
VDD
12
8
4
3
VDD = 0 to 15 V
RL = 2 kΩ
CL = 100 pF
VI = VDD/2
TA = +25°C
1
0
−1
0
5
10
15
20
25
30
35
40
45
50
4
VCOM
Buffer
3
2
Gamma Channels
1
0
0
2
Figure 32
4
6
8 10 12
t − Time − µs
15
4
VO − Output Voltage − V
0
10
8
2
Gamma Channels
0
0
5
10
15
20
t − Time − µs
Figure 34
12
25
30
VDD = 15 V
VI = 9 V
RL = 2 kΩ
CL = 100 pF
TA = +25°C
VI
12
9
6
3
VO − Output Voltage − V
6
VI − Input Voltage − V
8
2
4
16 18
LARGE SIGNAL VOLTAGE FOLLOWER
10
VDD = 10 V
VI = 6 V
RL = 2 kΩ
CL = 100 pF
TA = +25°C
VCOM
Buffer
14
Figure 33
LARGE SIGNAL VOLTAGE FOLLOWER
6
1
0
t − Time − µs
VI
2
0
15
12
9
VCOM
Buffer
6
Gamma Channels
3
0
0
4
8
12 16 20
t − Time − µs
Figure 35
24
28
32
36
VI − Input Voltage − V
IDD
3
5
0
2
4
VDD = 5 V
VI = 3 V
RL = 2 kΩ
CL = 100 pF
TA = +25°C
VI
VO − Output Voltage − V
IDD − Supply Current − mA
VO − All Channels
5
V I − Input Voltage − V
20
VO − Output Voltage − V
VDD − Supply Voltage − V
LARGE SIGNAL VOLTAGE FOLLOWER
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TRANSIENT CURVES (CONTINUED)
2.55
VDD = 5 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = +25°C
2.50
2.45
VO − Output Voltage − V
2.40
2.60
VI
5.05
VDD = 10 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = +25°C
5
4.95
Gamma Channels
Gamma Channels
5.05
2.55
VCOM Buffer
VCOM Buffer
4.95
2.45
2.40
0 0.5
1
1.5 2 2.5 3 3.5
t − Time − µs
4 4.5
0
5
0.50
Figure 36
1
1.50 2 2.50 3
t − Time − µs
3.50
4
4.90
4.50
Figure 37
TRANSIENT LOAD RESPONSE − SOURCING
7.55
VDD = 15 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = +25°C
7.50
7.45
VI − Input Voltage − V
7.60
VI
VLT − Input Voltage − V
SMALL SIGNAL VOLTAGE FOLLOWER
VO − Output Voltage − V
5
2.50
7
6
5
4
3
2
1
0
Transient Load
Pulse
Channel 1
VDD = 10 V, VI = 5 V,
CS = 100 pF, RS = 100 Ω,
CL = 100 pF, RL = 1 kΩ,
tT = 0.1 µs, TA = +25°C
5.15
5.1
5.05
7.40
7.60
5
7.55
4.95
7.50
VCOM Buffer
Output Voltage
7.45
7.40
Gamma Channels
0
0.5
1
1.5
2
2.5
t − Time − µs
Figure 38
4.9
4.85
3
3.5
4
4.5
0
0.1
0.2
0.3 0.4 0.5 0.6
t − Time − µs
0.7
0.8
0.9
VO − Output Voltage − V
VI
5.10
VO − Output Voltage − V
2.60
VI − Input Voltage − V
SMALL SIGNAL PULSE RESPONSE
V I − Input Voltage − V
SMALL SIGNAL VOLTAGE FOLLOWER
4.8
1
Figure 39
13
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TRANSIENT CURVES (CONTINUED)
5.1
5.05
5
4.95
4.9
4.85
0.1 0.2 0.3 0.4 0.5
0.6
0.7 0.8 0.9
1
Channel 1
VDD = 10 V, VI = 5 V,
RL = 1 kΩ, tT = 0.1 µs,
TA = +25°C
5.8
CL = 100 pF
5.4
5.2
5
CL = 10 nF
RNULL = 100 Ω
4.6
0
1
2
3
4
5
t − Time − µs
Figure 40
IL− Load Current − mA
IL− Load Current − mA
Sinking
6
VCOM Buffer
VDD = 10 V, VI = 5 V,
RL = 500 Ω, tT = 0.1 µs,
TA = +25°C
0
−6
5.2
5
4.8
CL = 10 nF
RNULL = 100 Ω
4.6
CL = 500 pF and
1000 pF
Sourcing
6
VO − Output Voltage − V
5.4
CL = 1000 pF
CL = 10 nF
5.5
5
CL = 100 nF
RNULL = 20 Ω
4.5
4
t − Time − µs
3.5
6 7 8 9 10 11 12 13 14 15
t − Time − µs
Figure 42
Figure 43
4.4
14
8
12
−12
CL = 100 pF
2
7
TRANSIENT LOAD REGULATION − VCOM BUFFER
Channel 1
VDD = 10 V, VI = 5 V,
RL = 1 kΩ, tT = 0.1 µs,
TA = +25°C
1
6
Figure 41
TRANSIENT LOAD REGULATION − SOURCING
0
4.8
4.8
t − Time − µs
6
5
4
3
2
1
0
5.6
CL = 1000 pF
3
4
5
6
7
8
0
1
2
3
4
5
VO − Output Voltage − V
0
6
5
4
3
2
1
0
VO − Output Voltage − V
Channel 1
VDD = 10 V, VI = 5 V,
CS = 100 pF, RS = 100 Ω,
CL = 100 pF, RL = 1 kΩ,
tT = 0.1 µs, TA = +25°C
IL− Load Current − mA
TRANSIENT LOAD REGULATION − SINKING
VO − Output Voltage − V
VLT − Input Voltage − V
TRANSIENT LOAD RESPONSE − SINKING
7
6
5
4
3
2
1
0
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
APPLICATION INFORMATION
The requirements on the number of gamma correction
channels vary greatly from panel to panel. Therefore,
the BUFxx702 series of gamma correction buffers
offers different channel combinations. The BUF11702
offers 10 gamma channels plus one VCOM channel,
whereas the BUF07702 provides six gamma channels
plus one VCOM. The VCOM channel on both models can
be used to drive the VCOM node on the LCD panel.
Gamma correction voltages are often generated using
a simple resistor ladder, as shown in Figure 44. The
BUFxx702 buffers the various nodes on the gamma
correction resistor ladder. The low output impedance of
the BUFxx702 forces the external gamma correction
voltage on the respective reference node of the LCD
source driver. Figure 44 shows an example of the
BUFxx702 in a typical block diagram driving an LCD
source driver with 10- or 6-channel gamma correction
reference inputs.
Figure 44. LCD Source Driver Typical Block Diagram
15
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SLOS359F − MARCH 2001 − REVISED MAY 2004
INPUT VOLTAGE RANGE GAMMA BUFFERS
COMMON BUFFER (VCOM)
Figure 45 shows a typical gamma correction curve with
10 gamma correction reference points (GMA1 through
GMA10). As can be seen from this curve, the voltage
requirements for each buffer vary greatly. The swing
capability of the input stages of the various buffers is
carefully matched to the application. Using the example
of the BUF11702 with 10 gamma correction channels,
buffers 1 to 5 have input stages that include VDD, but will
only swing within 1V to GND. Buffers 1 through 5 have
only a single NMOS input stage. Buffers 6 through 10
have only a single PMOS input stage. The input range
of the PMOS input stage includes GND.
The common buffer output of the BUF11702 has a
greater output drive capability than buffers 1 through
10, to meet the heavier current demands of driving the
common node of the LCD panel. It was also designed
to drive heavier capacitive loads and still remain stable,
as shown in Figure 46.
GMA2
25
20
15
10
5
10
100
CL − Load Capacitance − pF
1000
Figure 46. Phase Shift vs Load Capacitance
GMA6
GMA7
GMA8
GMA9
CAPACITIVE LOAD DRIVE
20
Input Data HEX0
30
40
OUTPUT VOLTAGE SWING GAMMA BUFFERS
The output stages have been designed to match the
characteristic of the input stage. Once again, using the
example of the BUF11702, this means that the output
stage of buffer 1 swings very close to VDD, typically
VCC − 100mV at 5mA; its ability to swing to GND is
limited. Buffers 2 through 5 have smaller output stages
with slightly larger output resistance, as they will not
have to swing as close to the positive rail as buffer 1.
Buffers 6 through 10 swing closer to GND than VDD.
Buffer 10 is designed to swing very close to GND;
typically, GND + 100mV at a 5mA load current. See the
Typical Characteristics for more details. This approach
significantly reduces the silicon area and cost of the
whole solution. However, due to this architecture, the
correct buffer needs to be connected to the correct
gamma correction voltage. Connect buffer 1 to the
gamma voltage closest to VDD, and buffers 2 through 5
to the following voltages. Buffer 10 should be connected
to the gamma correction voltage closest to GND (or the
negative rail), and buffers 9 through 6 to the following
higher voltages.
The BUF11702 has been designed to be able to
sink/source dc currents in excess of 10mA. Its output
stage has been designed to deliver output current
transients with little disturbance of the output voltage.
However, there are times when very fast current pulses
are required. Therefore, in LCD source driver buffer
applications, it is quite normal for capacitors to be
placed at the outputs of the reference buffers. These
capacitors improve the transient load regulation and will
typically vary from 100pF and more. The BUF11702
gamma buffers were designed to drive capacitances in
excess of 100pF and retain effective phase margins
above 50°, as shown in Figure 47.
140
BUF11702: Channels 1 to 10
120
Phase Shift − Deg
10
Figure 45. Gamma Correction Curve
16
35
30
0
GMA3
GMA4
GMA5
GMA10
VSS1
0
VDD = 10 V
RL = 2 kΩ
VCOM
40
Phase Shift − Deg
VDD1
GMA1
45
BUF07702: Channels 1 to 6
100
VDD = 10 V
RL = 2 kΩ
80
60
40
20
0
10
100
CL − Load Capacitance − pF
1000
Figure 47. Phase Shift Between Output and Input
vs Load Capacitance for the Gamma Buffers
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
APPLICATIONS WITH >10 GAMMA CHANNELS
When a greater number of gamma correction channels
are required, two or more BUFxx702 devices can be
used in parallel, as shown in Figure 48. This capability
provides a cost-effective way of creating more
reference voltages over the use of quad-channel op
amps or buffers. The suggested configuration in Figure
48 simplifies layout. The various different channel
versions provide a high degree of flexibility and also
minimize total cost and space.
Figure 48. Creating > 10 Gamma Voltage
Channels
MULTIPLE VCOM CHANNELS
In some LCD panels, more than one VCOM driver is
required for best panel performance. Figure 49 uses
three BUF07702s to create a total of 18
gamma-correction and three VCOM channels. This
solution saves considerable space and cost over the
more conventional approach of using five or six
quad-channel buffers or op amps.
Figure 49. 18-Channel Application with Three
Integrated VCOM Channels
17
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
COMPLETE LCD SOLUTION FROM TI
In addition to the BUFxx702 line of gamma correction
buffers, TI offers a complete set of ICs for the LCD panel
market, including source and gate drivers, various
power-supply solutions, and audio power solutions.
Figure 50 shows the total IC solution from TI.
AUDIO POWER AMPLIFIER FOR TV
SPEAKERS
The TPA3002D2 is a 7W (per channel) stereo audio
amplifier specifically targeted towards LCD monitors
and TVs. It offers highly efficient, filter-free Class-D
operation for driving bridge−tied stereo speakers. The
TPA3002D2 is designed to drive stereo speakers as low
as 8Ω without an output filter. The high efficiency of the
TPA3002D2 eliminates the need for external heatsinks
when playing music. Stereo speaker volume is
controlled with a dc voltage applied to the volume
control terminal offering a range of gain from −40dB to
+36dB. Line outputs, for driving external headphone
amplifier inputs, are also dc voltage−controlled with a
range of gain from −56dB to +20dB. An integrated +5V
regulated supply is provided for powering an external
headphone amplifier. The TPA3002D2 was released to
market in 2002. Texas Instruments offers a full line of
linear and switch-mode audio power amplifiers. For
more information, visit www.ti.com. For excellent audio
performance, TI recommends the OPA364 or OPA353
as headphone drivers.
GENERAL POWERPAD DESIGN
CONSIDERATIONS
The BUF11702 is available in the thermally enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the
die is mounted; see Figures 51(a) and (b). This
arrangement results in the lead frame being exposed as
a thermal pad on the underside of the package; see
Figure 51(c). Due to this thermal pad having direct
thermal contact with the die, excellent thermal
performance is achieved by providing a good thermal
path away from the thermal pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper
area, heat can be conducted away from the package
into either a ground plane or other heat-dissipating
device. Soldering the PowerPAD to the PCB is always
required, even with applications that have low power
dissipation. This provides the necessary thermal and
mechanical connection between the lead frame die pad
and the PCB.
The PowerPAD must be connected to the device’s most
negative supply voltage.
Figure 50. TI LCD Solution
18
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
NOTE A:
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 51. Views of Thermally Enhanced DGN Package
1. Prepare the PCB with a top-side etch pattern (see
Pin Configurations). There should be etching for the
leads as well as etch for the thermal pad.
2. Place 18 holes in the area of the thermal pad. These
holes should be 13mils in diameter. Keep them
small, so that solder wicking through the holes is not
a problem during reflow.
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the
BUFxx702 IC. These additional vias may be larger
than the 13mil diameter vias directly under the
thermal pad. They can be larger because they are
not in the thermal pad area to be soldered, thus,
wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane,
do not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This
makes the soldering of vias that have plane
connections easier. In this application, however, low
thermal resistance is desired for the most efficient
heat transfer. Therefore, the holes under the
BUFxx702 PowerPAD package should make their
connection to the internal ground plane with a
complete
connection
around
the
entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The
bottom-side solder mask should cover the five or
nine holes of the thermal pad area. This prevents
solder from being pulled away from the thermal pad
area during the reflow process.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8. With these preparatory steps in place, the
BUFxx702 IC is simply placed in position and run
through the solder reflow operation as any standard
surface-mount component. This preparation results
in a properly installed part.
For a given qJA, the maximum power dissipation is
shown in Figure 52, and is calculated by the following
formula:
PD +
ǒT
* TA
q JA
MAX
Ǔ
Where:
PD = maximum power dissipation (W)
TMAX = absolute maximum junction temperature (150°C)
TA = free-ambient air temperature (°C)
qJA = qJC + qCA
qJC = thermal coefficient from junction to case (°C/W)
qCA = thermal coefficient from case-to-ambient air (°C/W)
8
7
Maximum Power Dissipation − W
PowerPAD ASSEMBLY PROCESS
BUF11702
θJA = 27.9°C/W
2 oz. Trace and Copper
Pad With Solder
6
5
TJ = 125°C
4
3
2
1
0
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Figure 52. Maximum Power Dissipation vs
Free-Air Temperature
This lower thermal resistance enables the
BUFxx702 to deliver maximum output currents
even at high ambient temperatures.
19
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
APPLICATION INFORMATION
BUF11702 Demonstration Board
(Contact Factory)
decoupling capacitors are connected to the ground
plane of the demo board, as are the ground terminals of
the BUF11702.
The BUF11702 has an demonstration board that can be
mounted along with reference resistors and load
capacitors. This enables the BUF11702 to be used in its
own daughterboard in existing designs for easy
evaluation. The schematic of the BUF11702 demo
board is shown in Figure 53. Note that the demo board
has been configured for single-supply use. As such, all
In populated versions of the demo board, capacitors C1
to C4 have been included. Capacitors C1 and C2 are
bulk decoupling capacitors of 6.8µF, whereas
capacitors C3 and C4 are 100nF ceramic
high-frequency decoupling capacitors. Resistors R1 to
R32 and capacitors C5 to C16 have not been included
and are application-specific.
J2
J3
JP3
GND
GND
VREF
INCOM
GND
INCOM
R11
CH10
R21
R10
OUT9
IN9
R9
IN7
R7
CH6
OUT7
BUF11702
IN6
IN5
OUT4
R4
CH8
R18
R17
R15
R14
R3
R13
IN2
R12
IN1
CH7
R27
C11
CH6
R28
C10
C9
CH5
R29
CH4
R30
C8
CH3
R31
C7
CH2
R32
C6
NC
VDD
VDD
C4
JP2
GND
VDD2
JP1
J1
VDD
C1
Figure 53. BUF11702 Demonstration Board Schematic
20
CH1
GND
NC
VDD
C2
C12
R26
OUT1
R1
C3
C13
OUT2
R2
CH1
R25
OUT3
IN3
CH2
C14
OUT5
IN4
CH3
CH9
R16
R5
CH4
R24
OUT6
R6
CH5
R20
C15
OUT8
R8
CH7
R23
CH10
R19
IN8
CH8
C16
OUT10
IN10
CH9
OUTCOM
R22
OUTCOM
www.ti.com
SLOS359F − MARCH 2001 − REVISED MAY 2004
REFERENCE VOLTAGES
The reference voltages can be supplied externally via
the connector J2 (not included) or generated onboard
via resistors R1 to R11. An external low side reference
has been provided on the board so that the negative references can be referred to a voltage other than ground.
The reference ladder can be referred to either VDD
(master supply voltage) or a secondary voltage, VDD2.
This allows a low noise or absolute reference voltage to
be used for the LCD source driver’s DACs other than
the system voltage. If the secondary voltage is used,
then jumper JP1 should be left open and jumper JP2
shorted. If a ratiometric reference (proportional to the
master supply voltage) is to be used, then jumpers JP1
and JP2 should both be shorted, feeding VDD through to
the reference ladder.
OUTPUT
The outputs of the BUF11702 are fed to connector J3
(not mounted). This enables the output voltages to be
monitored directly on the demonstration board or fed
off-board for evaluation in a real system.
Onboard load resistors, R23 to R32, connected to
ground can also be mounted. These can be used to simulate resistive loading of the LCD source driver.
Transient improving capacitors are frequently used in
LCD panel applications. Therefore, pads to mount
these transient improving capacitors, C6 to C16, have
been included. Due to the possible magnitude of these
capacitors, pads have been placed between the output
of the BUF11702 and these capacitors to mount nulling
resistors, R12 to R22. If the nulling resistors are not required, shorts could be placed instead of resistors.
The pads for R1 to R32 and capacitors C3 to C16 have
been laid out to support 0805 or 1206 size components.
PowerPAD
The BUF11702 demonstration board has been laid out
to support the PowerPAD feature of the BUF11702. An
area is provided on the demo board, under the
BUF11702, for the exposed leadframe connection.
Eighteen vias are connected to the ground plane of the
demo board to significantly reduce the thermal case to
ambient resistance, qCA. See the Applications section
on general PowerPAD design considerations.
21
PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BUF07702PWP
ACTIVE
HTSSOP
PWP
20
70
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR
BUF07702PWPR
ACTIVE
HTSSOP
PWP
20
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR
BUF11702PWP
ACTIVE
HTSSOP
PWP
28
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR
BUF11702PWPR
ACTIVE
HTSSOP
PWP
28
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR
BUF11702PWPRG4
ACTIVE
HTSSOP
PWP
28
2000 Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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