NB100LVEP221 2.5V/3.3V 2:1:20 Differential HSTL/ECL/PECL Clock Driver Description The NB100LVEP221 is a low skew 2:1:20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The LVPECL input signals can be either differential configuration or single−ended (if the VBB output is used). The LVEP221 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The NB100LVEP221, as with most other ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single−ended CLK input operation is limited to a VCC ≥ 3.0 V in LVPECL mode, or VEE ≤ −3.0 V in NECL mode. www.onsemi.com MARKING DIAGRAMS* 52 1 NB100 LVEP221 AWLYYWWG LQFP−52 FA SUFFIX CASE 848H 52 1 1 NB100 LVEP221 AWLYYWWG 52 QFN−52 MN SUFFIX CASE 485M A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. Features • • • • • • • • • • • • 15 ps Typical Output−to−Output Skew 40 ps Typical Device−to−Device Skew Jitter Less than 2 ps RMS Maximum Frequency > 1.0 GHz Typical Thermally Enhanced 52−Lead LQFP and QFN VBB Output 540 ps Typical Propagation Delay LVPECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V Q Output will Default Low with Inputs Open or at VEE Pin Compatible with Motorola MC100EP221 These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2015 April, 2015 − Rev. 10 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. 1 Publication Order Number: NB100LVEP221/D Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 Q10 Q10 Q11 Q11 VCC0 NB100LVEP221 39 38 37 36 35 34 33 32 31 30 29 28 27 VCC0 40 26 Q12 Q5 41 25 Q12 Q5 42 24 Q13 Q4 43 23 Q13 Q4 44 22 Q14 Q3 45 21 Q14 Q3 46 20 Q15 Q2 47 19 Q15 Q2 48 18 Q16 Q1 49 17 Q16 Q1 50 16 Q17 Q0 51 15 Q17 Q0 52 14 VCC0 4 5 6 7 8 9 10 11 12 13 CLK0 VBB CLK1 CLK1 VEE Q19 Q19 Q18 Q18 VCC 3 CLK0 2 CLKSEL 1 VCC0 NB100LVEP221 All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat−sinking conduit, capable of transferring 1.2 Watts. This exposed pad is electrically connected to VEE internally. Figure 1. 52−Lead LQFP Pinout (Top View) www.onsemi.com 2 Q1 Q2 Q2 Q 3 Q3 Q4 Q4 Q5 Q5 VCC0 49 48 47 46 44 43 42 41 40 45 Q1 50 51 Q 0 Q0 52 NB100LVEP221 Exposed Pad (EP) VCC0 1 39 Q6 VCC 2 38 Q6 CLKSEL 3 37 Q7 CLK0 4 36 Q7 CLK0 5 35 Q8 VBB 6 34 Q8 CLK1 7 33 Q9 CLK1 8 32 Q9 VEE 9 31 Q10 Q19 10 30 Q10 Q19 11 29 Q11 Q18 12 28 Q11 Q18 13 27 VCC0 24 25 26 Q12 Q12 21 Q14 Q13 20 Q15 23 19 Q15 Q13 18 Q16 22 17 Q16 Q14 16 Q17 15 Q17 VCC0 14 NB100LVEP221 Figure 2. 52−Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION CLK0*, CLK0** ECL/PECL Differential Inputs CLK1*, CLK1** ECL/PECL or HSTL Differential Inputs Q0:19, Q0:19 ECL/PECL Differential Outputs CLK_SEL* ECL/PECL Active Clock Select Input VBB Reference Voltage Output VCC/VCCO Positive Supply VEE*** Negative Supply CLK0 0 CLK0 20 Q0 − Q19 Q0 − Q19 CLK1 20 1 CLK1 VBB * Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally. CLK_SEL VCC Table 2. FUNCTION TABLE VEE CLK_SEL Active Input L H CLK0, CLK0 CLK1, CLK1 Figure 3. Logic Diagram www.onsemi.com 3 NB100LVEP221 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP−52 QFN−52 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 200 V > 2 kV Pb−Free Pkg Level 3 Level 2 UL 94 V−0 @ 0.125 in 533 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (See Application Information) 0 lfpm 500 lfpm LQFP−52 LQFP−52 35.6 30 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (See Application Information) 0 lfpm 500 lfpm LQFP−52 LQFP−52 3.2 6.4 °C/W °C/W qJA Thermal Resistance (Junction−to−Ambient) (Note ) 0 lfpm 500 lfpm QFN−52 QFN−52 25 19.6 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note ) 2S2P QFN−52 21 °C/W Tsol Wave Solder 265 265 °C Pb Pb−Free VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 4 NB100LVEP221 Table 5. LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 2) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 100 125 150 104 130 156 116 145 174 mA VOH Output HIGH Voltage (Note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 3) 555 680 900 555 680 900 555 680 900 mV VIH Input HIGH Voltage (Single−Ended) (Note 4) 1335 1620 1335 1620 1275 1620 mV VIL Input LOW Voltage (Single−Ended) (Note 4) 555 900 555 900 555 900 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) CLK0/CLK0 CLK1/CLK1 1.2 0.3 2.5 1.6 1.2 0.3 2.5 1.6 1.2 0.3 2.5 1.6 V V 150 mA Symbol Characteristic IIH Input HIGH Current IIL Input LOW Current 150 CLK CLK 0.5 −150 150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to −1.3 V. 3. All outputs loaded with 50 W to VCC − 2.0 V. 4. Do not use VBB at VCC < 3.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 100 125 150 104 130 156 116 145 174 mA VOH Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 7) 1355 1480 1700 1355 1480 1700 1355 1480 1700 mV VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1700 1355 1700 1355 1700 mV VBB Output Reference Voltage (Note 8) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) CLK0/CLK0 CLK1/CLK1 3.3 1.6 1.2 0.3 3.3 1.6 1.2 0.3 3.3 1.6 V V 150 mA IIH Input HIGH Current IIL Input LOW Current 1875 1.2 0.3 150 CLK CLK 0.5 −150 1875 150 0.5 −150 0.5 −150 1875 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 6. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to −0.5 V. 7. All outputs loaded with 50 W to VCC − 2.0 V. 8. Single−ended input operation is limited VCC ≥ 3.0 V in LVPECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 5 NB100LVEP221 Table 7. LVNECL DC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 10) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 100 125 150 104 130 156 116 145 174 mA Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV Output LOW Voltage (Note 11) −1945 −1820 −1600 −1945 −1820 −1600 −1945 −1820 −1600 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1600 −1945 −1600 −1945 −1600 mV VBB Output Reference Voltage (Note 12) −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) CLK0/CLK0 CLK1/CLK1 0.0 −0.9 V V 150 mA Symbol Characteristic IEE Power Supply Current VOH VOL IIH Input HIGH Current IIL Input LOW Current −1425 VEE + 1.2 VEE + 0.3 0.0 −0.9 −1425 VEE + 1.2 VEE + 0.3 150 CLK CLK 0.0 −0.9 −1425 VEE + 1.2 VEE + 0.3 150 0.5 −150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 10. Input and output parameters vary 1:1 with VCC. 11. All outputs loaded with 50 W to VCC−2.0 V. 12. Single−ended input operation is limited VEE ≤ −3.0V in NECL mode. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. HSTL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V 0°C Symbol VIH VIL Min Characteristic Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit Input HIGH Voltage CLK1/CLK1 Vx+100 1600 Vx+100 1600 Vx+100 1600 mV CLK1/CLK1 −300 Vx−100 −300 Vx−100 −300 Vx−100 mV Input LOW Voltage VX Differential Configuration Cross Point Voltage 680 900 680 900 680 900 mV IIH Input HIGH Current −150 150 −150 150 −150 150 mA IIL Input LOW Current CLK1 CLK1 −150 −250 −150 −250 −150 −250 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. www.onsemi.com 6 NB100LVEP221 Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 to −3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 14) −40°C Symbol VOpp tPLH/tPHL Characteristic Differential Output Voltage (Figure 4) fout < 50 MHz fout < 0.8 GHz fout < 1.0 GHz Min Typ 550 550 500 700 700 700 25°C Max Min Typ 600 550 500 700 700 700 85°C Max Min Typ 600 500 400 700 700 600 Max Unit mV mV mV Propagation Delay (Differential Configuration) CLK0−Qx CLK1−Qx 540 590 600 640 540 590 660 710 540 590 750 800 ps ps tskew Within−Device Skew (Note 15) Device−to−Device Skew (Note 16) 15 40 50 200 15 40 50 200 15 40 50 200 ps ps tJITTER Random Clock Jitter (RMS) (Figure 4) 1 2 1 2 1 2 ps VPP Input Swing (Differential Configuration) (Note 17) (Figure 5) CLK0 CLK1 HSTL 400 300 800 800 1200 1000 400 300 800 800 1200 1000 400 300 800 800 1200 1000 mV mV DCO Output Duty Cycle 49.5 50 50.5 49.5 50 50.5 49.5 50 50.5 % tr/tf Output Rise/Fall Time (20%−80%) 100 200 300 100 200 300 150 250 350 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 14. Measured with 750 mV source (LVPECL) or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC−2 V. 15. Skew is measured between outputs under identical transitions and conditions on any one device. 16. Device−to−Device skew for identical transitions, outputs and VCC levels. 17. VPP is the differential configuration input voltage swing required to maintain AC characteristics. www.onsemi.com 7 NB100LVEP221 900 10 9 800 7 6 600 5 500 4 tJITTER ps (RMS) VOPP (mV) 8 700 3 400 2 300 1 200 0 0.1 0.2 0.4 0.6 0.8 1.0 fIN, INPUT FREQUENCY (GHz) Figure 4. Output Voltage (VOPP)/Jitter versus Input Frequency (VCC − VEE = 3.3 V @ 255C) VCC(LVPECL) VIH(DIFF) VPP VPP VIHCMR VIL(DIFF) VIL(DIFF) VEE VEE Figure 5. LVPECL Differential Input Levels Q VCCO(HSTL) VIH(DIFF) VX Figure 6. HSTL Differential Input Levels Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) www.onsemi.com 8 NB100LVEP221 APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100LVEP221 supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 9, “Recommended solder mask openings”, shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 9. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. The NB100LVEP221 uses a thermally enhanced 52−lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100LVEP221 high−speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100LVEP221. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100LVEP221 applications on multi−layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 8 providing an efficient heat removal path. All Units mm 0.2 1.0 1.0 4.6 0.2 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern Figure 9. Recommended Solder Mask Openings All Units mm Proper thermal management is critical for reliable system operation. This is especially true for high−fanout and high output drive capability products. For thermal system analysis and junction temperature calculation, the thermal resistance parameters of the package are provided: 4.6 Table 10. Thermal Resistance * 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter lfpm qJA 5C/W qJC 5C/W 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * Junction to ambient and Junction to board, four−conductor layer test board (2S2P) per JESD 51−8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100LVEP221 package is electrically shorted to the substrate of the integrated circuit and VEE. The thermal land should be electrically connected to VEE. Exposed Pad Land Pattern Figure 8. Recommended Thermal Land Pattern The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will www.onsemi.com 9 NB100LVEP221 ORDERING INFORMATION Package Shipping† NB100LVEP221FAG LQFP−52 (Pb−Free) 160 Units / Tray NB100LVEP221FARG LQFP−52 (Pb−Free) 1500 / Tape & Reel NB100LVEP221MNG QFN−52 (Pb−Free) 260 Units / Tray NB100LVEP221MNR2G QFN−52 (Pb−Free) 2000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 10 NB100LVEP221 PACKAGE DIMENSIONS LQFP 52 EXPOSED PAD CASE 848H ISSUE B SCALE 1:1 4 PL M M/2 −Z− 0.20 (0.008) T X-Y Z AJ AJ 52 40 1 39 ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ PLATING −X− AA −Y− L B J AB B/2 L/2 D REF 13 27 0.08 (0.003) 26 14 M Y T-U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE “E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM “X", “Y" AND “Z" TO BE DETERMINED AT DATUM PLANE DATUM “E". 5. DIMENSIONS M AND L TO BE DETERMINED AT SEATING PLANE DATUM “T". 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO BASE METAL INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLAND “E". 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). Z DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE DETAIL AJ−AJ A/2 0.20 (0.008) E X-Y Z A DETAIL AH −E− −T− AG G SEATING PLANE AG 48 PL D 0.08 (0.003) 0.10 (0.004) T 52 PL M T X-Y V Z 0.05 (0.002) R S AC AD EXPOSED PAD 14 26 S C MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.30 1.50 0.22 0.40 0.45 0.75 0.65 BSC 1.00 REF 0.09 0.20 0.05 0.20 12.00 BSC 12.00 BSC 0.20 REF 0_ 7_ 0_ ----1.70 12 _ REF 12 _ REF 0.20 0.35 0.07 0.16 0.08 0.20 4.58 4.78 4.58 4.78 INCHES MIN MAX 0.394 BSC 0.394 BSC 0.051 0.059 0.009 0.016 0.018 0.030 0.026 BSC 0.039 BSC 0.004 0.008 0.002 0.008 0.472 BSC 0.472 BSC 0.008 REF 0_ 7_ 0_ ----0.067 12 _ REF 12 _ REF 0.008 0.014 0.003 0.006 0.003 0.008 0.180 0.188 0.180 0.188 27 13 K W N P F H AE 0.25 GAGE PLANE RECOMMENDED SOLDERING FOOTPRINT DETAIL AH 12.36 52X 1.18 4.80 39 1 52 40 VIEW AG−AG 4.80 PKG OUTLINE www.onsemi.com 11 0.65 PITCH 12.36 52X 0.40 DIMENSIONS: MILLIMETERS NB100LVEP221 PACKAGE DIMENSIONS QFN52 8x8, 0.5P CASE 485M ISSUE C D PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ B DIM A A1 A2 A3 b D D2 E E2 e K L E 2X 0.15 C 2X 0.15 C A2 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50 0.10 C A 0.08 C A3 A1 RECOMMENDED SOLDERING FOOTPRINT REF SEATING PLANE C D2 14 52 X L 8.30 52X 26 0.62 6.75 27 13 E2 6.75 39 1 52 X K 8.30 52 40 e 52 X b NOTE 3 0.10 C A B PKG OUTLINE 0.05 C 0.50 PITCH 52X 0.30 DIMENSIONS: MILLIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100LVEP221/D