CXK5V8257BTM/BYM/BM -70LL/10LL 32768-word × 8-bit High Speed CMOS Static RAM For the availability of this product, please contact the sales office. Description The CXK5V8257BTM/BYM/BM is 262,144 bits high speed CMOS static RAM organized as 32768words by 8 bits. A polysilicon TFT cell technology realized extermely low stand-by current and higher data retention stability. Operating on a single 3.3V supply, directly LVTTL compatible (All inputs and outputs). And special feature are, low power consumption, high speed and broad package line-up. The CXK5V8257BTM/BYM/BM is a suitable RAM for portable equipment with battery back up. Features • Single +3.3V supply: 3.3V ±0.3V • Directly LVTTL compatible: All inputs and outputs • Fast access time: (Access time) CXK5V8257BTM/BYM/BM -70LL 70ns (Max.) -10LL 100ns (Max.) • Low standby current: CXK5V8257BTM/BYM/BM -70LL/10LL 3.5µA (Max.) • Low power data retention: 2.0V (Min.) • Available in many packages CXK5V8257BTM/BYM 8mm × 13.4mm 28 pin TSOP Package CXK5V8257BM 450mil 28 pin SOP Package CXK5V8257BTM 28 pin TSOP (Plastic) CXK5V8257BYM 28 pin TSOP (Plastic) CXK5V8257BM 28 pin SOP (Plastic) Block Diagram A14 A13 A12 A11 A9 A8 A7 A6 A5 Buffer A10 A4 A3 A2 A1 A0 Buffer OE Function 32768-word × 8 bit static RAM WE Row Decoder Memory Matrix VCC 512 × 512 GND I /O Gate Column Decoder Buffer I /O Buffer CE I /O1 I /O8 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93836A5Z-ST CXK5V8257BTM/BYM/BM AA Pin Configuration (Top View) OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 22 21 23 20 24 19 25 18 26 27 17 A3 A4 A5 A6 A7 A12 A14 Vcc WE A13 A8 A9 A11 OE 16 15 CXK5V8257BTM (Standard Pinout) 28 1 2 14 13 3 12 4 11 5 10 6 9 7 8 7 8 6 9 5 4 10 3 12 2 13 11 CXK5V8257BYM (Mirror Image Pinout) 1 28 14 15 27 26 16 25 18 24 19 23 20 22 21 17 Absolute Maximum Ratings Item A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 Symbol 28 Vcc 27 WE 26 A13 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A14 1 A12 2 A7 3 A6 4 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE A10 Pin Description A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 A0 to A14 Address input I/O1 to I/O8 data input/output CE Chip enable input WE Write enable input OE Output enable input VCC +3.3V power supply GND Ground CXK5V8257BM (Ta = 25°C, GND = 0V) Symbol Rating Unit V Supply voltage VCC Input voltage VIN –0.5 to +4.6 –0.5∗1 to VCC + 0.5 Input and output voltage VI/O –0.5∗1 to VCC + 0.5 V Allowable power dissipation PD 0.7 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +150 °C Soldering temperature · time Tsolder 235 · 10 °C · s V ∗1 VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE OE WE Mode I/O1 to I/O8 H × × Not selected High Z ISB1, ISB2 L H H Output disable High Z ICC1, ICC2 L L H Read Data out ICC1, ICC2 L × L Write Data in ICC1, ICC2 VCC Current × : “H” or “L” DC Recommended Operating Conditions Item (Ta = 0 to +70°C, GND = 0V) Symbol Min. Typ. Max. Supply voltage VCC 3.0 3.3 3.6 Input high voltage VIH — VCC + 0.3 Input low voltage VIL 2.0 –0.3∗2 — 0.8 ∗2 VIL = –3.0V Min. for pulse width less than 50ns. –2– Description Unit V CXK5V8257BTM/BYM/BM Electrical Characteristics • DC characteristics Item (VCC = 3.3V ± 0.3V, GND = 0V, Ta = 0 to +70°C) Symbol Test Conditions Min. Typ.∗1 Max. Unit Input leakage current ILI VIN = GND to VCC –0.5 — 0.5 µA Output leakage current ILO CE = VIH, OE = VIH or WE = VIL, VI/O = GND to VCC –0.5 — 0.5 µA Operating power supply current ICC1 CE = VIL, VIN = VIH or VIL, IOUT = 0mA — 0.9 2 mA 70LL — 21 40 10LL — 18 35 0 to +70°C — — 3.5 0 to +40°C — — 0.7 +25°C — 0.12 0.35 Average operating ICC2 current Standby current ISB1 Min. cycle, Duty = 100%, IOUT = 0mA CE ≥ VCC – 0.2V mA µA ISB2 CE = VIH — 0.06 0.7 mA Output high voltage VOH IOH = –2mA 2.4 — — V Output low voltage VOL IOL = 2.0mA — — 0.4 V ∗1 VCC = 3.3V, Ta = 25°C I/O capacitance Item (Ta = 25°C, f = 1MHz) Symbol Test condition Min. Typ. Max. Unit Input capacitance CIN VIN = 0V — — 8 pF I/O capacitance CI/O VI/O = 0V — — 10 pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions (VCC = 3.3V ± 0.3V, Ta = 0 to +70°C) Item Conditions Input pulse high level VIH = 2.0V Input pulse low level VIL = 0.8V Input rise time tr = 5ns tf = 5ns Input fall time Input and output reference level Output load conditions TTL -70LL 1.4V CL∗2 = 30pF, 1TTL -10LL CL∗2 = 100pF, 1TTL ∗2 CL includes scope and jig capacitances. –3– CL CXK5V8257BTM/BYM/BM • Read cycle (WE = “H”) -70LL Item Read cycle time Address access time Chip enable access time (CE) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Chip disable to output in high Z (CE) Output disable to output in high Z (OE) ∗1 Symbol tRC tAA tCO tOE tOH tLZ tOLZ tHZ∗1 tOHZ∗1 -10LL Unit Min. Max. Min. Max. 70 — 100 — ns — 70 — 100 ns — 70 — 100 ns — 35 — 50 ns 20 — 20 — ns 10 — 10 — ns 5 — 10 — ns — 30 — 35 ns — 30 — 35 ns tHZ and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle -70LL Item Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE) Output active from end of write Write to output in high Z ∗2 Symbol tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗2 -10LL Unit Min. Max. Min. Max. 70 — 100 — ns 60 — 80 — ns 60 — 80 — ns 30 — 35 — ns 0 — 0 — ns 55 — 60 — ns 0 — 0 — ns 0 — 0 — ns 0 — 0 — ns 10 — 10 — ns — 30 — 35 ns tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –4– CXK5V8257BTM/BYM/BM Timing Waveform • Read cycle (1): CE = OE = VIL, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2): WE = VIH tRC Address tAA CE tCO tHZ tLZ OE tOE tOHZ tOLZ Data valid Data out High impedance • Write cycle (1): WE control tWC Address tWR tAW OE tCW CE tAS tWP (∗1) WE tDW tDH Data valid Data in tWHZ tOW Data out High impedance (∗2) –5– (∗2) CXK5V8257BTM/BYM/BM • Write cycle (2): CE control tWC Address tAW OE tAS tWR1 (∗3) tCW CE tWP WE tDW Data in tDH Data valid Data out High impedance ∗1 Write is executed when both CE and WE are at low simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is measured at the period from the rising edge of CE to the end of write cycle. –6– CXK5V8257BTM/BYM/BM Data retention waveform • Low supply voltage data retention waveform tCDRS tR Data retention mode VCC 3.0V 2.0V VDR CE CE ≥ VCC – 0.2V GND Data Retention Characteristics Item Symbol Data retention voltage VDR Data retention current ICCDR1 (Ta = 0 to +70°C) Test condiitions Min. Typ. Max. Unit 2.0 — 3.6 V 0 to +70°C — — 3 0 to +40°C — — 0.6 +25°C — 0.1 0.3 CE ≥ VCC – 0.2V VCC = 3.0V, CE ≥ 2.8V µA ICCDR2 VCC = 2.0 to 3.6V, CE ≥ VCC – 0.2V — 0.12∗1 3.5 µA Data retention setup time tCDRS Chip disable to data retention mode 0 — — ns Recovery time tR 5 — — ms ∗1 VCC = 3.3V, Ta = 25°C –7– CXK5V8257BTM/BYM/BM Package Outline Unit: mm CXK5V8257BTM 28PIN TSOP (Plastic) ∗8.0 ± 0.1 0.1 13.4 ± 0.3 8 ∗11.8 ± 0.1 21 1.2 MAX A 22 + 0.1 0.2 – 0.05 28 1 + 0.07 0.127 – 0.02 7 0.55 ± 0.1 0.5 ± 0.1 + 0.1 0.05 – 0.05 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE TSOP-28P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE TSOP028-P-0000-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE CXK5V8257BYM 28PIN TSOP (Plastic) ∗8.0 ± 0.1 1.2 MAX 0.1 13.4 ± 0.3 21 ∗11.8 ± 0.1 8 A 7 + 0.1 0.2 – 0.05 1 28 + 0.07 0.127 – 0.02 22 0.55 ± 0.1 0.5 ± 0.1 + 0.1 0.05 – 0.05 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE TSOP-28P-L01R LEAD TREATMENT SOLDER PLATING EIAJ CODE TSOP028-P-0000-B LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE –8– CXK5V8257BTM/BYM/BM CXK5V8257BM 28PIN SOP (PLASTIC) + 0.4 2.3 – 0.15 + 0.4 18.0 – 0.1 28 15 0.15 14 1 0.4 ± 0.1 1.27 0.24 1.0 ± 0.2 11.8 ± 0.4 + 0.3 8.4 – 0.1 + 0.2 0.1 – 0.05 0° to 10° + 0.1 0.05 0.15 – M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-28P-L05 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗SOP028-P-0450 LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.7g JEDEC CODE –9–