LINER LTC4009-2 High efficiency, multi-chemistry battery charger Datasheet

LTC4009
LTC4009-1/LTC4009-2
High Efficiency,
Multi-Chemistry
Battery Charger
Description
Features
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General Purpose Battery Charger Controller
Efficient 550kHz Synchronous Buck PWM Topology
±0.5% Output Float Voltage Accuracy
Programmable Charge Current: 4% Accuracy
Programmable AC Adapter Current Limit:
3% Accuracy
No Audible Noise with Ceramic Capacitors
Wide Input Voltage Range: 6V to 28V
Wide Output Voltage Range: 2V to 28V
Indicator Outputs for AC Adapter Present, Charging,
C/10 Current Detection and Input Current Limiting
Analog Charge Current Monitor
Micropower Shutdown
Thermally Enhanced 20-Pin 4mm × 4mm × 0.75mm
QFN Package
Applications
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Notebook Computers
Portable Instruments
Battery Backup Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5723970.
The LTC®4009 is a constant-current/constant-voltage
battery charger controller. It uses a synchronous quasiconstant frequency PWM control architecture that will
not generate audible noise with ceramic bulk capacitors.
Charge current is set by the combination of external
sense, input and programming resistors. With no built-in
termination, the LTC4009 family charges a wide range of
batteries under external control.
The LTC4009 features a fully adjustable output voltage, while
the LTC4009-1 and LTC4009-2 can be pin-programmed for
lithium-ion/polymer battery packs of 1-, 2-, 3- or 4-series
cells. The LTC4009-1 provides output voltage of 4.1V/cell,
and the LTC4009-2 is a 4.2V/cell version.
The device includes AC adapter input current limiting which
maximizes the charge rate for a fixed input power level. An
external sense resistor programs the input current limit, and
the ICL status pin indicates when the battery charge current
is being reduced as a result of AC adapter current limiting.
The CHRG status pin is active during all charging modes,
including special indication for low charge current.
Typical Application
33mΩ
0.1µF
DCIN
14.3k
1.5k
CLP
SW
INTVDD
ICL
BGATE
SHDN
GND
ITH
CSP
Efficiency at DCIN = 20V
100
0.1µF
95
2µF
6.8µH
3.01k
6.04k
0.1µF
CHARGE
CURRENT
MONITOR
4.7nF
20µF
FBDIV
301k
26.7k
VFB
32.8k
+
12.3V
Li-Ion
BATTERY
EFFICIENCY
90
POWER LOSS
85
1000
VOUT = 12.3V
RSENSE = 33mΩ
RIN = 3.01k
RPROG = 26.7k
DIN = SSB44
L = IHLP-2525CZ 6.8µH
80
75
70
BAT
PROG
33mΩ
3.01k
CSN
10000
0
0.5
1.0
1.5
2.0
CHARGE CURRENT (A)
2.5
POWER LOSS (mW)
ACP
POWER TO
SYSTEM
5.1k
CLN
DCDIV BOOST
LTC4009
TGATE
CHRG
TO/FROM
MCU
20µF
0.1µF
EFFICIENCY (%)
FROM
ADAPTER
13V TO 20V
100
3.0
4009 TA01b
4009 TA01a
4009fd
LTC4009
LTC4009-1/LTC4009-2
Absolute Maximum Ratings
(Note 1)
DCIN, CLP, CLN or SW to GND.................... –0.3V to 30V
CLP to CLN.............................................................±0.3V
CSP, CSN or BAT to GND............................ –0.3V to 28V
CSP to CSN.............................................................±0.3V
BOOST to GND............................................ –0.3V to 36V
BOOST to SW............................................... –0.3V to 7V
DCDIV, SHDN, FVS0, FVS1 or VFB to GND.... –0.3V to 7V
ACP, CHRG or ICL to GND........................... –0.3V to 30V
Operating Temperature Range
(Note 2).............................................. –40°C to 125°C
Junction Temperature (Note 3).............................. 125°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
LTC4009-1
LTC4009-2
20 19 18 17 16
15 CSP
CLN 1
CLP 2
14 CSN
CLP 2
BGATE
15 CSP
14 CSN
DCIN 3
13 PROG
21
INTVDD
20 19 18 17 16
CLN 1
DCIN 3
SW
BOOST
TOP VIEW
BGATE
INTVDD
SW
TGATE
BOOST
TOP VIEW
TGATE
LTC4009
13 PROG
21
11 BAT
6
7
8
9 10
FVS1
9 10
FVS0
8
VFB
7
FBDIV
6
CHRG
DCDIV 5
ACP
11 BAT
SHDN
12 ITH
DCDIV 5
CHRG
ICL 4
ACP
12 ITH
SHDN
ICL 4
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4009CUF#PBF
LTC4009CUF#TRPBF
4009
20-Lead (4mm × 4mm) Plastic QFN
0°C to 85°C
LTC4009CUF-1#PBF
LTC4009CUF-1#TRPBF
40091
20-Lead (4mm × 4mm) Plastic QFN
0°C to 85°C
LTC4009CUF-2#PBF
LTC4009CUF-2#TRPBF
40092
20-Lead (4mm × 4mm) Plastic QFN
0°C to 85°C
LTC4009IUF#PBF
LTC4009IUF#TRPBF
4009
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LTC4009IUF-1#PBF
LTC4009IUF-1#TRPBF
40091
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LTC4009IUF-2#PBF
LTC4009IUF-2#TRPBF
40092
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4009fd
LTC4009
LTC4009-1/LTC4009-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Charge Voltage Regulation
VTOL
VBAT Accuracy (See Test Circuits)
LTC4009
C-Grade
I-Grade
l
l
–0.5
–0.8
–1.0
0.5
0.8
1.0
%
%
%
LTC4009-1/LTC4009-2
C-Grade
FVS1 = 0V, FVS0 = 0V, I-Grade
FVS1 = 0V, FVS1 = 5V, I-Grade
FVS1 = 5V, FVS0 = 0V, I-Grade
FVS1 = 5V, FVS1 = 5V, I-Grade
l
l
l
l
l
–0.6
–0.8
–1.1
–1.15
–1.25
–1.35
0.6
0.8
1.1
1.15
1.25
1.35
%
%
%
%
%
%
IVFB
VFB Input Bias Current
VFB = 1.2V
RON
FBDIV On-Resistance
ILOAD = 100µA
l
ILEAK-FBDIV
FBDIV Output Leakage Current
SHDN = 0V, FBDIV = 0V
l
–1
VBOV
VFB Overvoltage Threshold
LTC4009
l
1.235
BAT Overvoltage Threshold
LTC4009-1/LTC4009-2, Relative to
Selected Output Voltage
l
103
106
l
l
–4
–5
–9.5
±20
85
nA
190
Ω
0
1
µA
1.281
1.32
V
109
%
4
5
9.5
%
%
%
Charge Current Regulation
ITOL
Charge Current Accuracy with RIN = 3.01k,
6V < BAT < 18V (LTC4009),
6V < BAT < 15V (LTC4009-1, LTC4009-2)
RPROG = 26.7k
C-Grade
I-Grade
VSENSE = 0mV, PROG = 1.2V
–12.75
–11.67
–10.95
µA
VSENSE Step from 0mV to 5mV,
PROG = 1.2V
–1.78
–1.66
–1.54
µA
140
125
195
325
250
265
430
mV
mV
mV
AI
Current Sense Amplifier Gain (PROG ∆I) with
RIN = 3.01k, 6V < BAT < 18V (LTC4009),
6V < BAT < 15V (LTC4009-1, LTC4009-2)
VCS-MAX
Maximum Peak Current Sense Threshold Voltage ITH = 2V, C-Grade
per Cycle (RIN = 3.01k)
ITH = 2V, I-Grade
ITH = 5V
l
l
l
VC10
C/10 Indicator Threshold Voltage
PROG Falling
340
400
460
mV
VREV
Reverse Current Threshold Voltage
PROG Falling
180
253
295
mV
97
96
92
100
100
103
104
108
mV
mV
mV
–2
mV
28
V
Input Current Regulation
VCL
Current Limit Threshold
CLP – CLN
C-Grade
I-Grade
l
l
ICLN
CLN Input Bias Current
CLN = CLP
VICL
ICL Indicator Threshold
(CLP – CLN) – VCL
–8
6
±100
–5
nA
DCIN, CLP Supplies
OVR
Operating Voltage Range
DCIN and CLP
IDCO
DCIN Operating Current
No Gate Loads
1.5
2
mA
ICLPO
CLP Operating Current
CLP = 20V, No Gate Loads
0.5
0.8
mA
VCBT
CLP Boost Threshold Voltage
VCNT
CLP Normal Threshold Voltage (Note 5)
VOVP
DCDIV Overvoltage Protection Threshold
DCDIV Rising
CLP – DCIN, CLP Rising
l
10
25
60
mV
DCIN – CLP, CLP Falling
l
10
25
60
mV
1.75
1.825
1.9
VOVP(HYST) DCDIV OVP Threshold Hysteresis
110
V
mV
Shutdown
VACP
DCDIV AC Present Threshold Voltage
VACP(HYST)
DCDIV ACP Threshold Hysteresis Voltage
IDCDIV
DCDIV Input Current
VIL
SHDN Input Voltage Low
DCDIV Rising
l
1.13
1.2
1.27
50
DCDIV = 1.2V
–1
l
0
V
mV
1
µA
300
mV
4009fd
LTC4009
LTC4009-1/LTC4009-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
VIH
SHDN Input Voltage High
RIN
SHDN Pull-Down Resistance
CONDITIONS
MIN
l
TYP
MAX
1.4
V
50
IDCS
DCIN Shutdown Current
SHDN = 0V
ICLPS
CLP Shutdown Current
CLP = 12V, SHDN = 0V or DCDIV = 0V
l
ILEAK-BAT
BAT Leakage Current
SHDN = 0V or DCDIV = 0V,
0V ≤ CSP = CSN = BAT ≤ 20V
l
ILEAK-CSN
CSN Leakage Current
SHDN = 0V or DCDIV = 0V,
0V ≤ CSP = CSN = BAT ≤ 20V
ILEAK-CSP
CSP Leakage Current
ILEAK-SW
SW Leakage Current
UNITS
kΩ
215
µA
9
18
µA
–1.5
0
1.5
µA
l
–1.5
0
1.5
µA
SHDN = 0V or DCDIV = 0V,
0V ≤ CSP = CSN = BAT ≤ 20V
l
–1.5
0
1.5
µA
SHDN = 0V or DCDIV = 0V,
0V ≤ SW ≤ 20V
l
–1
0
2
µA
l
4.85
5
5.15
V
INTVDD Regulator
INTVDD
Output Voltage
No Load
ΔVDD
Load Regulation
IDD = 20mA
IDD
Short-Circuit Current (Note 6)
INTVDD = 0V
–0.4
–1
%
50
85
130
mA
65
60
100
135
140
mV
mV
633
kHz
Switching Regulator
VCE
Charge Enable Threshold Voltage
IITH
ITH Current
fTYP
Typical Switching Frequency
fMIN
Minimum Switching Frequency
DCMAX
tR-TG
CLP – BAT, CLP Rising
C-Grade
I-Grade
l
l
ITH = 1.4V
–40/+90
µA
467
550
CLOAD = 3.3nF
20
25
Maximum Duty Cycle
CLOAD = 3.3nF
98
99
TGATE Rise Time
CLOAD = 3.3nF, 10% – 90%
60
110
ns
tF-TG
TGATE Fall Time
CLOAD = 3.3nF, 90% – 10%
50
110
ns
tR-BG
BGATE Rise Time
CLOAD = 3.3nF, 10% – 90%
60
110
ns
tF-BG
BGATE Fall Time
CLOAD = 3.3nF, 90% – 10%
60
110
tNO
TGATE, BGATE Non-Overlap Time
CLOAD = 3.3nF, 10% – 10%
110
kHz
%
ns
ns
Float Voltage Select Inputs (LTC4009-1/LTC4009-2 Only)
VIL
Input Voltage Low
VIH
Input Voltage High
IIN
Input Current
0.5
V
10
µA
500
mV
3.5
0V ≤ VIN ≤ 5V
V
–10
Indicator Outputs
VOL
Output Voltage Low
ILOAD = 100µA, PROG = 1.2V
ILEAK
Output Leakage
IC10
CHRG C/10 Current Sink
SHDN = 0V, DCDIV = 0V, VOUT = 20V
l
–10
CHRG = 2.5V
l
15
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4009C is guaranteed to meet performance specifications
over the 0°C to 85°C operating temperature range. The LTC4009I is
guaranteed to meet performance specifications over the –40°C to 125°C
operating temperature range.
Note 3: Operating junction temperature TJ (in °C) is calculated from
the ambient temperature TA and the total continuous package power
25
10
µA
38
µA
dissipation PD (in watts) by the formula TJ = TA + (θJA • PD). Refer to the
Applications Information section for details.
Note 4: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND, unless otherwise
specified.
Note 5: This threshold is guaranteed to be satisfied if CLP = DCIN when
the LTC4009 exits shutdown.
Note 6: Output current may be limited by internal power dissipation. Refer
to the Applications Information section for details.
4009fd
LTC4009
LTC4009-1/LTC4009-2
Test Circuits
LTC4009
1.2085V
PROG
13
LTC4009-1
LTC4009-2
FROM ICL
(CLP = CLN)
–
–
–
+
FROM ICL
(CLP = CLN)
EA
1.2085V
PROG
ITH
VFB
10
ITH
11
+
12
TARGET VARIES
WITH FVS0,1
LTC1055
–
EA
BAT
13
12
1.2085V
TARGET
–
–
–
+
+
LTC1055
–
0.6V
0.6V
4009 TC02
4009 TC01
Typical Performance Characteristics
(TA = 25°C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8µH)
Efficiency at DCIN = 20V, BAT = 8V
10000
RSENSE = 33mΩ
RIN = 3.01k
EFFICIENCY (%)
90
1000
EFFICIENCY
85
80
10000
RSENSE = 33mΩ
RIN = 3.01k
95
POWER LOSS
EFFICIENCY
90
85
0.5
0
1.0
1.5
2.0
CHARGE CURRENT (A)
2.5
100
3.0
80
0.5
0
1.0
1.5
2.0
CHARGE CURRENT (A)
4009 G01
RSENSE = 33mΩ
RIN = 3.01k
85
250
0.04
225
0.02
0
–0.02
0
0.5
1.0
1.5
2.0
CHARGE CURRENT (A)
2.5
4009 G03
–0.10
175
125
–0.06
100
3.0
200
150
–0.04
100
–0.08
80
CLP = BAT + 3V
(CLP ≥ 6V)
275
RON (Ω)
1000
VFB ERROR (%)
EFFICIENCY (%)
POWER LOSS
90
FBDIV RON vs BAT
0.06
EFFICIENCY
100
3.0
300
LTC4009 TEST CIRCUIT
0.08
POWER LOSS (mW)
95
0.10
10000
2.5
4009 G02
VFB Line Regulation
Efficiency at DCIN = 20V, BAT = 16V
100
1000
POWER LOSS (mW)
POWER LOSS
POWER LOSS (mW)
95
100
EFFICIENCY (%)
100
Efficiency at DCIN = 20V, BAT = 12V
5
10
20
15
CLP (V)
25
30
4009 G04
75
0
5
15
10
BAT (V)
20
25
4009 G05
4009fd
LTC4009
LTC4009-1/LTC4009-2
Typical Performance Characteristics
(TA = 25°C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8µH)
Charge Current Accuracy
2A
1A
12.1V
1A
3A
RECONNECT
LOAD
STATE
DISCONNECT
4009 G06
CLP = 20V
TIME (1ms/DIV)
VOUT = 12.3V
CHARGE CURRENT ERROR (%)
BATTERY VOLTAGE
(500mV/DIV)
5
Charge Current Line Regulation
0.5
RSENSE = 33mΩ
RIN = 3.01k
4
DCIN = 24V
RPROG = 35.7k
3
2
1
0
DCIN = 12V
RPROG = 26.7k
–1
–2
0
2
4
6
BAT = 6V
RSENSE = 33mΩ
RIN = 3.01k
0.4
CHARGE CURRENT ERROR (%)
Battery Load Dump
0.3
ICHG = 1A
0.2
0.1
ICHG = 2A
0
–0.1
ICHG = 3A
–0.2
–0.3
–0.4
–0.5
8 10 12 14 16 18 20 22 24
15
DCIN (V)
10
5
BAT (V)
3.0
ICHG = 3A
3.0
2.5
ICHG
2A/DIV
IIN
2.0
2.5
ICHG = 2A
2.0
CURRENT (A)
CHARGE CURRENT (A)
PWM Soft-Start
Input Current Limit
3.5
1.5
ICHG = 1A
1.0
DCIN = 20V
RSENSE = 33mΩ
RIN = 3.01k
–0.5
11.0
11.4
1.0
0.5
12.6
13.0
–1.0
PROG
1V/DIV
2.5A BULK CHARGE
2.1A INPUT CURRENT LIMIT
–0.5
11.8
12.2
BAT (V)
ITH
1V/DIV
ICHG
1.5
0
0.5
0
25
4009 G07
4009 G15
Charge Current Load Regulation
20
SHDN
5V/DIV
TIME (500µs/DIV)
ICL STATE
0
0.5
1.0
1.5
SYSTEM LOAD (A)
2.0
2.5
4009 G09
4009 G08
Gate Drive Non-Overlap
PWM Frequency vs Duty Cycle
BGATE
ICHG = 750mA
500
PWM FREQUENCY (kHz)
EXTERNAL FET DRIVE (1V/DIV)
600
TGATE
TIME (80ns/DIV)
4009 G10
4009 G11
400
300
200
CLP = 6V
CLP = 12V
CLP = 20V
CLP = 25V
100
0
0
20
40
60
DUTY CYCLE (%)
80
100
4009 G12
4009fd
LTC4009
LTC4009-1/LTC4009-2
Typical Performance Characteristics
(TA = 25°C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8µH)
PWM Frequency vs Charge Current
Battery Shutdown Current
25
600
PWM FREQUENCY (kHz)
BATTERY CURRENT (µA)
BAT = 5V
500
BAT = 12V
400
CLP = 15V
RSENSE = 33mΩ
RIN = 3.01k
300
200
0
0
0.5
1.0
1.5
2.0
CHARGE CURRENT (A)
DC1104 WITH
SSB44 INPUT
DIODE
15
LTC4009
ALL PINS
10
5
BAT = 14.5V
100
20
2.5
3.0
4009 G13
0
0
5
15
20
10
BATTERY VOLTAGE (V)
25
4009 G14
Pin Functions
CLN (Pin 1): Adapter Input Current Limit Negative Input.
The LTC4009 senses voltage on this pin to determine if
the charge current should be reduced to limit total input
current. The threshold is set 100mV below the CLP pin. An
external filter should be used to remove switching noise.
This input should be tied to CLP if not used. Operating
voltage range is (CLP – 110mV) to CLP.
condition exists. An external resistor divider programs
these threshold levels relative to DCIN. Operating voltage
range is GND to INTVDD.
CLP (Pin 2): Adapter Input Current Limit Positive Input.
The LTC4009 also draws power from this pin, including
a small amount for some shutdown functions. Operating
voltage range is GND to 28V.
ACP (Pin 7): Active-Low AC Adapter Present Indicator
Output. This open-drain output pulls to GND when adequate
AC adapter (DC) voltage is present, based on the DCDIV
input. This output should be left floating if not used.
DCIN (Pin 3): DC Power Input. The LTC4009 draws power
from this pin when an external DC power source is present.
This pin is typically isolated from the CLP pin by a diode
and should be bypassed with a capacitance of 0.1µF or
more. Operating voltage range is GND to 28V.
ICL (Pin 4): Active-Low Input Current Limit Indicator Output. This open-drain output pulls to GND when the charge
current is reduced because of AC adapter input current
limiting. This output should be left floating if not used.
DCDIV (Pin 5): AC Adapter Present Comparator Input. The
LTC4009 senses voltage on this pin to determine when an
adequate DC power source is present, or if an overvoltage
SHDN (Pin 6): Active-low Shutdown Input. Driving SHDN
below 300mV unconditionally forces the LTC4009 into the
shutdown state. This input has a 50kΩ internal pull-down
to GND. Operating voltage range is GND to INTVDD.
CHRG (Pin 8): Active-Low Charge Indicator Output. This
open-drain output provides three levels of information
about charge status using a strong pull-down, 25µA weak
pull-down or high impedance. Refer to the Operation and
Applications Information sections for further details. This
output should be left floating if not used.
FBDIV (Pin 9, LTC4009): Battery Voltage Feedback Resistor Divider Source. The LTC4009 connects this pin to BAT
when charging is in progress. FBDIV is an open-drain
PFET output to BAT with an operating voltage range of
GND to BAT.
4009fd
LTC4009
LTC4009-1/LTC4009-2
Pin Functions
FVS0 (Pin 9, LTC4009-1/LTC4009-2): Battery Voltage
Select Input (LSB). This pin is one of two pins used on the
LTC4009-1 or LTC4009-2 to select one of four preset battery
voltages. Selection is done by connecting to either GND or
INTVDD. Operating voltage range is GND to INTVDD.
CSP (Pin 15): Charge Current Sense Positive Input.
Place an external input resistor (RIN, Figure 1) between this pin and the positive side of the charge
current sense resistor. Operating voltage ranges from
(BAT – 50mV) to (BAT + 200mV).
VFB (Pin 10, LTC4009): Battery Voltage Feedback Input. An
external resistor divider between FBDIV and GND with the
center tap connected to VFB programs the charger output
voltage. In constant voltage mode, this pin is nominally
at 1.2085V. Refer to the Applications Information section
for complete details on programming battery float voltage.
Operating voltage range is GND to 1.25V.
BGATE (Pin 16): External Synchronous NFET Gate Control
Output. This output provides gate drive to an external NMOS
power transistor switch used for synchronous rectification
to increase efficiency in the step-down DC/DC converter.
Operating voltage is GND to INTVDD. BGATE should be
left floating if not used.
FVS1 (Pin 10, LTC4009-1/LTC4009-2): Battery Voltage
Select Input (MSB). This pin is one of two pins used on
the LTC4009-1 or LTC4009-2 to select one of four preset
battery voltages. Selection is done by connecting to
either GND or INTVDD. Operating voltage range is GND
to INTVDD.
BAT (Pin 11): Battery Pack Connection. The LTC4009 uses
the voltage on this pin to control PWM operation when
charging. Operating voltage range is GND to CLN.
ITH (Pin 12): PWM Control Voltage and Compensation
Node. The LTC4009 develops a voltage on this pin to
control cycle-by-cycle peak inductor current. An external
R-C network connected to ITH provides PWM loop compensation. Refer to the Applications Information section
for further details on establishing loop stability. Operating
voltage range is GND to INTVDD.
PROG (Pin 13): Charge Current Programming and Monitoring Pin. An external resistance connected between PROG
and GND, along with the current sense and PWM input
resistors, programs the maximum charge current. The
voltage on this pin can also provide a linearized indicator
of charge current. Refer to the Applications Information
section for complete details on current programming and
monitoring. Operating voltage range is GND to INTVDD.
CSN (Pin 14): Charge Current Sense Negative Input. Place an external input resistor (RIN, Figure 1)
between this pin and the negative side of the charge
current sense resistor. Operating voltage ranges from
(BAT – 50mV) to (BAT + 200mV).
INTVDD (Pin 17): Internal 5V Regulator Output. This pin
provides a means of bypassing the internal 5V regulator
used to power the LTC4009 PWM FET drivers. This supply
shuts down when the LTC4009 shuts down. Refer to the
Application Information section for details if additional
power is drawn from this pin by the application circuit.
SW (Pin 18): PWM Switch Node. The LTC4009 uses the
voltage on this pin as the source reference for its topside
NFET (PWM switch) driver. Refer to the Applications Information section for additional PCB layout suggestions
related to this critical circuit node. Operating voltage range
is GND to CLN.
TGATE (Pin 19): External NFET Switch Gate Control Output.
This output provides gate drive to an external NMOS power
transistor switch used in the DC/DC converter. Operating
voltage range is GND to (CLN + 5V).
BOOST (Pin 20): TGATE Driver Supply Input. A bootstrap
capacitor is returned to this pin from a charge network
connected to SW and INTVDD. Refer to the Applications
Information section for complete details on circuit topology and component values. Operating voltage ranges from
(INTVDD – 1V) to (CLN + 5V).
GND (Exposed Pad Pin 21): Ground. The package paddle
provides a single-point ground for the internal voltage
reference and other critical LTC4009 circuits. It must be
soldered to a suitable PCB copper ground pad for proper
electrical operation and to obtain the specified package
thermal resistance.
4009fd
LTC4009
LTC4009-1/LTC4009-2
Block Diagram
3
2
1
4
8
10
(LTC4009)
DCIN
BOOST AND
OV DETECTION
CLP
INPUT
CURRENT
LIMIT
CLN
ICL
CHRG
C/10
DETECTION
VFB
+
CSP
–
CSN
CA
+
–
EA
+
–
–
–
CC
R1
TO
INTERNAL CIRCUITS
PROG
BAT
BOOST
OSCILLATOR
TGATE
PWM
LOGIC
CHARGE
OVERVOLTAGE
9 FBDIV
5
7
6
DCDIV
ACP
TO
INTERNAL
CIRCIUTS
5V
REGULATOR
SW
INTVDD
BGATE
GND
SHUTDOWN
CONTROL
SHUTDOWN
TO
INTERNAL
CIRCUITS
14
13
1.2085V
REFERENCE
ITH
11
15
12
20
19
18
17
16
21
4009 BD01
SHDN
4009fd
LTC4009
LTC4009-1/LTC4009-2
Block Diagram
2
1
4
8
10
9
11
DCIN
BOOST AND
OV DETECTION
CLP
INPUT
CURRENT
LIMIT
CLN
ICL
CHRG
C/10
DETECTION
VFB
FVS1
FVS0
BAT
+
CSP
–
CSN
CA
OUTPUT
VOLTAGE
SELECT
+
CC
–
EA
R1
+
–
–
–
3
(LTC4009-1/LTC4009-2)
TO
INTERNAL CIRCUITS
PROG
BOOST
OSCILLATOR
TGATE
OVERVOLTAGE
PWM
LOGIC
TO
INTERNAL
CIRCIUTS
5V
REGULATOR
SW
INTVDD
BGATE
GND
5
7
6
DCDIV
ACP
SHUTDOWN
CONTROL
SHUTDOWN
TO
INTERNAL
CIRCUITS
14
13
1.2085V
REFERENCE
ITH
CHARGE
15
12
20
19
18
17
16
21
4009 BD02
SHDN
4009fd
10
LTC4009
LTC4009-1/LTC4009-2
Operation
Overview
The LTC4009 is a synchronous step-down (buck) current
mode PWM battery charger controller. The maximum
charge current is programmed by the combination of a
charge current sense resistor (RSENSE), matched input
resistors (RIN, Figure 1), and a programming resistor
(RPROG) between the PROG and GND pins. Battery voltage is programmed either with an external resistor divider
between FBDIV and GND (LTC4009) or two digital battery
voltage select pins (LTC4009-1/LTC4009-2). In addition,
the PROG pin provides a linearized voltage output of the
actual charge current.
The LTC4009 family does not have any built-in charge
termination and is flexible enough for charging any type
of battery chemistry. These are building block ICs intended
for use with an external circuit, such as a microcontroller,
capable of managing the entire algorithm required for
the specific battery being charged. Each member of the
LTC4009 family features a shutdown input and various state
indicator outputs, allowing easy and direct management by
a wide range of external (digital) charge controllers. Due
to the popularity of rechargeable lithium-ion chemistries,
the LTC4009-1 and LTC4009-2 also offer internal precision
resistors that can be digitally selected to produce one of
four preset output voltages for simplified design of those
charger types.
Shutdown
The LTC4009 remains in shutdown until DCDIV exceeds
1.2V, and SHDN is driven above 1.4V. In shutdown, current
drain from the battery is reduced to the lowest possible
level, thereby increasing standby time. When in shutdown,
the ITH pin is pulled to GND and the CHRG, ICL, FET gate
drivers and INTVDD output are all disabled. The ACP status
output indicates sensed adapter input voltage during all
LTC4009 states. Charging can be stopped at any time by
forcing SHDN below 300mV.
Soft-Start
CLP exceeds BAT by 100mV and ITH exceeds a threshold
that assures initial current will be positive (about 5% to
25% of the maximum programmed current). To limit inrush
current, soft-start delay is created with the compensation
values used on the ITH pin. Longer soft-start times can be
realized by increasing the filter capacitor on ITH, if reduced
loop bandwidth is acceptable. The actual charge current at
the end of soft-start will depend on which loop (current,
voltage or adapter limit) is in control of the PWM. If this
current is below that required by the ITH start-up threshold,
the resulting charge current transient duration depends on
loop compensation but is typically less than 100µs.
Bulk Charge
When soft-start is complete, the LTC4009 begins sourcing the current programmed by the external components
connected to CSP, CSN and PROG. Some batteries may
require a small conditioning trickle current if they are heavily
discharged. As shown in the Applications Information section, the LTC4009 can address this need through a variety
of low current circuit techniques on the PROG pin. Once
a suitable cell voltage has been reached, charge current
can be switched to a higher, bulk charge value.
End-of-Charge and CHRG Output
As the battery approaches the programmed output voltage, charge current will begin to decrease. The opendrain CHRG output can indicate when the current drops
to 10% of its programmed full-scale value by turning off
the strong pull-down (open-drain FET) and turning on a
weak 25µA pull-down current. This weak pull-down state
is latched until the part enters shutdown or the sensed
current rises to roughly C/6. C/10 indication will not be
set if charge current has been reduced due to adapter
input current limiting or DCIN/battery overvoltage. As
the charge current approaches 0A, the PWM continues to
operate in full continuous mode. This avoids generation
of audible noise, allowing bulk ceramic capacitors to be
used in the application.
Exiting the shutdown state enables the charger and releases
the ITH pin. When enabled, switching will not begin until
4009fd
11
LTC4009
LTC4009-1/LTC4009-2
Operation
LTC4009
2
11
WATCHDOG
TIMER
CLP
BAT
CLOCK
OSCILLATOR
S
SYSTEM
POWER
TGATE
Q
PWM
LOGIC
RD
BGATE
+
+
CSP
–
CSN
19
L1
16
RIN
15
CA
CC
R1
–
PROG
FROM ICL
VFB
RSENSE
RIN
14
VSENSE
–
ICHRG
13
RPROG
+
–
–
–
EA
+
CPROG
+
10
1.2085V
ITH
12
LOOP
COMPENSATION
4009 F01
Figure 1. PWM Circuit Diagram
Charge Current Monitoring
When the LTC4009 is charging, the voltage on the PROG pin
varies in direct proportion to the charge current. Referring
to Figure 1, the nominal PROG voltage is given by
VPROG =
ICHRG • RSENSE • RPROG
+ 11.67µA • RPROG
RIN
Voltage tolerance on PROG is limited by the charge current
accuracy specified in the Electrical Characteristics table.
Refer to the Applications Information section on programming charge current for additional details.
Adapter Input Current Limit
The LTC4009 can monitor and limit current from the input
DC supply, which is normally an AC adapter. When the
programmed adapter input current is reached, charge
current is reduced to maintain the desired maximum input
current. The ITH and PROG pins will reflect the reduced
charge current. This limit function avoids overloading the
DC input source, allowing the product to operate at the
same time the battery is charging without complex load
management algorithms. The battery will automatically be
charged at the maximum possible rate that the adapter will
support, given the application’s operating condition. The
LTC4009 can only limit input current by reducing charge
current, and in this case the charger uses nonsynchronous PWM operation to prevent boosting if the average
charge current falls below about 25% of the maximum
programmed current. Note that the ICL indicator output
becomes active (low) at an adapter input current level just
slightly less than that required for the internal amplifier to
begin to assert control over the PWM loop.
If system load current equals or exceeds the input adapter
current limit for more than a few milliseconds, the bootstrap
capacitor between BOOST and SW can fully discharge due
to normal pin leakage currents. In this case, the PWM will
not restart until the system current has dropped to about
85% of the programmed input adapter limit value.
Charger Status Indicator Outputs
The LTC4009 open-drain indicator outputs provide valuable information about the IC’s operating state and can
4009fd
12
LTC4009
LTC4009-1/LTC4009-2
Operation
be used for a variety of purposes in applications. Table 1
summarizes the state of the three indicator outputs as a
function of LTC4009 operation.
Table 1. LTC4009 Open-Drain Indicator Outputs
ACP
CHRG
ICL
CHARGER STATE
Off
Off
Off
No DC Input (Shutdown)
On
Off
Off
Shutdown, Reverse Current or
DCIN Overvoltage
On
On
Off
Bulk Charge
On
25µA
Off
Low Current Charge or Initial
CLP-BAT < 100mV
On
On
On
Input Current Limit During Bulk
Charge
On
25µA
On
Input Current Limit During Low
Current Charge
On
Off
On
Input Current Limit During DCIN
Overvoltage
PWM Controller
The LTC4009 uses a synchronous step-down architecture to produce high operating efficiency. The nominal
operating frequency of 550kHz allows use of small filter
components. The following conceptual discussion of basic
PWM operation references Figure 1.
The voltage across the external charge current sense
resistor RSENSE is measured by current amplifier, CA. This
instantaneous current (VSENSE/RIN) is fed to the PROG pin
where it is averaged by an external capacitor and converted
to a voltage by the programming resistor RPROG between
PROG and GND. The PROG voltage becomes the average
ON
charge current input signal to error amplifier, EA. EA also
receives loop control information from the battery voltage
feedback input VFB and the adapter input current limit
circuit. The ITH output of the error amplifier is a scaled
control voltage for one input of the PWM comparator, CC.
ITH sets a peak inductor current threshold, sensed by R1,
to maintain the desired average current through RSENSE.
The current comparator output does this by switching the
state of the RS latch at the appropriate time.
At the beginning of each oscillator cycle, the PWM clock
sets the RS latch and turns on the external topside NFET
(bottom-side synchronous NFET off) to refresh the current
carried by the external inductor L1. The inductor current
and voltage across RSENSE begin to rise linearly. CA buffers
this instantaneous voltage rise and applies it to CC with
gain supplied by R1. When the voltage across R1 exceeds
the peak level set by the ITH output of EA, the top FET
turns off and the bottom FET turns on. The inductor current then ramps down linearly until the next rising PWM
clock edge. This closes the loop and sources the correct
inductor current to maintain the desired parameter (charge
current, battery voltage, or input current). To produce a
near constant frequency, the PWM oscillator implements
the equation:
tOFF =
CLP – BAT
CLP • 550kHz
Repetitive, closed-loop waveforms for stable PWM operation appear in Figure 2.
tOFF
TOP FET
OFF
ON
BOTTOM FET
OFF
THRESHOLD
SET BY ITH
VOLTAGE
INDUCTOR
CURRENT
4009 F02
Figure 2. PWM Waveforms
4009fd
13
LTC4009
LTC4009-1/LTC4009-2
Operation
PWM Watchdog Timer
As input and output conditions vary, the LTC4009 may need
to utilize PWM duty cycles approaching 100%. In this case,
operating frequency may be reduced well below 550kHz.
An internal watchdog timer observes the activity on the
TGATE pin. If TGATE is on for more than 40µs, the watchdog
activates and forces the bottom NFET on (top NFET off)
for about 100ns. This avoids a potential source of audible
noise when using ceramic input or output capacitors and
prevents the boost supply capacitor for the top gate driver
from discharging. In low drop out operation, the actual
charge current may not be able to reach the programmed
full-scale value due to the watchdog function.
Overvoltage Protection
The LTC4009 also contains overvoltage detection that
prevents transient battery voltage overshoots of more than
about 6% above the programmed output voltage. When
battery overvoltage is detected, both external MOSFETs are
turned off until the overvoltage condition clears, at which
time a new soft start sequence begins. This is useful for
properly charging battery packs that use an internal switch
to disconnect themselves for performing functions such
as calibration or pulse mode charging.
Reverse Charge Current Protection (Anti-Boost)
Because the LTC4009 always attempts to operate synchronously in full continuous mode (to avoid audible noise from
ceramic capacitors), reverse average charge current can
occur during some invalid operating conditions. To avoid
boosting a lightly loaded system supply during reverse
operation, the LTC4009 monitors the voltage on CLP to
determine if it rises 25mV above DCIN during charge.
However, under heavier system loads, CLP may not boost
above DCIN, even though reverse average current is flowing. In this case a second circuit monitors indication of
reverse average current on PROG.
If the designer intends to replace the input diode with a
MOSFET for improved efficiency, using the ACP signal of
the LTC4009 to control the MOSFET is not recommended.
In this case, the LTC4012 is strongly suggested, because
it includes ideal diode control of the MOSFET, instead of
driving it as a simple switch. This solution is the most effective at detecting boost conditions and quickly shutting
down the IC. If for some reason the LTC4012 solution is
not acceptable, and a MOSFET with external control is
used to replace the input diode, and there are conditions
involving very low reverse current under no system load
with an AC adapter that cannot sink current, it may still
be possible to boost the DCIN input supply. To cover this
case, the LTC4009 monitors the resistor divider attached
to the DCDIV pin and sets an input overvoltage fault if that
voltage exceeds 1.825V.
If any of these circuits detects boost operation, The LTC4009
turns off both external MOSFETs until the reverse current
condition clears. Once DCIN-CLP > 25mV, a new soft-start
sequence begins.
4009fd
14
LTC4009
LTC4009-1/LTC4009-2
Applications Information
Programming Charge Current
The formula for charge current is:
ICHRG =
RIN
RSENSE
 1.2085V

•
– 11.67µA
 RPROG

The LTC4009 operates best with 3.01k input resistors,
although other resistors near this value can be used to
accommodate standard sense resistor values. Refer to
the subsequent discussion on inductor selection for other
considerations that come into play when selecting input
resistors RIN.
RSENSE should be chosen according to the following
equation:
RSENSE =
The resistance between PROG and GND can simply be
set with a single a resistor, if only maximum charge current needs to be controlled during the desired charging
algorithm. However, some batteries require a low charge
current for initial conditioning when they are heavily discharged. The charge current can then be safely switched
to a higher level after conditioning is complete. Figure 3
illustrates one method of doing this with 2-level control
of the PROG pin resistance. Turning Q1 off reduces the
charge current to IMAX/10 for battery conditioning. When
Q1 is on, the LTC4009 is programmed to allow full IMAX
current for bulk charge. This technique can be expanded
through the use of additional digital control inputs for an
arbitrary number of pre-programmed current values.
100mV
IMAX
where IMAX is the desired maximum charge current ICHRG.
The 100mV target can be adjusted to some degree to obtain
standard RSENSE values and/or a desired RPROG value, but
target voltages lower than 100mV will cause a proportional
reduction in current regulation accuracy.
The required minimum resistance between PROG and GND
can be determined by applying the suggested expression
for RSENSE while solving the first equation given above for
charge current with ICHRG = IMAX:
1.2085V • RIN
RPROG(MIN) =
0.1V + 11.67µA • RIN
If RIN is chosen to be 3.01k with a sense voltage of 100mV,
this equation indicates a minimum value for RPROG of
26.9k. Table 6 gives some examples of recommended
charge current programming component values based
on these equations.
LTC4009
PROG
13
BULK
CHARGE
PRECHARGE
R1
26.7k
Q1
2N7002
R2
53.6k
CPROG
4.7nF
4009 F03
Figure 3. Programming 2-Level Charge Current
For a truly continuous range of maximum charge current
control, pulse width modulation can be used as shown in
Figure 4. The value of RPROG controls the maximum value
of charge current which can be programmed (Q1 continuously on). PWM of the Q1 gate voltage changes the value
of RPROG to produce lower currents. The frequency of this
modulation should be higher than a few kHz, and CPROG
must be increased to reduce the ripple caused by switching Q1. In addition, it may be necessary to increase loop
4009fd
15
LTC4009
LTC4009-1/LTC4009-2
Applications Information
BAT
LTC4009
95Ω
TYPICAL
PROG
11
13
FBDIV
RMAX
511k
RPROG
5V
0V
Q1
2N7002
9
CZ
R1
LTC4009
+
CPROG
VFB 10
R2A
4009 F04
R2B*
GND
(EXPOSED PAD) 21
Figure 4. Programming PWM Current
compensation capacitance connected to ITH to maintain
stability or prevent large current overshoot during startup. Selecting a higher Q1 PWM frequency (≈10kHz) will
reduce the need to change CPROG or other compensation
values.Charge current will be proportional to the duty cycle
of the PWM input on the gate of Q1.
Programming LTC4009 Output Voltage
Figure 5 shows the external circuit for programming the
charger voltage when using the LTC4009. The voltage is
then governed by the following equation:
VBAT =
1.2085V • (R1+ R2)
, R2 = R2A + R2B
R2
See Table 2 for approximate resistor values for R2.
 V

R1 = R2  BAT – 1 , R2 = R2A + R2B
 1.2085V 
Selecting R2 to be less than 50k and the sum of R1 and
R2 at least 200k or above, achieves the lowest possible
error at the VFB sense input. Note that sources of error
such as R1 and R2 tolerance, FBDIV RON or VFB input
impedance are not included in the specifications given in
the Electrical Characteristics. This leads to the possibility that very accurate (0.1%) external resistors might be
4009 F05
*OPTIONAL TRIM RESISTOR
Figure 5. Programming LTC4009 Output Voltage
required. Actually, the temperature rise of the LTC4009 will
rarely exceed 50°C at the end of charge, because charge
current will have tapered to a low level. This means that
0.25% resistors will normally provide the required level of
overall accuracy. Table 2 gives recommended values for
R1 and R2 for popular lithium-ion battery voltages. For
values of R1 above 200k, addition of capacitor CZ may
improve transient response and loop stability. A value of
10pF is normally adequate.
Table 2. Programming LTC4009 Output Voltage
VBAT VOLTAGE
R1 (0.25%)
R2A (0.25%)
R2B (1%)*
4.1V
165k
69.0k
–
4.2V
167k
67.3k
200
8.2V
162k
28.0k
–
8.4V
169k
28.4k
–
12.3V
301k
32.8k
–
12.6V
294k
31.2k
–
16.4V
284k
22.6k
–
16.8V
271k
21.0k
–
20.5V
316k
19.8k
–
21.0V
298k
18.2k
–
24.6V
298k
15.4k
–
25.2V
397k
20.0k
–
*To obtain required accuracy requires series resistors for R2.
4009fd
16
LTC4009
LTC4009-1/LTC4009-2
Applications Information
Programming LTC4009-1/LTC4009-2 Output Voltage
The LTC4009-1/LTC4009-2 feature precision internal battery voltage feedback resistor taps configured for common
lithium-ion voltages. All that is required to program the
desired voltage is proper pin programming of FVS0 and
FVS1 as shown in Table 3.
CDC
2
FVS1
FVS0
4.1V
4.2V
GND
GND
8.2V
8.4V
GND
INTVDD
12.3V
12.6V
INTVDD
GND
16.4V
16.8V
INTVDD
INTVDD
Programming Input Current Limit
To set the input current limit, ILIM, the minimum wall
adapter current rating must be known. To account for the
tolerance of the LTC4009 input current sense circuit, 5%
should be subtracted from the adapter’s minimum rated
output. Refer to Figure 6 and program the input current
limit function with the following equation.
RCL =
100mV
ILIM
where ILIM is the desired maximum current draw from
the DC (adapter) input, including adjustments for tolerance, if any.
Often an AC adapter will include a rated current output
margin of at least +10%. This can allow the adapter current limit value to simply be programmed to the actual
minimum rated adapter output current. Table 4 shows
some common RCL current limit programming values.
A lowpass filter formed by RF (5.1k) and CF (0.1µF) is
required to eliminate switching noise from the LTC4009
PWM and other system components. If input current limiting is not desired, CLN should be shorted to CLP while
CLP remains connected to power.
1
CLN
LTC4009
4009 F06
Figure 6. Programming Input Current Limit
VBAT VOLTAGE
LTC4009-2
TO REMAINDER
OF SYSTEM
RF
5.1k
CF 0.1µF
10k
CLP
Table 3. LTC4009-1/LTC4009-2 Output Voltage Programming
LTC4009-1
RCL
FROM DC
POWER INPUT
Table 4. Common RCL Values
ADAPTER
RATING
RCL VALUE (1%)
RCL POWER
DISSIPATION
RCL POWER
RATING
0.50A
0.200Ω
0.050W
0.25W
0.75A
0.133Ω
0.075W
0.25W
1.00A
0.100Ω
0.100W
0.25W
1.25A
0.080Ω
0.125W
0.25W
1.50A
0.067Ω
0.150W
0.25W
1.75A
0.057Ω
0.175W
0.25W
2.00A
0.050Ω
0.200W
0.25W
Figure 7 shows an optional circuit that can influence the
parameters of the input current limit in two ways. The
first option is to lower the power dissipation of RCL at the
expense of accuracy without changing the input current
DCIN
D1
INPUT DIODE
CLP
2
LTC4009
CLN
1
INTVDD 17
CF
0.22µF
RF
2.49k 1%
R2
RCL
1%
TO REMAINDER
OF SYSTEM
Q2
2SC2412
Q1
IMX1
R1
1%
R3 = R1
1%
4009 F07
Figure 7. Adjusting Input Current Limit
4009fd
17
LTC4009
LTC4009-1/LTC4009-2
Applications Information
limit value. The second is to make the input current limit
value programmable.
The overall accuracy of this circuit needs to be better than
the power source current tolerance or be margined such
that the worse-case error remains under the power source
limits. The accuracy of the Figure 7 circuit is a function of
the INTVDD, VBE, RCL, RF, R1 and R3 tolerances. To improve
accuracy, the tolerance of RF should be changed from
5.1k, 5% to a 2.49k 1% resistor. RCL and the programming
resistors R1 and R3 should also be 1% tolerance such
that the dominant error is INTVDD (±3%). Bias resistor R2
can be 5%. When choosing NPN transistors, both need
to have good gain (>100) at 10µA levels. Low gain NPNs
will increase programming errors. Q1 must be a matched
NPN pair. Since RF has been reduced in value by half, the
capacitor value of CF should double to 0.22µF to remain
effective at filtering out any noise.
If you wish to reduce RCL power dissipation for a given
current limit, the programming equation becomes:
RCL
 5 • 2.49k 
100mV – 
 R1 
=
ILIM
If you wish to make the input current limit programmable,
the equation becomes:
 5 • 2.49k 
100mV – 
 R1 
ILIM =
RCL
The equation governing R2 for both applications is based
on the value of R1. R3 should always be equal to R1.
R2 = 0.875 • R1
In many notebook applications, there are situations
where two different ILIM values are needed to allow two
different power adapters or power sources to be used.
In such cases, start by setting RLIM for the high power
ILIM configuration and then use Figure 7 to set the lower
ILIM value. To toggle between the two ILIM values, take
the three ground connections shown in Figure 7, combine
them into one common connection and use a small-signal
NFET (2N7002) to open or close that common connection to circuit ground. When the NFET is off, the circuit
is defeated (floating) allowing ILIM to be the maximum
value. When the NFET is on, the circuit will become active
and ILIM will drop to the lower set value.
Monitoring Charge Current
The PROG pin voltage can be used to indicate charge current where 1.2085V indicates full programmed current (1C)
and zero charge current is approximately equal to RPROG •
11.67µA. PROG voltage varies in direct proportion to the
charge current between this zero-current (offset) value and
1.2085V. When monitoring the PROG pin voltage, using a
buffer amplifier as shown in Figure 8 will minimize charge
current errors. The buffer amplifier may be powered from
the INTVDD pin or any supply that is always on when the
charger is on.
INTVDD 17
LTC4009
–
+
PROG 13
<30nA
TO SYSTEM
MONITOR
4009 F08
Figure 8. PROG Voltage Buffer
C/10 CHRG Indicator
The value chosen for RPROG has a strong influence on
charge current monitoring and the accuracy of the C/10
charge indicator output (CHRG). The LTC4009 uses the
voltage on the PROG pin to determine when charge current
has dropped to the C/10 threshold. The nominal threshold
of 400mV produces an accurate low charge current indication of C/10 as long as RPROG = 26.7k, independent of
all other current programming considerations. However,
it may sometimes be necessary to deviate from this value
to satisfy other application design goals.
4009fd
18
LTC4009
LTC4009-1/LTC4009-2
Applications Information
If RPROG is greater than 26.7k, the actual level at which
low charge current is detected will be less than C/10. The
highest value of RPROG that can be used while reliably
indicating low charge current before reaching final VBAT
is 30.1k. RPROG can safely be set to values higher than
this, but low current indication will be lost.
If RPROG is less than 26.7k, low charge current detection
occurs at a level higher than C/10. More importantly, the
LTC4009 becomes increasingly sensitive to reverse current. The lowest value of RPROG that can be used without
the risk of erroneous boost operation detection at end of
charge is 26.1k. Values of RPROG less than this should not
be used. See the Operation section for more information
about reverse current.
that is actually greater than C/10. If external circuitry is
insensitive to, or can ignore, this momentary C/10 indication at start-up, the capacitor can be omitted.
By using two different value pull-up resistors, a microprocessor can detect three states from this pin (charging,
C/10 and not charging). See Figure 10. When a digital
output port (OUT) from the microprocessor drives one
of the resistors and a second digital input port polls the
network, the charge state can be determined as shown
in Table 5.
3.3V
LTC4009
The nominal fractional value of IMAX at which C/10 indication occurs is given by:
VDD
200k
33k
CHRG 8
µP
OUT
IN
4009 F10
400mV – (RPROG • 11.67µA)
IC10
=
IMAX 1.2085V – (RPROG • 11.67µA)
Figure 10. Microprocessor Status Interface
Direct digital monitoring of C/10 indication is possible with
an external application circuit like the one shown in Figure 9.
The LTC4009 initially indicates C/10 until the PWM has
started and the actual charge current can be determined
(PROG pin voltage). The 0.1µF capacitor from CHRG to
GND is used to filter this initial pulse, which is typically
less than 2ms when starting toward a final charge current
Table 5. Digital Read Back State (IN, Figure 10)
OUT STATE
LTC4009
CHARGER STATE
Hi-Z
1
Off
1
1
C/10 Charge
0
1
Bulk Charge
0
0
VLOGIC
INTVDD 17
100k
100k
Q1
TP0610T
LTC4009
CHRG
100k
C/10
CHRG
Q2
2N7002
8
0.1µF
Q3
2N7002
100k
4009 F09
Figure 9. Digital C/10 Indicator
4009fd
19
LTC4009
LTC4009-1/LTC4009-2
Applications Information
Input and Output Capacitors
In addition to typical input supply bypassing (0.1µF) on
DCIN, the relatively high ESR of aluminum electrolytic
capacitors is helpful for reducing ringing when hot plugging the charger to the AC adapter. Refer to LTC Application
Note 88 for more information.
The input capacitor between system power (drain of top
FET, Figure 1) and GND is required to absorb all input PWM
ripple current, therefore it must have adequate ripple current
rating. Maximum RMS ripple current is typically one-half
of the average battery charge current. Actual capacitance
value is not critical, but using the highest possible voltage
rating on PWM input capacitors will minimize problems.
Consult with the manufacturer before use.
The output capacitor shown across the battery and ground
must also absorb PWM output ripple current. The general
formula for this capacitor current is:
IRMS =
 V 
0.29 • VBAT • 1 – BAT
 VCLP 
L1 • fPWM
For example, IRMS = 0.22A with:
VBAT = 12.6V
VCLP = 19V
L1 = 10µH
fPWM = 550kHz
High capacity ceramic capacitors (20µF or more) available
from a variety of manufacturers can be used for input/output capacitors. Other alternatives include OS-CON and
POSCAP capacitors from Sanyo.
Low ESR solid tantalum capacitors have high ripple current rating in a relatively small surface mount package,
but exercise caution when using tantalum for input or
output bulk capacitors. High input surge current can be
created when the adapter is hot-plugged to the charger
or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when
subjected to very high surge currents. Select tantalum
capacitors that have high surge current ratings or have
been surge tested.
EMI considerations usually make it desirable to minimize
ripple current in battery leads. Adding Ferrite beads or
inductors can increase battery impedance at the nominal
550KHz switching frequency. Switching ripple current splits
between the battery and the output capacitor in inverse
relation to capacitor ESR and the battery impedance. If
the ESR of the output capacitor is 0.2Ω and the battery
impedance is raised to 4Ω with a ferrite bead, only 5% of
the current ripple will flow to the battery.
Inductor Selection
Higher switching frequency generally results in lower
efficiency because of MOSFET gate charge losses, but it
allows smaller inductor and capacitor values to be used.
A primary effect of the inductor value L1 is the amplitude
of ripple current created. The inductor ripple current ΔIL
decreases with higher inductance and PWM operating
frequency:
 V 
VBAT • 1 – BAT 
 VCLP 
∆IL =
L1 • fPWM
Accepting larger values of ΔIL allows the use of low inductance, but results in higher output voltage ripple and
greater core losses. Lower charge currents generally call
for larger inductor values.
4009fd
20
LTC4009
LTC4009-1/LTC4009-2
Applications Information
The LTC4009 limits maximum instantaneous peak inductor
current during every PWM cycle. To avoid unstable switch
waveforms, the ripple current must satisfy:
assuming that inductor value could also vary by 25% at
IMAX. For I-grade parts, reduce maximum ΔIL to less than
0.4 • IMAX, but only if the IC will actually be used to charge
batteries over the wider I-grade temperature range. In that
case, a good starting point can be found by multiplying
the inductor values shown in Table 6 by a factor of 1.6 and
rounding up to the nearest standard value.
 150mV

∆IL < 2 • 
– IMAX 
 RSENSE

so choose:
Table 6. Minimum Typical Inductor Values
VCLP
L1 (Typ)
IMAX
RSENSE
0.125 • VCLP
L1 >
 150mV

fPWM • 
– IMAX 
 RSENSE

For C-grade parts, a reasonable starting point for setting
ripple current is ΔIL = 0.4 • IMAX. For I-grade parts, use ΔIL
= 0.2 • IMAX only if the IC will actually be used to charge
batteries over the wider I-grade temperature range. The
voltage compliance of internal LTC4009 circuits also imposes limits on ripple current. Select RIN (in Figure 1) to
avoid average current errors in high ripple designs. The
following equation can be used for guidance:
INTVDD 17
SW 18
100mΩ
26.7k
1A
100mΩ
3.01k
26.7k
1A
10V to 20V
≥20µH
>20V
≥28µH
1A
100mΩ
3.01k
26.7k
<10V
≥5.1µH
2A
50mΩ
3.01k
26.7k
10V to 20V
≥10µH
2A
50mΩ
3.01k
26.7k
>20V
≥14µH
2A
50mΩ
3.01k
26.7k
TGATE BOOST Supply
RIN should not be less than 2.37k or more than 6.04k. Values of RIN greater than 3.01k may cause some reduction in
programmed current accuracy. Use these equations and
guidelines, as represented in Table 6, to help select the correct inductor value. This table was developed for C-grade
parts to maintain maximum ΔIL near 0.6 • IMAX with fPWM at
550kHz and VBAT = 0.5 • VCLP (the point of maximum ΔIL),
LTC4009
RPROG
≥10µH
To guarantee that a chosen inductor is optimized in any
given application, use the design equations provided and
perform bench evaluation in the target application, particularly at duty cycles below 20% or above 80% where
PWM frequency can be much less than the nominal value
of 550kHz.
RSENSE • ∆IL
R
• ∆IL
≤ RIN ≤ SENSE
50µA
20µA
BOOST 20
RIN
3.01k
<10V
Use the external components shown in Figure 11 to develop a bootstrapped BOOST supply for the TGATE FET
driver. A good set of equations governing selection of the
two capacitors is:
C1 =
D1
1N4148
C2
2µF
20 • QG
, C2 = 20 • C1
4.5V
C1
0.1µF
L1
4009 F11
TO
RSENSE
Figure 11. TGATE Boost Supply
4009fd
21
LTC4009
LTC4009-1/LTC4009-2
Applications Information
where QG is the rated gate charge of the top external NFET
with VGS = 4.5V. The maximum average diode current is
then given by:
ID = QG • 665kHz
To improve efficiency by increasing VGS applied to the top
FET, substitute a Schottky diode with low reverse leakage
for D1.
PWM jitter has been observed in some designs operating
at higher VIN/VOUT ratios. This jitter does not substantially
affect DC charge current accuracy. A series resistor with a
value of 5Ω to 20Ω can be inserted between the cathode
of D1 and the BOOST pin to remove this jitter if present.
A resistor case size of 0603 or larger is recommended to
lower ESL and achieve the best results.
FET Selection
Two external power MOSFETs must be selected for use
with the charger: an N-channel power switch (top FET)
and an N-channel synchronous rectifier (bottom FET).
Peak gate-to-source drive levels are internally set to about
5V. Consequently, logic-level FETs must be used. In addition to the fundamental DC current, selection criteria for
these MOSFETs also include channel resistance RDS(ON),
total gate charge QG, reverse transfer capacitance CRSS,
maximum rated drain-source voltage BVDSS and switching
characteristics such as td(ON/OFF). Power dissipation for
each external FET is given by:
PD(TOP) =
VBAT • IMAX 2 • (1+ δ∆T)RDS(ON)
VCLP
where δ is the temperature dependency of RDS(ON), ΔT
is the temperature rise above the point specified in the
FET data sheet for RDS(ON) and k is a constant inversely
related to the internal LTC4009 top gate driver. The term
(1 + δΔT) is generally given for a MOSFET in the form
of a normalized RDS(ON) curve versus temperature, but
δ of 0.005/°C can be used as a suitable approximation
for logic-level FETs if other data is not available. CRSS =
QGD/dVDS is usually specified in the MOSFET characteristics. The constant k = 2 can be used in estimating top
FET dissipation. The LTC4009 is designed to work best
with external FET switches with a total gate charge at 5V
of 15nC or less.
For VCLP < 20V, high charge current efficiency generally
improves with larger FETs, while for VCLP > 20V, top gate
transition losses increase rapidly to the point that using
a topside NFET with higher RDS(ON) but lower CRSS can
actually provide higher efficiency. If the charger will be
operated with a duty cycle above 85%, overall efficiency
is normally improved by using a larger top FET.
The synchronous (bottom) FET losses are greatest at high
input voltage or during a short circuit, which forces a low
side duty cycle of nearly 100%. Increasing the size of this
FET lowers its losses but increases power dissipation in the
LTC4009. Using asymmetrical FETs will normally achieve
cost savings while allowing optimum efficiency.
Select FETs with BVDSS that exceeds the maximum VCLP
voltage that will occur. Both FETs are subjected to this level
of stress during operation. Many logic-level MOSFETs are
limited to 30V or less.
+ k • VCLP 2 • IMAX • CRSS • 665kHz
PD(BOT)
VCLP – VBAT ) • IMAX 2 • (1+ δ∆T)RDS(ON)
(
=
VCLP
4009fd
22
LTC4009
LTC4009-1/LTC4009-2
Applications Information
The LTC4009 uses an improved adaptive TGATE and
BGATE drive that is insensitive to MOSFET inertial delays,
td(ON/OFF), to avoid overlap conduction losses. Switching
characteristics from power MOSFET data sheets apply
only to a specific test fixture, so there is no substitute for
bench evaluation of external FETs in the target application.
In general, MOSFETs with lower inertial delays will yield
higher efficiency.
Diode Selection
A Schottky diode in parallel with the bottom FET and/or
top FET in an LTC4009 application clamps SW during the
non-overlap times between conduction of the top and
bottom FET switches. This prevents the body diode of the
MOSFETs from forward biasing and storing charge, which
could reduce efficiency as much as 1%. One or both diodes
can be omitted if the efficiency loss can be tolerated. A 1A
Schottky is generally a good size for 3A chargers due to the
low duty cycle of the non-overlap times. Larger diodes can
actually result in additional efficiency (transition) losses
due to larger junction capacitance.
Loop Compensation and Soft-Start
The three separate PWM control loops of the LTC4009
can be compensated by a single set of components attached between the ITH pin and GND. As shown in the
typical LTC4009 application, a 6.04k resistor in series
with a capacitor of at least 0.1µF provides adequate loop
compensation for the majority of applications.
The LTC4009 can be soft-started with the compensation
capacitor on the ITH pin. At start-up, ITH will quickly rise
to about 0.25V, then ramp up at a rate set by the compensation capacitor and the 40µA ITH bias current. The
full programmed charge current will be reached when ITH
reaches approximately 2V. With a 0.1µF capacitor, the time
to reach full charge current is usually greater than 1.5ms.
This capacitor can be increased if longer start-up times
are required, but loop bandwidth and dynamic response
will be reduced.
INTVDD Regulator Output
Bypass the INTVDD regulator output to GND with a low
ESR X5R or X7R ceramic capacitor with a value of 0.47µF
or larger. The capacitor used to build the BOOST supply
(C2 in Figure 11) can serve as this bypass. Do not draw
more than 30mA from this regulator for the host system,
governed by IC power dissipation.
Calculating IC Power Dissipation
The user should ensure that the maximum rated junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC4009 package (θJA) is
37°C/W, provided the Exposed Pad is in good thermal
contact with the PCB. The actual thermal resistance in
the application will depend on forced air cooling and other
heat sinking means, especially the amount of copper on
the PCB to which the LTC4009 is attached. The following
formula may be used to estimate the maximum average
power dissipation PD (in watts) of the LTC4009, which is
dependent upon the gate charge of the external MOSFETs.
This gate charge, which is a function of both gate and drain
voltage swings, is determined from specifications or graphs
in the manufacturer’s data sheet. For the equation below,
find the gate charge for each transistor assuming 5V gate
swing and a drain voltage swing equal to the maximum
VCLP voltage. Maximum LTC4009 power dissipation under
normal operating conditions is then given by:
PD = DCIN(2.8mA + IDD + 665kHz(QTGATE + QBGATE))
– 5IDD
where:
IDD = Average external INTVDD load current, if any
QTGATE = Gate charge of external top FET in Coulombs
QBGATE = Gate charge of external bottom FET in
Coulombs
4009fd
23
LTC4009
LTC4009-1/LTC4009-2
Applications Information
PCB Layout Considerations
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4009 is essential. Refer
to Figure 12. For maximum efficiency, the switch node
rise and fall times should be minimized. The following
PCB design priority list will help insure proper topology.
Layout the PCB using this specific order.
1. Input capacitors should be placed as close as possible
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
2. Place the LTC4009 close to the switching FET gate
terminals, keeping the connecting traces short to
produce clean drive signals. This rule also applies to IC
supply and ground pins that connect to the switching
FET source pins. The IC can be placed on the opposite
side of the PCB from the switching FETs.
3. Place the inductor input as close as possible to the
switching FETs. Minimize the surface area of the switch
node. Make the trace width the minimum needed to
support the programmed charge current. Use no copper fills or pours. Avoid running the connection on
multiple copper layers in parallel. Minimize capacitance
from the switch node to any other trace or plane.
4. Place the charge current sense resistor immediately
adjacent to the inductor output, and orient it such
that current sense traces to the LTC4009 are not long.
These feedback traces need to be run together as a
single pair with the smallest spacing possible on any
given layer on which they are routed. Locate any filter
component on these traces next to the LTC4009, and
not at the sense resistor location.
5. Place output capacitors adjacent to the sense resistor
output and ground.
6. Output capacitor ground connections must feed into
the same copper that connects to the input capacitor
ground before connecting back to system ground.
7. Connection of switching ground to system ground,
or any internal ground plane, should be single-point.
If the system has an internal system ground plane,
a good way to do this is to cluster vias into a single
star point to make the connection.
8. Route analog ground as a trace tied back to the LTC4009
GND paddle before connecting to any other ground.
Avoid using the system ground plane. A useful CAD
technique is to make analog ground a separate ground
net and use a 0Ω resistor to connect analog ground
to system ground.
9. A good rule of thumb for via count in a given high
current path is to use 0.5A per via. Be consistent when
applying this rule.
SWITCH NODE
L1
VIN
CIN
HIGH
FREQUENCY
CIRCULATING
PATH
RSENSE
VBAT
COUT
D1
+
BAT
ANALOG
GROUND
GND
SWITCHING GROUND
4009 F12
SYSTEM
GROUND
Figure 12. High Speed Switching Path
4009fd
24
LTC4009
LTC4009-1/LTC4009-2
Applications Information
10. If possible, place all the parts listed above on the same
PCB layer.
11. Copper fills or pours are good for all power connections
except as noted above in Rule 3. Copper planes on
multiple layers can also be used in parallel. This helps
with thermal management and lowers trace inductance,
which further improves EMI performance.
12. For best current programming accuracy, provide a
Kelvin connection from RSENSE to CSP and CSN. See
Figure 13 for an example.
13. It is important to minimize parasitic capacitance on
the CSP and CSN pins. The traces connecting these
pins to their respective resistors should be as short
as possible.
DIRECTION OF CHARGING CURRENT
RSENSE
4009 F13
TO CSP
RIN
TO CSN
RIN
Figure 13. Kelvin Sensing of Charge Current
4009fd
25
LTC4009
LTC4009-1/LTC4009-2
Package Description
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.00 REF
2.45 ± 0.05
2.45 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
0.75 ± 0.05
R = 0.05
TYP
R = 0.115
TYP
19 20
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
4.00 ± 0.10
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
1
2.00 REF
2.45 ± 0.10
2
2.45 ± 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4009fd
26
LTC4009
LTC4009-1/LTC4009-2
Revision History
(Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
3/10
I-Grade Parts Added. Reflected Throughout the Data Sheet
1 to 28
4009fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC4009
LTC4009-1/LTC4009-2
Typical Application
12.6V 2 Amp Charger
FROM
ADAPTER
15V AT 2A
C1
0.1µF
R
8
3
R2
22.1k
5
R3
2.43k
TO/FROM
MCU
6
C2
0.1µF
R4
6.04k
13
C3
4.7nF
R5
26.7k
CHRG
CLP
DCIN
CLN
DCDIV
BOOST
2
C4
0.1µF
SHDN
GND
ITH
CSP
CSN
20 R15 0Ω*
C5
0.1µF
D3
D5
C6
2µF
R9 3.01k
14
R10 3.01k
10
R6
53.6k
R12
294k
Q2
C10
10pF
L1
10µH
R14
100k
D6
18V
ZENER
Q4
TO POWER SYSTEM LOAD
WHEN ADAPTER IS NOT
PRESENT, USE
SCHOTTKY DIODE D5 OR
THE COMBINATION OF R14,
D6 AND Q4
R11
50mΩ
C9
10µF
+
12.6V
Li-Ion
BATTERY
4009 TA02
R13
31.2k
OR
PFET
FDR858P
Q3
15
PROG
C8
10µF
D4
21
11
BAT
9
FBDIV
VFB
R8
5.1k
1
19
TGATE
LTC4009
18
SW
7
17
ACP
INTVDD
4
16
ICL
BGATE
12
Q1
POWER TO SYSTEM
R1
3k
D1
BULK
CHARGE
R7
50mΩ
D2
D2, D4: MBR230LSFT1
D3:CMDSH-3
Q1: 2N7002
Q2, Q3: Si7212DN OR SiA914DJ
OR Si4816BDY (OMIT D4)
L1: IHLP-2525CZER100M11
*SEE TGATE BOOST SUPPLY
IN APPLICATIONS INFORMATION
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC4006
Small, High Efficiency, Fixed Voltage, Lithium-Ion
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Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current
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Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current
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High Efficiency, Programmable Voltage/Current Battery
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Voltage/Current Programming, Thermistor Sensor and Indicator
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LTC4012/LTC4012-1
LTC4012-2
High Efficiency, Multichemistry Battery Chargers with
PowerPath Control
Constant-Current/Constant-Voltage Switching Regulator in a 20-Lead
QFN Package, AC Adapter Current Limit, PFET Input Ideal Diode Control,
Indicator Outputs
LTC4411
2.6A Low Loss Ideal Diode
No External MOSFET, Automatic Switching Between DC Sources, 140mΩ
On-Resistance in ThinSOTTM package
LTC4412/LTC4412HV
Low Loss PowerPath Controllers
Very Low Loss Replacement for Power Supply ORing Diodes Using
Minimal External Complements, Operates Up to 28V (36V for HV)
LTC4413
Dual 2.6A, 2.5V to 5.5V Ideal Diodes
Low Loss Replacement for ORing Diodes, 100mΩ On-Resistance
LTC4414
36V, Low Loss PowerPath Controller for Large PFETs
Low Loss Replacement for ORing Diodes, Operates Up to 36V
LTC4416
Dual Low Loss PowerPath Controllers
Low Loss Replacement for ORing Diodes, Operates Up to 36V, Drives
Large PFETs, Programmable, Autonomous Switching
4009fd
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LT 0610 REV D • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2008