Microsemi LX1673-06CLQ High frequency pwm regulator Datasheet

LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
KEY FEATURES
DESCRIPTION
With onboard gate drivers, the switching
PWM output is capable of sourcing up to
15A. The LX1673 also features an
additional Linear Regulator Controller
output, which when coupled with an
inexpensive MOSFET is capable of
supplying up to an additional 5A for I/O,
memory, and other supplies surrounding
today’s microprocessor designs.
Each regulator output voltage is
programmed via a simple voltage-divider
network.
Integrated hiccup mode current limiting
is implemented utilizing MOSFET RDS(ON)
impedance. This enables the LX1673 to
monitor maximum current limit conditions
without the use of expensive current sense
resistors.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
ƒ Two Independently Regulated
Outputs
ƒ Outputs As Low As 0.8V
Generated From An Internal 1%
Reference
ƒ Integrated High Current MOSFET
Drivers
ƒ 300KHz, 600KHz, and 900KHz
High Frequency Operation
Minimizes External Component
Requirements
ƒ Soft-Start and Power Sequencing
Control
ƒ Adjustable Linear Regulator Driver
Output
ƒ No current-sense resistors
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The LX1673 is a highly integrated
power supply controller IC featuring one
PWM switching regulator stage with an
additional onboard linear regulator
driver.
With several switching frequencies
available (up to 900kHz) the LX1673
can be optimized for both cost and PCB
space.
Utilizing external compensation, a wide selection of external
components can be chosen for use in
any application while maintaining
stable operation.
The LX1673 incorporates a fully
programmable soft-start and power
sequence capabilities. The LDO and
PWM have independent enable pins.
APPLICATIONS/BENEFITS
ƒ
ƒ
ƒ
ƒ
ƒ
Video Card Power Supplies
PC Peripherals
Computer Add-On Cards
3.3V Power Conversion
DDR Memory Termination
PRODUCT HIGHLIGHT
+3.3V
+5V
PWRGD
VOUT1
+12V
+3.3V
20
19
18
17
+5V
16
LDVCC PWGD VC1 TDRV PGND
1
15
LDGD
BDRV
LDFB
VCCL
2
VOUT2
14
3
LX1673
LDDIS
VCC
4
13
12
DGND
5
AGND
CS
DIS
6
+5V
VS
SS
7
EA+
8
EA9
11
EAO
10
LDDIS
DIS
-40 to 85
-40 to 85
-40 to 85
300
600
900
LQ
LX1673
TA (°C)
PACKAGE ORDER INFO
Plastic TSSOP
Switching
PW
20-Pin
Frequency (kHz)
Plastic MLPQ
20-Pin
RoHS Compliant / Pb-free
RoHS Compliant / Pb-free
LX1673-03CPW
LX1673-06CPW
LX1673-09CPW
LX1673-03CLQ
LX1673-06CLQ
LX1673-09CLQ
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1673-03CPW-TR)
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
The limitation on transient time is thermal and is due to zener diodes on the supply
pins, application of maximum voltages will increase current into that pin and
increase package power dissipation.
THERMAL DATA
PW Plastic TSSOP 20-Pin
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
PGND
TDRV
VC1
LDGD 1
BDRV
LDFB
VCCL
LDDIS
VCC
DGND
VS
AGND
11 CS
EAO
EA-
EA+
SS
6
LQ PACKAGE
Package Peak Temp. for Solder Reflow (40 Seconds Maximum Exposure).. 260°C(+0, -5)
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
PWGD
16
DIS
Supply Voltage (VCC) DC ................................................................-0.3V to 5.5V
Supply Voltage (VCC) Transient .........................................................-0.3V to 6V
Driver Supply Voltage (VCCL) DC .....................................................-0.3V to 13V
Driver Supply Voltage (VCCL) Transient............................................-0.3V to 16V
Driver Supply Voltage (VC1) DC .......................................................-0.3V to 19V
Input Voltage (SS/DIS) .....................................................................-0.3V to 5.5V
Output Drive Peak Current Source (HO, LO).......................................1A (500ns)
Output Drive Peak Current Sink (HO, LO) ..........................................1A (500ns)
Operating Temperature Range .........................................................-40°C to 85°C
Maximum Operating Junction Temperature ................................................ 150°C
Storage Temperature Range...........................................................-65°C to 150°C
Lead Temperature (Soldering 180 seconds) ................................................ 235°C
LDVCC
PACKAGE PIN OUT
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ABSOLUTE MAXIMUM RATINGS
(Top View)
N.C. – No Internal Connection
N/U – Not Used
RSVD – Do Not Use
VC1
PGOOD
LDOVCC
LDGD
LDFB
LDDIS
DGND
AGND
DIS
SS
90°C/W
1
20
10
11
TDRV
PGND
BDRV
VCCL
VCC
VS
CS
EAO
EAEA+
PW PACKAGE
(Top View)
LQ
Pb-free 100% Matte Tin Lead Finish
Plastic MLPQ 20-Pin
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
35°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJC).
The θJA numbers are guidelines for the thermal performance of the device/pc-board system.
All of the above assume no airflow.
PACKAGE DATA
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
NAME
DESCRIPTION
EA-
Voltage Feedback – Output voltage is connected through a resistor network to this pin for feedback to set the
desired output voltage of the switching PWM output.
EAO
Error Amplifier Output – Sets error amplifier gain and external compensation if used.
EA+
Voltage Reference – Connect to the SS pin or any other external voltage. Used in conjunction with EA-, and an
external resistor divider, to set the desired output voltage for the PWM output.
VCC
IC supply voltage (nominal 5V).
VCCL
Power supply pin for Low side drivers.
LDFB
Low Dropout Regulator Voltage Feedback – Sets output voltage of external MOSFET via resistor network.
CS
Over-Current Limit Set – Connecting a resistor between CS pin and the source of the high-side MOSFET sets the
current-limit threshold for the PWM output. A minimum of 1KΩ must be in series with this pin.
SS
PWM Soft-start/Hiccup Capacitor Pin – During start-up, the voltage on this pin controls the output voltage of the
switching regulator. An internal 20KΩ resistor and the external capacitor set the time constant for soft-start
function. The Soft-start function does not initialize until the supply voltage on VCC exceeds the UVLO threshold.
When an over-current condition occurs, this capacitor is used for the timing of hiccup mode protection.
AGND
Analog ground reference.
DGND
Digital ground reference.
LDGD
Low Dropout Regulator Gate Drive – Connect to gate of external N-Channel MOSFET for linear regulator
function.
PGND
MOSFET Driver Power Ground. Connects to the source of the bottom N-channel MOSFETS of the switching
regulator.
TDRV
High Side MOSFET Gate Driver
BDRV
Low Side MOSFET Gate Driver
VC1
LDDIS
High-Side MOSFET Gate Driver Supply – Connect to separate supply or boot strap supply to ensure proper highside gate driver supply voltage.
LDO Disable Input – High disables LDO output. This pin has a 100KΩ pull down resistor.
Voltage reference for Short Circuit Current sense. This pin is also the supply pin for the Current Sense
Comparator. This pin cannot be left floating, if current limit is not used connect to VCC.
PWGD
Power Good Output – Open drain output, goes high at end of Soft Start and no Fault. Pulls low if any Fault
condition occurs.
LDVCC
LDO VCC Supply – Connect to voltage supply greater than supply rail for LDO MOSFET drain.
DIS
Copyright © 2004
Rev 1.0, 3/18/2005
PACKAGE DATA
VS
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FUNCTIONAL PIN DESCRIPTION
PWM Disable Input –High disables the PWM output. This pin has a 80KΩ pull down resistor.
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
Parameter
`
Test Conditions
Min
VCC
4.5
ICC
LDO Operating Current
V
16
Static and Dynamic
6
ILDVCC
mA
1
mA
0.792
0°C ≤ TA ≤ 70°C
0.784
0.816
V
Line Regulation Note 1
-1
1
%
Load Regulation Note 1
-1
1
VSS
0.8V
0.808
V
Dead Time
3000pF Load 2 Volt Level
160
nS
Minimum Pulse Width
All Frequencies
150
nS
Maximum Duty Cycle
LX1673-03 Load = 3000pF
85
%
Maximum Duty Cycle
LX1673-06 Load = 3000pF
75
%
Maximum Duty Cycle
LX1673-09 Load = 3000pF
70
%
ERROR AMPLIFIERS
Input Offset Voltage
VOS
Common Mode Voltage = 1V
-6.0
DC Open Loop Gain
Unity Gain Bandwidth
UGBW
High Output Voltage
VOH
I Source = 2mA
Low Output Voltage
VOL
I Sink = 10uA
Input Common Mode Voltage Range
Input Offset Voltage < 20mV
Input Bias Current
0 and 3.5 V Common Mode Voltage
3.8
6.0
mV
70
dB
16
MHz
5.0
V
100
0.1
3.5
100
mV
V
nA
CURRENT SENSE
Current Sense Bias Current
Trip Threshold
ISET
VTRIP
VCS = VVS – 0.3V , VVS = 5V
45
50
55
µA
Referenced to VS , VVS = 5V
260
300
340
mV
5
mA
Current Sense Delay
TCSD
Current Sense Comparator
ICS
Operating Current
OUTPUT DRIVERS – N-CHANNEL MOSFETS
Current into VS pin
350
Low Side Driver Operating Current
IVCCL
Static
High Side Driver Operating Current
IVC1
Drive Rise Time, Fall Time
TRF
High Level Voltage
VDH
ISOURCE = 20mA, VCCL = 12V
Low Level Voltage
VDL
ISINK = 20mA, VCCL = 12V
2
nS
2.5
mA
Static
3
mA
CL = 3000pF
50
nS
10
11
0.15
V
0.25
V
OSCILLATOR
PWM Switching Frequency
Ramp Amplitude
Copyright © 2004
Rev 1.0, 3/18/2005
FSW
LX1673-03
255
300
345
LX1673-06
510
600
690
LX1673-09
765
900
1035
VRAMP
1.25
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
KHz
VPP
Page 4
ELECTRICALS
`
Units
TA=25°C
Reference Voltage
`
Max
5.5
VCCL,VC1
Operation Current
`
LX1673
Typ
SWITCHING REGULATORS
Input Voltage
`
Symbol
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where
otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VC1=12V, LDVCC = 12V, TDRV = BDRV = 3000pF Load.
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
Parameter
`
Symbol
Test Condition
Min
LX1673
Typ
4.0
4.25
4.0
Start-Up Threshold (VCC)
Hysteresis VCC
SS Input Resistance
SS Shutdown Threshold
V
4.5
V
0.1
V
RSS
20
KΩ
VSHDN
0.1
V
10
%
Hiccup Mode Duty Cycle
CSS = 0.1µF
LINEAR REGULATOR CONTROLLER
Voltage Reference Tolerance
`
Units
UVLO AND SOFT-START (SS)
Start-Up Threshold (VC1, VCCL, LDVCC)
`
Max
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ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where
otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VC1=12V, LDVCC = 12V, TDRV = BDRV = 3000pF Load.
VLDFB = .8V, COUT = 330µF
Source Current
IHDRV
VOUT = 10V
Sink Current
ILDRV
VOUT = 0.4V
2
30
%
mA
0.2
mA
1
V
KΩ
DISABLE INPUTS
PWM Disable
DIS
LDO Disable
LDDIS
Threshold
Internal Pull down Resistance
80
Threshold
2.5
V
Internal Pull down Resistance
100
KΩ
POWER GOOD
Drain to Source Voltage
I = 3mA
Leakage
Note 1:
Note 2:
Note 3:
0.4
V
0.05
µA
System Specification
Low duty cycle pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature
Functionality over the –40 to 85 deg C operating temperature range is assured by design, characterization, and statistical process
control
ELECTRICALS
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
RSET
ISET
CS
Vin (5V)
CS Comp
IRESET
VS
VTRIP
PWM
+
R
Q
ISET
S
Q
EAO
VC1
CIN
TDRV
L1
V out 1
ESR
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BLOCK DIAGRAM
COUT
BDRV
PGND
+5V
Comp
+
EA-
VCCL
Hiccup
-
+ Amplifier/
Compensation
VREF
+5V
20k
UVLO
Ramp
Oscillator
EA+
UVLO
VCC
S
F
LDVCC
FAULT S
R
S
5.5V
TEMP
SS1
SS
DIS
PWGD
CSS
Figure 1 – Block Diagram of PWM Phase
+12V
+V
LDGD
BLOCK DIAGRAM
LDVCC
VREF
16V
+
VOUT 2
LDFB
-
+5V
LDDIS
Figure 2 – LDO Controller Block Diagram
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
WWW . Microsemi .C OM
APPLICATION SCHEMATIC
+5
+5
PWM
Vout
PWRGD
+12
+3.3
20
19
18
17
+5
16
LDVCC PWGD VC1 TDRV PGND
1
LDO
Vout
15
LDGD
BDRV
LDFB
VCCL
2
3
LX1673
LDDIS
VCC
4
+5
13
12
DGND
VS
5
AGND
CS
DIS
6
LDDIS
14
SS
7
EA+
8
EA9
11
EAO
10
DIS
Figure 3 – Schematic with Bootstrap Supply for PWM High Side Drive
+5
+5
PWM
Vout
PWRGD
PWM
Vout
20
19
18
17
+5
16
LDVCC PWGD VC1 TDRV PGND
1
LDO
Vout
15
LDGD
BDRV
LDFB
VCCL
2
3
LX1673
LDDIS
VCC
4
+5
13
12
VS
AGND
CS
DIS
6
SS
7
EA+
8
EA9
11
APPLICATIONS
DGND
5
LDDIS
14
EAO
10
DIS
Figure 4 – Schematic for 5 Volt only Input
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
GENERAL DESCRIPTION
The LX1673 is a voltage-mode pulse-width modulation
controller integrated circuit. The internal oscillator and ramp
generator frequency is fixed to 300KHz, 600KHz, or 900KHz.
The device has external compensation, for more flexibility of
output current magnitude.
UNDER VOLTAGE LOCKOUT (UVLO)
At power up, the LX1673 monitors the supply voltage for
VCC, VCCL, LDVCC and VC1 (there is no requirement for
sequencing the supplies). Before all supplies reach their undervoltage lock-out (UVLO) thresholds, the soft-start (SS) pin is
held low to prevent soft-start from beginning, the oscillator is
disabled and all MOSFETs are held off. There is an internal
delay that will filter out transients less that 1.5µSec.
SOFT-START
Once the supplies are above the UVLO threshold, the soft-start
capacitor begins to be charged by the reference through a 20kΩ
internal resistor. The capacitor voltage at the SS pin rises as a
simple RC circuit. The SS pin is connected to the error
amplifier’s non-inverting input that controls the output voltage.
The output voltage will follow the SS pin voltage if sufficient
charging current is provided to the output capacitor.
The simple RC soft-start allows the output to rise faster at the
beginning and slower at the end of the soft-start interval. Thus,
the required charging current into the output capacitor is less at
the end of the soft-start interval. A comparator monitors the SS
pin voltage and indicates the end of soft-start when SS pin
voltage reaches 95% of VREF.
When the sensed voltage across RDS(ON) plus the set resistor
exceeds the 300mV, VTRIP threshold, the OCP comparator outputs
a signal to reset the PWM latch and to start hiccup mode. The
soft-start capacitor (CSS) is discharged slowly (10 times slower
than when being charged up by RSS). When the voltage on the SS
pin reaches a 0.1V threshold, hiccup finishes and the circuit softstarts again. During hiccup both MOSFETs are held off.
Hiccup is disabled during the soft-start interval, allowing the
circuit to start up with maximum current. If the rate of rise of the
output voltage is too fast, the required charging current to the
output capacitor may be higher than the limit-current. In this case,
the peak MOSFET current is regulated to the limit-current by the
current-sense comparator. If the MOSFET current still reaches its
limit after the soft-start finishes, the hiccup is triggered again.
When the output has a short circuit the hiccup circuit ensures that
the average heat generation in both MOSFETs and the average
current is much less than in normal operation,.
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THEORY OF OPERATION
Over-current protection can also be implemented using a sense
resistor, instead of using the RDS(ON) of the upper MOSFET, for
greater set-point accuracy.
OSCILLATOR FREQUENCY
An internal oscillator sets the switching frequency at 300kHz,
600kHz, or 900kHz.
OVER-CURRENT PROTECTION (OCP) AND HICCUP
The LX1673 uses the RDS(ON) of the upper MOSFET, together
with a resistor (RSET) to set the actual current limit point. The
current sense comparator senses the MOSFET current 350nS
after the top MOSFET is switched on in order to reduce
inaccuracies due to ringing. A current source supplies a current
(ISET), whose magnitude is 50µA. The set resistor RSET is
selected to set the current limit for the application. RSET and VS
should be connected directly at the upper MOSFET drain and
source to get an accurate measurement across the low resistance
RDS(ON).
APPLICATIONS
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 8
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
OUTPUT INDUCTOR
The output inductor should be selected to meet the
requirements of the output voltage ripple in steady-state operation
and the inductor current slew-rate during transient. The peak-topeak output voltage ripple is:
(
)
ESR × I RIPPLE + ∆I < VEX
VRIPPLE = ESR × I RIPPLE
Where IRIPPLE is the inductor ripple current, ∆I is the maximum
load current step change, and VEX is the allowed output voltage
excursion in the transient.
VIN − VOUT
Electrolytic capacitors can be used for the output capacitor, but
are less stable with age than tantalum capacitors. As they age, their
ESR degrades, reducing the system performance and increasing the
risk of failure. It is recommended that multiple parallel capacitors
be used, so that, as ESR increase with age, overall performance
will still meet the processor’s requirements.
where
∆I =
L
×
D
fs
∆I is the inductor ripple current, L is the output inductor value
and ESR is the Effective Series Resistance of the output
capacitor.
∆I should typically be in the range of 20% to 40% of the
maximum output current. Higher inductance results in lower
output voltage ripple, allowing slightly higher ESR to satisfy the
transient specification. Higher inductance also slows the inductor
current slew rate in response to the load-current step change, ∆I,
resulting in more output-capacitor voltage droop. When using
electrolytic capacitors, the capacitor voltage droop is usually
negligible, due to the large capacitance
The inductor-current rise and fall times are:
TRISE = L×
∆I
(V
IN
− VOUT
)
and
There is frequently strong pressure to use the least expensive
components possible; however, this could lead to degraded longterm reliability, especially in the case of filter capacitors.
Microsemi’s demonstration boards use the CDE Polymer AL-EL
(ESRE) filter capacitors, which are aluminum electrolytic, and
have demonstrated reliability. The OS-CON series from Sanyo
generally provides the very best performance in terms of long term
ESR stability and general reliability, but at a substantial cost
penalty. The CDE Polymer AL-EL (ESRE) filter series provides
excellent ESR performance at a reasonable cost. Beware of offbrand, very low-cost filter capacitors, which have been shown to
degrade in both ESR and general electrolytic characteristics over
time.
INPUT CAPACITOR
TFALL = L×
The input capacitor and the input inductor, if used, are to filter
the pulsating current generated by the buck converter to reduce
interference to other circuits connected to the same 5V rail. In
addition, the input capacitor provides local de-coupling for the
buck converter. The capacitor should be rated to handle the RMS
current requirements. The RMS current is:
∆I
VOUT
.
The inductance value can be calculated by
L=
VIN − VOUT
∆I
×
I RMS = I L d(1 − d)
fs
Where IL is the inductor current and d is the duty cycle. The
maximum value occurs when d = 50%, then IRMS =0.5IL. For a 5V
input and output voltages in the range of 2 to 3V, the required RMS
current is very close to 0.5IL.
The output capacitor is sized to meet ripple and transient
performance specifications. Effective Series Resistance (ESR) is
a critical parameter. When a step load current occurs, the output
voltage will have a step that equals the product of the ESR and
the current step, ∆I. In an advanced microprocessor power
SOFT-START CAPACITOR
The value of the soft-start capacitor determines how fast the
output voltage rises and how large the inductor current is required
to charge the output capacitor. The output voltage will follow the
voltage at the SS pin if the required inductor current does not
exceed the maximum allowable current for the inductor.
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Page 9
APPLICATIONS
D
OUTPUT CAPACITOR
Copyright © 2004
Rev 1.0, 3/18/2005
supply, the output capacitor is usually selected for ESR instead of
capacitance or RMS current capability. A capacitor that satisfies
the ESR requirements usually has a larger capacitance and current
capability than strictly needed. The allowed ESR can be found by:
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APPLICATION NOTE
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
The SS pin voltage can be expressed as:
(
VSS = V ref 1 − e
− t/R SSCSS
)
Where RSS and CSS are the soft-start resistor and capacitor.
The current required to charge the output capacitor during the soft
start interval is.
dVss
Iout = Cout
dt
VrefCout − t/R SS C SS
e
RssCss
OUTPUT DISABLE
The LX1673 PWM MOSFET driver outputs are shut off by
pulling the disable (DIS) pin above 1.2V. There is a 80KΩ pull
down resistor on this input.
and at t=0
Im ax =
VrefCout
RssCss
The required inductor current for the output capacitor to follow
the soft start voltage equals the required capacitor current plus the
load current. The soft-start capacitor should be selected to
provide the desired power on sequencing and insure that the
overall inductor current does not exceed its maximum allowable
rating.
Values of CSS equal to 0.1µf or greater are unlikely to result in
saturation of the output inductor unless very large output
capacitors are used.
OVER-CURRENT PROTECTION
Current limiting occurs at current level ICL when the voltage
detected by the current sense comparator is greater than the
current sense comparator threshold, VTRIP (300mV).
I CL × R DS(ON) + I SET × R SET = VTRIP
So,
R SET =
VTRIP − I CL × R DS(ON)
I SET
=
300 mV − I CL × R DS(ON)
50 µA
0.3 − 10 × 0.010
50 × 10− 6
= 4K Ω
Note: Maximum RSET is 6KΩ . Any resistor 6KΩ or greater will
not allow startup since ICL will equal zero (50µA x 6KΩ =
300mV).
At higher PWM frequencies or low duty cycles where the upper
gate drive is less than 350nS wide the 350nS delay for current
limit enable may result in current pulses exceeding the desired
Copyright © 2004
Rev 1.0, 3/18/2005
The LDO voltage regulator has its own Disable pin (LDDIS) for
control of this output voltage. Pulling this pin above 3 V disables
the LDO. There is a 100KΩ pull down resistor on this input.
PROGRAMMING THE OUTPUT VOLTAGE
The output Voltage is sensed by the feedback pin (FBX) which is
compared to a 0.8V reference. The output voltage can be set to any
voltage above 0.8V (and lower than the input voltage) by means of
a resistor divider (see Figure 1).
VOUT = VREF (1 + R 1 /R 2 )
Note: This equation is simplified and does not account for error
amplifier input current. Keep R1 and R2 close to 1KΩ (order of
magnitude).
DDR VTT TERMINATION VOLTAGE
Double Data Rate (DDR) SDRAM requires a termination
voltage (VTT) in addition to the line driver supply voltage (VDDQ)
and receiver supply voltage (VDD).
VTT for DDR memory can be generated with the LX1673 by
using the positive input of the phase 2 error amplifier RF2 as a
reference input from an external reference voltage VREF which is
defined as one half of VDDQ. Using VREF as the reference input
will insure that all voltages are correct and track each other as
specified in the JEDEC (EIA/JESD8-9A) specification. The phase 2
output will then be equal to VREF and track the VDDQ supply as
required.
When an external reference is used the connection between the
error amplifier positive input and the Soft Start pin is lost and Soft
Start will not function. It is recommended that the external
reference voltage have an R-C time constant that will be long
enough to allow the output capacitor to charge slowly.
See Microsemi Application Note 17 for more details
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
APPLICATIONS
Example:
For 10A current limit, using FDS6670A MOSFET ( 10m Ω
RDS(ON)):
R SET =
Short circuit protection still exists due to the narrow pulse width
even though the magnitude of the current pulses will be higher than
the calculated value.
If OCP is not desired connect both VSX and VCX to VCC. Do not
leave them floating.
Taking the derivative with respect to time results in
Iout =
current limit set point. If the upper MOSFET on time is less than
350nS and a short circuit condition occurs the duty cycle will
increase, since VOUT will be forced low. The current limit circuit
will be enabled when the upper gate drive exceeds 350nS although
the actual peak current limit value will be higher than calculated
with the above equation.
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APPLICATION NOTE (CONTINUED)
LX1673
TM
®
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
1. The minimum RSET resistor value is 1k ohm for the current
limit sensing. If this resistor becomes shorted, it will do
permanent damage to the IC.
4.
. If current limit is not used connect the VS and VC pins
together and to VCC. Do not leave them floating. A floating VS
pin will result in operation resembling a hiccup condition.
2. A resistor has been put in series with the gate of the LDO
pass transistor to reduce the output noise level. The resistor
value can be changed to optimize the output transient
response versus output noise.
3. To delay the turn on of the LDO controller output, a
capacitor should be connected between the LDDIS pin and
the +5volts. The LDDIS input has a 100K pull down
resistor, which keeps the LDO active until this pin is pulled
high. During the power up sequence the capacitor connected
to the LDDIS pin will keep the LDO off until this capacitor,
being charge by the 100K pull down resistor, goes through
the low input threshold level.
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APPLICATION NOTE CONSIDERATIONS
APPLICATIONS
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 11
LX1673
®
TM
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
LQ
20-Pin Micro Leadframe Package (MLPQ) Package
D
Dim
b
A
A1
A3
b
D
D2
E
E2
e
L
L
D2
E
E2
e
A1
A
MILLIMETERS
MIN
MAX
0.80
1.00
0
0.05
0.25 REF
0.23
0.38
5.00 BSC
1.25
3.25
5.00 BSC
1.25
3.25
0.65 BSC
0.35
0.75
INCHES
MIN
MAX
0.031
0.039
0
0.002
0.010
0.009
0.015
0.197
0.050
0.128
0.197
0.050
0.128
0.026
0.014
0.030
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PACKAGE DIMENSIONS
A3
Note:
Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(0.006”) on any side. Lead dimension shall
not include solder coverage.
PW
20-Pin Thin Small Shrink Outline (TSSOP)
Dim
3 2 1
E
E1
e
1
A2 A
SEATING PLANE
b
A1
L
c
INCHES
MIN
MAX
0.043
0.002
0.006
0.031
0.041
0.007
0.012
0.004
0.008
0.252
0.260
0.246
0.258
0.169
0.177
0.026 BSC
0.018
0.030
0°
8°
0.004
solder coverage.
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 12
MECHANICALS
D
A
A1
A2
b
c
D
E
E1
e
L
Θ1
*LC
MILLIMETERS
MIN
MAX
1.10
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40
6.60
6.25
6.55
4.30
4.50
0.65 BSC
0.45
0.75
0°
8°
0.10
LX1673
TM
®
High Frequency PWM Regulator
P RODUCTION D ATA S HEET
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NOTES
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
Copyright © 2004
Rev 1.0, 3/18/2005
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 13
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