NSC DS3893AV Btl turbotransceiverâ ¢ Datasheet

DS3893A
BTL TURBOTRANSCEIVER™
General Description
The TURBOTRANSCEIVER is designed for use in very high
speed bus systems. The bus terminal characteristics of the
TURBOTRANSCEIVER are referred to as “Backplane
Transceiver Logic” (BTL). BTL is a new logic signaling standard that has been developed to enhance the performance
of backplane buses. BTL compatible transceivers feature
low output capacitance drivers to minimize bus loading, a 1V
nominal signal swing for reduced power consumption and
receivers with precision thresholds for maximum noise immunity. This new standard eliminates the settling time delays, that severely limit the TTL bus performance, to provide
significantly higher bus transfer rates.
The TURBOTRANSCEIVER is compatible with the requirements of the proposed IEEE 896 Futurebus draft standard. It
is similar to the DS3896/97 BTL TRAPEZOIDAL™ Transceivers but the trapezoidal feature has been removed to
improve the propagation delay. A stripline backplane is therefore required to reduce the crosstalk induced by the faster
rise and fall times. This device can drive a 10Ω load with a
typical propagation delay of 3.5 ns for the driver and 5 ns for
the receiver.
When multiple devices are used to drive a parallel bus, the
driver enables can be tied together and used as a common
control line to get on and off the bus. The driver enable delay
is designed to be the same as the driver propagation delay in
order to provide maximum speed in this configuration. The
low input current on the enable pin eases the drive required
for the common control line.
The bus driver is an open collector NPN with a Schottky
diode in series to isolate the transistor output capacitance
from the bus when the driver is in the inactive state. The
active output low voltage is typically 1V. The bus is intended
to be operated with termination resistors (selected to match
the bus impedance) to 2.1V at both ends. Each of the
resistors can be as low as 20Ω.
Features
n Fast single ended transceiver (typical driver enable and
receiver propagation delays are 3.5 ns and 5 ns)
n Backplane Transceiver Logic (BTL) levels (1V logic
swing)
n Less than 5 pF bus-port capacitance
n Drives densely loaded backplanes with equivalent load
impedances down to 10Ω
n 4 transceivers in 20 pin PCC package
n Specially designed for stripline backplanes
n Separate bus ground returns for each driver to minimize
ground noise
n High impedance, MOS and TTL compatible inputs
n TRI-STATE™ control for receiver outputs
n Built-in bandgap reference provides accurate receiver
threshold
n Glitch free power up/down protection on all outputs
n Oxide isolated bipolar technology
Connection and Logic Diagram
00869801
Order Number DS3893AV
See NS Package Number V20A
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
TRAPEZOIDAL™ and TURBOTRANSCEIVER™ are trademarks of National Semiconductor Corp.
© 2004 National Semiconductor Corporation
DS008698
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DS3893A BTL TURBOTRANSCEIVER
March 1997
DS3893A
Absolute Maximum Ratings (Note 1)
Lead Temperature (Soldering, 3
sec.)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Recommended Operating
Conditions
6.5V
Control Input Voltage
5.5V
Driver Input and Receiver Output
5.5V
Min
Max
Supply Voltage, VCC
4.5
5.5
V
2.0
2.2
V
0
70
˚C
Driver Output Receiver Input Clamp
Current
± 15 mA
Bus Termination Voltage (VT)
Power Dissipation at 70˚C
900 mW
Operating Free Air Temperature
Storage Temperature Range
260˚C
Units
−65˚C to +150˚C
Electrical Characteristics (Notes 2, 3, 4)
TA = 0 to +70˚C, VCC = 5V ± 10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AND CONTROL INPUT: (DE, RE , Dn)
VIH
Input High Voltage
VIL
Input Low Voltage
II
Input Leakage Current
DE = RE = Dn = VCC
IIH
Input High Current
DE = RE = Dn = 2.5V
20
µA
IIL
Dn Input Low Current
Dn = 0.5V, DE = VCC = Max
−200
µA
DE Input Low Current
DE = 0.5V, Dn = VCC = Max
−500
µA
RE Input Low Current
RE = 0.5V, VCC = Max
−100
µA
Input Diode Clamp Voltage
Iclamp = −12 mA
−1.2
V
VCL
2.0
V
0.8
V
100
µA
DRIVER OUTPUT/RECEIVER INPUT: (Bn)
VOLB
Output Low Bus Voltage
Dn = DE = VIH (Figure 2)
0.75
1.0
1.2
V
0.75
1.0
1.1
V
100
µA
100
µA
2.9
V
3.2
V
RT = 10Ω, VT = 2.2V
Dn = DE = VIH (Figure 2)
RT = 18.5Ω, VT = 2.14
IILB
Output Bus Current (Power On)
Dn = DE = 0.8V, VCC = Max
−250
Bn = 0.75V
IIHB
Output Bus Current (Power Off)
Dn = DE = 0.8V, VCC = 0V
Bn = 1.2V
VOCB
Driver Output Positive Clamp
VCC = Max or 0V, Bn = 1 mA
VOHB
Output High Bus Voltage
VCC = Max, Dn = 0.8V (Figure 2)
VCC = Max or 0V, Bn = 10 mA
1.90
V
VT = 2.0V, RT = 10Ω
VTH
Receiver Input Threshold
1.47
1.55
1.62
V
0.35
0.5
V
RECEIVER OUTPUT: (Rn)
VOH
Voltage Output High
Bn = 1.2V, Ioh = −3 mA, RE = 0.8V
VOL
Voltage Output Low
Bn = 2V, Iol = 6 mA, RE = 0.8V
IOZ
TRI-STATE Leakage
Vo = 2.5V, RE = 2V
20
µA
Vo = 0.5V, RE = 2V
−20
µA
−120
−200
mA
70
95
mA
IOS
ICC
Output Short Circuit Current
Bn = 1.2V, Vo = 0V
(Note 5)
RE = 0.8V, VCC = Max
Supply Current
Dn = DE = RE = VIH, VCC = Max
2.5V
−80
V
Note 1: “Absolute maximum ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
Note 3: All typicals are given for VCC = 5V and TA = 25˚C.
Note 4: Unused inputs should not be left floating. Tie unused inputs to either VCC or GND thru a resistor.
Note 5: Only one output at a time should be shorted.
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2
TA = 0 to +70˚C, VCC = 5V ± 10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER: (Figure 3 and Figure 6)
tPHL
Driver Input to Output
VT = 2V RT = 10Ω, CL = 30 pF, DE = 3V
1
3.5
7
ns
tPLH
Driver Input to Output
VT = 2V, RT = 10Ω, CL = 30 pF, DE = 3V
1
3.5
7
ns
tr
Output Rise time
VT = 2V, RT = 10Ω, CL = 30 pF, DE = 3V
1
2
5
ns
tf
Output Fall Time
VT = 2V, RT = 10Ω, CL = 30 pF, DE = 3V
1
2
5
ns
tskew
Skew Between Drivers
(Note 6)
1
ns
in Same Package
DRIVER ENABLE: (Figure 3 and Figure 6)
tPHL
Enable Delay
VT = 2V, RT = 10Ω, CL = 30 pF, Dn = 3V
1
3.5
7
ns
tPLH
Disable Delay
VT = 2V, RT = 10Ω, CL = 30 pF, Dn = 3V
1
3.5
7
ns
CL = 50 pF, RE = DE = 0.3V, S3 Closed
2
5
8
ns
2
5
8
RECEIVER: (Figure 4 and Figure 7)
tPHL
Receiver Input to Output
tPLH
Receiver Input to Output
CL = 50 pF, RE = DE = 0.3V, S3 Open
tskew
Skew Between Receivers
(Note 6)
1
ns
ns
in Same Package
RECEIVER ENABLE: (Figure 5 and Figure 8)
tZL
tZH
tLZ
tHZ
Receiver Enable to
CL = 50 pF, RL = 500, DE = 0.3V
Output Low
S2 Open
2
6
12
ns
2
5
12
ns
1
5
8
ns
1
4
8
ns
Bn = 2V
Receiver Enable to
CL = 50 pF, RL = 500, DE = 0.3V
Output High
S1 OpenBn = 1V
Receiver Disable
CL = 50 pF, RL = 500, DE = 0.3V
From Output Low
S2 OpenBn = 2V
Receiver Disable
CL = 50 pF, RL = 500, DE = 0.3V
From Output High
S1 OpenBn = 1V
Note 6: tD and tR skew is an absolute value, defined as differences seen in propagation delays between each of the drivers or receivers in the same package of
the same delay, VCC, temperature and load conditions.
00869802
Note: n = 1, 2, 3, 4
00869812
FIGURE 1. Equivalent Bus Output
FIGURE 2. Driver Output Voltage
3
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DS3893A
Switching Characteristics
DS3893A
AC Test Circuits
00869803
FIGURE 3.
00869804
FIGURE 4.
00869805
Note:
Unless Otherwise Specified
The Switches are Closed
FIGURE 5.
Switching Time Waveforms
00869806
FIGURE 6. Driver Propagation Delay
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4
DS3893A
Switching Time Waveforms
(Continued)
00869807
FIGURE 7. Receiver Propagation Delay
00869808
Note: tR = tF ≤ 4 ns From 10% to 90%
Note: n = 1, 2, 3, 4
FIGURE 8. Receiver Enable and Disable Times
Typical Application
00869809
not carry transient switching currents. The transceivers
should be mounted as close as possible to the connector. It
should be noted that even one inch of trace can add a
significant amount of ringing to the bus signal.
Application Information
Due to the high current and very high speed capability of the
TURBOTRANSCEIVER’s driver output stage, circuit board
layout and bus grounding are critical factors that affect the
system performance.
Each of the TURBOTRANSCEIVER’s bus ground pins
should be connected to the nearest backplane ground pin
with the shortest possible path. The ground pins on the
connector should be distributed evenly through its length.
Although the bandgap reference receiver threshold provides
sufficient DC noise margin (Figure 9), ground noise and
ringing on the data paths could easily exceed this margin if
the series inductance of the traces and connectors are not
kept to a minimum. The bandgap ground pin should be
returned to the connector through a separate trace that does
00869810
FIGURE 9. Noise Margin
5
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DS3893A
Application Information
(Continued)
00869811
FIGURE 10.
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6
DS3893A BTL TURBOTRANSCEIVER
Physical Dimensions
inches (millimeters) unless otherwise noted
Plastic Chip Carrier (V)
Order Number DS3893AV
NS Package Number V20A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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