LINER LT1186F Dac programmable ccfl switching regulator Datasheet

LT1186F
DAC Programmable
CCFL Switching Regulator
(Bits-to-NitsTM)
face modes including standard SPI mode and pulse mode.
On power-up, the DAC counter resets to half-scale and the
Wide Battery Input Range: 4.5V to 30V
DAC configures to SPI or pulse mode depending on the CS
Grounded Lamp or Floating Lamp Configurations
signal level. In SPI mode, the system microprocessor
Open Lamp Protection
serially transfers the present 8-bit data and reads back the
Precision 50µA Full-Scale DAC Programming Current previous 8-bit data. In pulse mode, the upper six bits of the
Standard SPI Mode or Pulse Mode
DAC configure as increment-only (1-wire interface) or
DAC Setting Is Retained in Shutdown
increment/decrement (2-wire interface) operation dependU
ing on the DIN signal level.
FEATURES
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APPLICATIONS
■
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The LT1186F control circuitry operates from a logic supply
voltage of 3.3V or 5V. The IC also has a battery supply
voltage pin that operates from 4.5V to 30V. The LT1186F
draws 6mA typical quiescent current. An active low shutdown pin reduces total supply current to 35µA for standby
operation and the DAC retains its last setting. A 200kHz
switching frequency minimizes magnetic component size.
Current mode switching techniques with cycle-by-cycle
limiting gives high reliability and simple loop frequency
compensation. The LT1186F is available in a 16-pin narrow SO package.
Notebook and Palmtop Computers
Portable Instruments
Retail Terminals
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DESCRIPTION
The LT ®1186F is a fixed frequency, current mode, switching regulator that provides the control function for Cold
Cathode Fluorescent Lighting (CCFL). The IC includes an
efficient high current switch, an oscillator, output drive
logic, control circuitry and a micropower 8-bit 50µA fullscale current output DAC. The DAC provides simple “bitsto-lamp current control” and communicates in two inter-
, LTC and LT are registered trademarks of Linear Technology Corporation.
Bits-to-Nits is a trademark of Linear Technology Corporation. 1 Nit = 1 Candela/meter2
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TYPICAL APPLICATION
90% Efficient Floating CCFL with 1-Wire (Increment Only) Pulse Mode Control of Lamp Current
1
2
3
C7, 1µF
FROM MPU
CCFL
PGND
ICCFL
CCFL VSW
BULB
16
6
7
8
VCC
SHDN
IOUT
CLK
CS
DOUT
10
3
6
2
+
R2
220k
12
11
C2
27pF
3kV
L2 = COILTRONICS CTX100-4
*DO NOT SUBSTITUTE COMPONENTS
L1
15
DIO
AGND
L1 = COILTRONICS CTX210605
LAMP
C5
1000pF
14
BAT
LT1186F
4
13
CCFL VC
ROYER
5
SHUTDOWN
UP TO 6mA
CCFL BACKLIGHT APPLICATION CIRCUITS
CONTAINED IN THIS DATA SHEET ARE COVERED
BY U.S. PATENT NUMBER 5408162
AND OTHER PATENTS PENDING
D1
BAT85
+
VIN
3.3V
OR
5V
C4
2.2µF
10
DIN 9
ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3A AND C3B.
MAKE 3CB ESR ≥ 0.5Ω TO PREVENT DAMAGE TO THE LT1186F HIGH-SIDE
SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON
0µA TO 50µA ICCFL CURRENT GIVES
C1 MUST BE A LOW LOSS CAPACITOR, C1 = WIMA MKP-20
0mA TO 6mA LAMP CURRENT
Q1, Q2 = ZETEX ZTX849 OR ROHM 2SC5001
FOR A TYPICAL DISPLAY.
1
4
+
C3B
2.2µF
35V
Q2*
C3A
2.2µF
35V
BAT
8V TO 28V
R1
750Ω
C1*
0.068µF
R3
100k
COILTRONICS (407) 241-7876
5
Q1*
L2
100µH
D1
1N5818
LT1186F • TA01
FOR ADDITIONAL CCFL/LCD CONTRAST APPLICATION CIRCUITS,
REFER TO THE LT1182/83/84/84F DATA SHEET
1
LT1186F
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VCC ........................................................................... 7V
BAT, Royer, BULB .................................................. 30V
CCFL VSW ............................................................... 60V
Shutdown ................................................................. 6V
ICCFL Input Current .............................................. 10mA
DIO Input Current (Peak, < 100ms).................... 100mA
Digital Inputs ................................ – 0.3V to VCC + 0.3V
Digital Outputs .............................. – 0.3V to VCC + 0.3V
DAC Output Voltage ....................... – 20V to VCC + 0.3V
Junction Temperature (Note 1) ........................... 100°C
Operating Ambient Temperature Range
LT1186FC ............................................ 0°C to 100°C
LT1186FI .......................................... – 40°C to 100°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
TOP VIEW
CCFL PGND 1
ICCFL 2
DIO 3
CCFL VC 4
15 BULB
14 BAT
12 VCC
SHDN 6
11 IOUT
CS 8
LT1186FCS
LT1186FIS
13 ROYER
AGND 5
CLK 7
ORDER PART
NUMBER
16 CCFL VSW
10 DOUT
9
DIN
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 100°C, θJA = 100°C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DOUT = Three-State, DIO = IOUT
= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.
xSYMBOL PARAMETER
CONDITIONS
IQ
Supply Current
3V ≤ VCC ≤ 6.5V, 1/2 Full-Scale DAC Output Current
ISHDN
SHUTDOWN Supply Current
SHUTDOWN = 0V, CCFL VC Open (Note 2)
SHUTDOWN Input Bias Current
SHUTDOWN = 0V, CCFL VC = Open
5
SHUTDOWN Threshold Voltage
f
DC(MAX)
BV
Switching Frequency
Maximum Switch Duty Cycle
Measured at CCFL VSW, ISW = 50mA,
ICCFL = 100µA, CCFL VC = Open
MIN
●
Measured at CCFL VSW
Switch Leakage Current
VSW = 12V, Measured at CCFL VSW
VSW = 30V, Measured at CCFL VSW
ICCFL Summing Voltage
3V ≤ VCC ≤ 6.5V
UNITS
6
9.5
mA
35
70
µA
10
µA
0.45
0.85
1.2
V
●
175
160
200
200
225
240
kHz
kHz
●
80
75
85
85
%
%
60
70
V
●
20
40
µA
µA
0.465
0.465
0.505
0.555
V
V
5
15
mV
–5
5
15
µA
0.425
0.385
∆ICCFL Summing Voltage for
∆Input Programming Current
ICCFL = 0µA to 100µA
CCFL VC Offset Sink Current
CCFL VC = 1.5V, Positive Current Measured into Pin
∆CCFL VC Source Current for
∆ICCFL Programming Current
ICCFL = 25µA, 50µA, 75µA, 100µA,
CCFL VC = 1.5V
TJ < 0°C
●
4.70
4.95
5.20
µA/µA
●
4.60
4.95
5.20
µA/µA
DIO = 5mA out of Pin, Measure I(VC) at CCFL VC = 1.5V
●
94
99
104
µA/mA
CCFL VC Low Clamp Voltage
VBAT – VBULB = BULB Protect Servo Voltage
●
0.1
0.3
V
CCFL VC High Clamp Voltage
ICCFL = 100µA
●
1.7
2.1
2.4
V
CCFL VC Switching Threshold
CCFL VSW DC = 0%
●
0.6
0.95
1.3
V
CCFL VC to DIO Current Servo Ratio
2
MAX
●
Measured at CCFL VSW
Switch Breakdown Voltage
TYP
LT1186F
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DOUT = Three-State, DIO = IOUT
= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
CCFL High-Side Sense Servo Current
ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V
TJ < 0°C
CCFL High-Side Sense Servo Current
Line Regulation
BAT = 5V to 30V, ICCFL = 100µA,
I(VC) = 0µA at CCFL VC = 1.5V
●
●
MIN
TYP
MAX
UNIT
0.93
0.91
1.00
1.00
1.07
1.07
A
A
0.1
0.16
%/V
CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins
●
50
100
150
µA
BULB Protect Servo Voltage
●
6.5
7.0
7.5
V
5
9
µA
1.25
0.9
1.9
1.6
3.0
2.6
A
A
0.6
1.0
Ω
20
30
mA/A
ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V,
Servo Voltage Measured between BAT and BULB Pins
BULB Input Bias Current
ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V
ILIM
CCFL Switch Current Limit
Duty Cycle = 50%
Duty Cycle = 75% (Note 3)
●
●
VSAT
CCFL Switch On Resistance
CCFL ISW = 1A
●
∆IQ
∆ISW
Supply Current Increase During
CCFL Switch On Time
CCFL ISW = 1A
DAC Resolution
DAC Full-Scale Current
8
V(IOUT) = 0.465V, Measured in SPI Mode
●
DAC Zero Scale Current
48.5
47.0
50
50
V(IOUT) = 0.465V, Measured in SPI Mode
DAC Differential Nonlinearity
●
Bits
51.5
53.0
µA
µA
200
nA
±2.0
LSB
4
LSB
±1
µA
DAC Supply Voltage Rejection
3V ≤ VCC ≤ 6.5V, IOUT = Full Scale, V(IOUT) = 0.465V
●
Logic Input Current
0V ≤ VIN ≤ VCC
●
VIH
High Level Input Voltage
VCC = 3.3V
VCC = 5V
●
●
VIL
Low Level Input Voltage
VCC = 3.3V
VCC = 5V
●
●
VOH
High Level Output Voltage
VCC = 3.3V, IO = 400µA
VCC = 5V, IO = 400µA
●
●
VOL
Low Level Output Voltage
VCC = 3.3V, IO = 1mA
VCC = 5V, IO = 2mA
●
●
0.4
0.4
V
V
IOZ
Three-State Output Leakage
VCS = VCC
●
±5
µA
2
MHz
2
1.9
2
V
V
0.45
0.80
2.1
2.4
V
V
V
V
SERIAL INTERFACE (Notes 4, 5)
fCLK
Clock Frequency
●
tCKS
Setup Time, CLK↓ Before CS↓
●
150
ns
tCSS
Setup Time, CS↓ Before CLK↑
●
400
ns
tDV
CS↓ to DOUT Valid
●
150
ns
tDS
Data in Setup Time Before CLK↑
●
150
ns
tDH
Data in Hold Time After CLK↑
●
150
ns
tDO
CLK↓ to DOUT Valid
●
150
ns
tCKHI
CLK High Time
●
200
ns
tCKLO
CLK Low Time
●
250
ns
tCSH
CLK↓ Before CS↑
●
150
tDZ
CS↑ to DOUT In Hi-Z
tCKH
CS↑ Before CLK↑
See Test Circuits
See Test Circuits
See Test Circuits
ns
●
400
ns
●
400
ns
3
LT1186F
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DOUT = Three-State, DIO = IOUT
= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL INTERFACE (Notes 4, 5)
tCSLO
CS Low Time
tCSHI
CS High Time
fCLK = 2MHz
The ● denotes specifications which apply over the specified operating
temperature range.
Note 1: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LT1186FCS: TJ = TA + (PD)(100°C/W)
Note 2: Does not include switch leakage.
●
4550
ns
●
400
ns
Note 3: For duty cycles (DC) between 50% and 80%, minimum
guaranteed switch current is given by ILIM = 1.4(1.393 – DC) for the
LT1186F due to internal slope compensation circuitry.
Note 4: Timings for all input signals are measured at 0.8V for a High-toLow transition and 2.0V for a Low-to-High transition.
Note 5: Timings are guaranteed but not tested.
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TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Current
vs Temperature
90
8
8O
SHUTDOWN CURRENT (µA)
100
9
SUPPLY CURRENT (mA)
10
7
6
5
4
3
2
6
70
60
50
VCC = 5V
40
30
VCC = 3V
20
10
1
Shutdown Threshold Voltage
vs Temperature
0.7
LT1186F • G04
2
VCC = 3V
1
Maximum Duty Cycle
vs Temperature
240
95
230
93
220
210
200
190
180
170
0.6
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
VCC = 5V
LT1186F • G03
CCFL MAXIMUM DUTY CYCLE (%)
CCFL FREQUENCY (kHz)
SHUTDOWN THRESHOLD VOLTAGE (V)
1.1
0.8
3
Frequency vs Temperature
1.2
0.9
4
LT1186F • G02
LT1186F • G01
1.0
5
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
4
Shutdown Input Bias Current
vs Temperature
SHUTDOWN INPUT BIAS CURRENT (µA)
Supply Current
vs Temperature
160
–75 –50 –25
91
89
87
85
83
81
79
77
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G05
75
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G06
LT1186F
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TYPICAL PERFORMANCE CHARACTERISTICS
ICCFL Summing Voltage
Load Regulation
T = –55°C
T = 25°C
T = 125°C
0
20 40 60 80 100 120 140 160 180 200
ICCFL PROGRAMMING CURRENT (µA)
5.05
1.0
POSITIVE DIO VOLTAGE (V)
ICCFL = 10µA
4.90
4.85
4.80
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.6
1.4
I(DIO) = 10mA
I(DIO) = 5mA
0.8
0.6
I(DIO) = 1mA
0.4
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
I(DIO) = 10mA
I(DIO) = 5mA
98
97
96
95
–75 – 50 –25
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G13
I(DIO) = 1mA
0.6
0.4
0
–75 –50 –25
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G12
VC High Clamp Voltage
vs Temperature
0.30
CCFL VC LOW CLAMP VOLTAGE (V)
CCFL VC DIO CURRENT SERVO RATIO (µA/mA)
103
99
0.8
VC Low Clamp Voltage
vs Temperature
I(DIO) = 1mA
I(DIO) = 5mA
1.0
LT1186F • G11
VC to DIO Current Servo
Ratio vs Temperature
100
I(DIO) = 10mA
1.2
0.2
LT1186F • G10
101
3
2
1
CCFL VC = 0.5V
0
–1
–2
–3
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
Negative DIO Voltage
vs Temperature
0.2
102
CCFL VC = 1.0V
LT1186F • G09
2.4
CCFL VC HIGH CLAMP VOLTAGE (V)
∆CCFL VC SOURCE CURRENT FOR
∆ICCFL PROGRAMMING CURRENT (µA/µA)
1.2
ICCFL = 50µA
CCFL VC = 1.5V
4
Positive DIO Voltage
vs Temperature
5.10
4.95
9
8
7
6
5
LT1186F • G08
∆CCFL VC Source Current for
∆ICCFL Programming Current
vs Temperature
ICCFL = 100µA
CCFL VC SINK OFFSET CURRENT (µA)
10
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
LT1186F • G07
5.00
VC Sink Offset Current
vs Temperature
NEGATIVE DIO VOLTAGE (V)
0.53
0.52
0.51
0.50
0.49
0.48
0.47
0.46
0.45
0.44
0.43
0.42
0.41
0.40
0.39
0.38
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
∆ICCFL SUMMING VOLTAGE (mV)
ICCFL SUMMING VOLTAGE (V)
ICCFL Summing Voltage
vs Temperature
0.25
0.20
0.15
0.10
0.05
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G14
2.3
2.2
2.1
2.0
1.9
1.8
1.7
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G15
5
LT1186F
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TYPICAL PERFORMANCE CHARACTERISTICS
BULB Protect Servo Voltage
vs Temperature
1.1
1.0
0.9
0.8
0.7
BULB INPUT BIAS CURRENT (µA)
1.2
10
7.4
7.3
7.2
ICCFL = 100µA
7.1
7.0
6.9
ICCFL = 50µA
6.8
6.7
6.6
6.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0.6
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
2
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G18
High-Side Sense Null Current Line
Regulation vs Temperature
130
120
110
100
90
80
70
60
50
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.040
1.020
1.000
0.980
0.960
0.940
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
CCFL HIGH-SIDE SENSE LINE REGULATI0N (%V)
CCFL HIGH-SIDE SENSE NULL CURRENT (A)
140
1.060
0.160
0.140
0.120
0.100
0.080
0.060
0.040
0.020
0.000
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
LT1186F • G20
LT1186F • G19
VSW Sat Voltage
vs Switch Current
LT1186F • G21
VSW Current Limit vs Duty Cycle
1.0
Forced Beta vs ISW on VSW
110
2.5
100
T = 25°C
0.7
T = 125°C
0.6
T = –5°C
0.5
0.4
0.3
0.2
90
2.0
T = 0°C
80
T = 25°C
1.5
FORCED BETA
0.8
CCFL VSW CURRENT LIMIT (A)
0.9
CCFL VSW SAT VOLTAGE (V)
4
High-Side Sense Null
Current vs Temperature
150
T = 125°C
MINIMUM
1.0
70
60
50
40
30
0.5
20
0.1
10
0
0.3
0.9
1.2
0.6
SWITCH CURRENT (A)
1.5
LT1186F • G22
6
6
LT1186F • G17
High-Side Sense Supply Current
vs Temperature
0
8
ICCFL = 10µA
LT1186F • G16
CCFL HIGH-SIDE SENSE SUPPLY CURRENT (µA)
BULB Input Bias Current
vs Temperature
7.5
1.3
BULB PROTECT SERVO VOLTAGE (V)
CCFL VC SWITCHING THRESHOLD VOLTAGE (V)
VC Switching Threshold
vs Temperature
0
0
0
10
20
30 40 50 60
DUTY CYCLE (%)
70
80
90
LT1186F • G23
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CCFL ISW (A)
LT1186F • G24
LT1186F
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TYPICAL PERFORMANCE CHARACTERISTICS
DAC IOUT vs Temperature
DAC IOUT vs Supply Voltage
52
VOUT = 0V
VOUT = 0V
TJ = 25°C
52
VCC = 5V
50
VCC = 3.3V
49
52
51
OUTPUT CURRENT (µA)
51
OUTPUT CURRENT (µA)
OUTPUT CURRENT (µA)
DAC IOUT vs IOUT Bias Voltage
53
53
50
49
48
47
–25
0
25
50
TEMPERATURE (°C)
75
100
51
VCC = 5V
50
49
VCC = 3.3V
48
47
46
46
48
–50
TJ = 25°C
45
0
4
2
6
SUPPLY VOLTAGE (V)
LT1186F • G25
8
LT1186F • G26
45
–20
–15
5
–10
–5
0
OUTPUT BIAS VOLTAGE (V)
10
LT1186F • G27
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PIN FUNCTIONS
CCFL PGND (Pin 1): This pin is the emitter of an internal
NPN power switch. CCFL switch current flows through
this pin and permits internal, switch-current sensing. The
regulator provides a separate analog ground and power
ground to isolate high current ground paths from low
current signal paths. Linear Technology recommends the
use of star-ground layout techniques.
ICCFL (Pin 2): This pin is the input to the CCFL lamp current
programming circuit. This pin internally regulates to
465mV. The pin accepts a DC input current signal of 0µA
to 50µA full scale from the DAC. This input signal is
converted to a 0µA to 250µA source current at the CCFL VC
pin. As input programming current increases, the regulated lamp current increases. For a typical 6mA lamp, the
range of input programming current is about 0µA to 50µA.
DIO (Pin 3): This pin is the common connection between
the cathode and anode of two internal diodes. The remaining terminals of the two diodes connect to ground. In a
grounded-lamp configuration, DIO connects to the low
voltage side of the lamp. Bidirectional lamp current flows
in the DIO pin and thus the diodes conduct alternately on
half cycles. Lamp current is controlled by monitoring onehalf of the average lamp current. The diode conducting on
negative half cycles has one-tenth of its current diverted to
the CCFL VC pin. This current nulls against the source
current provided by the lamp-current programmer circuit.
A single capacitor on the CCFL VC pin provides both stable
loop compensation and an averaging function to the halfwave-rectified sinusoidal lamp current. Therefore, input
programming current relates to one-half of average lamp
current. This scheme reduces the number of loop compensation components and permits faster loop transient
response in comparison to previously published circuits.
If a floating lamp configuration is used, ground the DIO
pin.
CCFL VC (Pin 4): This pin is the output of the lamp current
programmer circuit and the input of the current comparator for the CCFL regulator. Its uses include frequency
compensation, lamp-current averaging for grounded-lamp
circuits and current limiting. The voltage on the CCFL VC
pin determines the current trip level for switch turn-off.
During normal operation this pin sits at a voltage between
0.95V (zero switch current) and 2.0V (maximum switch
current) with respect to analog ground (AGND). This pin
has a high impedance output and permits external voltage
clamping to adjust current limit. A single capacitor to
ground provides stable loop compensation. This simplified loop compensation method permits the CCFL regulator to exhibit single-pole transient response behavior and
virtually eliminates transformer output overshoot.
7
LT1186F
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PIN FUNCTIONS
AGND (Pin 5): This is the low current analog ground. It is
the negative sense terminal for the internal 1.24V reference and the ICCFL summing voltage in the LT1186F.
Connect low current signal paths that terminate to ground
and frequency compensation components that terminate
to ground directly to this pin for best regulation and
performance.
SHDN (Pin 6): Pulling this pin low causes complete
regulator shutdown with quiescent current typically reduced to 35µA. If the pin is not used, use a pull-up resistor
to force a logic high level (maximum of 6V) or tie directly
to VCC. In a shutdown condition, the DAC retains its last
output current setting and returns to this level when the
logic-low signal at the shutdown pin is removed.
CLK (Pin 7): This pin is the shift clock for the DAC. This
clock synchronizes the serial data and is a Schmitt
trigger input. In standard SPI mode, the clock shifts data
into DIN and out of DOUT on the rising and falling edges
of the clock respectively. In pulse mode, the rising edge
of the clock either increments or decrements the counter.
This action depends on the choice of a 1-wire interface
(increment only) or a 2-wire interface (increment/decrement).
CS (Pin 8): This pin is the chip select input for the DAC. In
SPI mode, a logic low on the CS pin enables the DAC to
receive and transfer 8-bit serial data. After the serial input
data is shifted in, a rising edge of CS transfers the data into
the counter, the DAC assumes the new IOUT value and the
DOUT pin returns to the high impedance state. On power
up, a logic high places the DAC into pulse mode. Pulling CS
low after this places the DAC into SPI mode until VCC
resets.
DIN or UP/DN (Pin 9): This pin is the digital input for the
DAC. In SPI mode, the 8-bit serial data is shifted into the
DIN input on each rising edge of the clock signal. In pulse
mode, on power up, a logic high at DIN transfers the pin
function from DIN to UP/DN, puts the counter into increment-only mode and the pin function shifts to up or down
increment control of DAC output current. If UP/DN receives a logic-low signal, the counter configures to increment/decrement mode until VCC resets.
8
DOUT (Pin 10): This pin is the digital output for the DAC. In
SPI mode, DOUT is in three-state until CS falls low. The
DOUT pin then serially transfers the previous 8-bit data on
every falling edge of the clock. When CS rises high again,
DOUT returns to a three-state condition. In pulse mode,
DOUT is always three-stated.
IOUT (Pin 11): This pin is the analog current output for the
DAC and provides an output current of 50 ±3µA over
temperature. This pin can be biased from – 20V to 2V for
a 3.3V VCC supply voltage or from – 20V to 2.5V for a 5V
VCC supply voltage. However, this pin is tied to the ICCFL pin
and provides the programming current which sets operating lamp current. The IOUT pin has very little bias voltage
change when it is tied to the ICCFL pin as ICCFL is regulated.
The programming current is sourced from the IOUT pin and
sunk by the ICCFL pin.
VCC (Pin 12): This is the supply pin for the LT1186F. The
IC accepts an input voltage range of 3V minimum to 6.5V
maximum with little change in quiescent current (zero
switch current). An internal, low-dropout regulator provides a 2.4V supply for most of the internal circuitry.
Supply current increases as switch current increases at a
rate approximately 1/50 of switch current. This corresponds to a forced Beta of 50 for the power switch. The IC
incorporates undervoltage lockout by sensing regulator
dropout and locking out switching for input voltages
below 2.5V. Hysteresis is not used to maximize the useful
range of input voltage. The typical input voltage is a 3.3V
or 5V logic supply.
ROYER (Pin 13): This pin connects to the center-tapped
primary of the Royer converter and is used with the BAT
pin in a floating-lamp configuration where lamp current is
controlled by sensing Royer primary-side converter current. This pin is the inverting terminal of a high-side
current sense amplifier. The typical quiescent current is
50µA into the pin. If the CCFL regulator is not used in a
floating-lamp configuration, tie the Royer and BAT pins
together.
LT1186F
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BAT (Pin 14): This pin connects to the battery or AC wall
adapter voltage from which the CCFL Royer converter
operates. This voltage is typically higher than the VCC
supply voltage but can equal VCC if VCC is a 5V logic supply.
The BAT voltage must be at least 2.1V greater than the
internal 2.4V regulator or 4.5V. This pin provides biasing
for the lamp-current programming block, is used with the
Royer pin for floating-lamp configurations and connects
to one input for the open-lamp protection circuitry. For
floating-lamp configurations, this pin is the noninverting
terminal of a high-side current sense amplifier. The typical
quiescent current is 50µA into the pin. The BAT and Royer
pins monitor the primary-side Royer converter current
through an internal 0.1Ω topside current sense resistor. A
0A to1A primary-side, center tap converter current is
translated to an input signal range of 0mV to 100mV for the
current sense amplifier. This input range translates to a
0µA to 500µA sink current at the CCFL VC pin that nulls
against the source current provided by the programmer
circuit. The BAT pin also connects to the topside of the
internal clamp between the BAT and BULB pins that is used
for open-lamp protection.
BULB (Pin 15): This pin connects to the low side of a 7V
threshold comparator between the BAT and BULB pins.
This circuit sets the maximum voltage level across the
primary side of the Royer converter under all operating
conditions and limits the maximum secondary output
under start-up conditions or open-lamp conditions. This
eases transformer voltage rating requirements. Set the
voltage limit to ensure lamp start-up with worst-case,
lamp start voltages and cold temperature, system operating conditions. The BULB pin connects to the junction of
an external divider network. The divider network connects
from the center tap of the Royer transformer or the actual
battery supply voltage to the topside of the current source
“tail inductor.” A capacitor across the top of the divider
network filters switching ripple and sets a time constant
that determines how quickly the clamp activates. When
the comparator activates, sink current is generated to pull
the CCFL VC pin down. This action transfers the entire
regulator loop from current mode operation into voltage
mode operation.
CCFL VSW (Pin 16): This pin is the collector of the internal
NPN power switch for the CCFL regulator. The power
switch provides a minimum of 1.25A. Maximum switch
current is a function of duty cycle as internal slope compensation ensures stability with duty cycles greater than
50%. Using a driver loop to automatically adapt base drive
current to the minimum required to keep the switch in a
quasi-saturation state yields fast switching times and high
efficiency operation. The ratio of switch current to driver
current is about 50:1.
TEST CIRCUITS
Voltage Waveforms for tDZ, tDV
Voltage Waveforms for tDO
Load Circuit for tDO
1.4V
CLK
3k
2.0V
CS
0.8V
0.8V
tDO
DOUT
2.4V
DOUT
100pF
0.4V
DOUT
WAVEFORM 1
(SEE NOTE 1)
DOUT
WAVEFORM 2
(SEE NOTE 2)
Load Circuit for tDZ, tDV
3k
0.4V
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS
DISABLED BY CS
5V t DZ WAVEFORM 2, t DV
DOUT
100pF
tDZ
tDV
LT1186F • TC03
LT1186F • TC01
90%
2.4V
t DZ WAVEFORM 1
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS
DISABLED BY CS
LT1186F • TC04
LT1186F • TC02
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LT1186F
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LT1186F DAC Programmable CCFL Switching Regulator
VCC
BAT
14
12
SHUTDOWN 6
SHUTDOWN
UNDERVOLTAGE
LOCKOUT
2.4V
REGULATOR
ROYER
13
THERMAL
SHUTDOWN
CCFL
VSW
16
200kHz
OSC
LOGIC
R4
0.1Ω
ANTISAT
+
–
D2
6V
gm
COMP
R3
1k
0µA TO 50µA FROM IOUT
Q5
1×
+
Q6
2×
+
Q4
5×
–
Q7
9×
Q11
–
GAIN = 4.4
Q8
1×
Q10
2×
Q9
3×
V1
0.465V
R1
0.125Ω
CURRENT
AMP
Q3
2×
CCFL
Q1
DRIVE
D1
2
5
3
15
4
1
ICCFL
AGND
DIO
BULB
CCFL
VC
CCFL
PGND
POWER-ON
RESET
LATCH
AND
LOGIC
VOLTAGE
REFERENCE
SHDN
UP ONLY/
UP/DN
LATCH
AND
LOGIC
SHDN
MODE SELECT
0 = PULSE
1 = SPI
CS 8
11 IOUT
50µA
FULL SCALE
8
CLK
CLK 7
DIN 9
8-BIT
CURRENT
DAC
8-BIT COUNTER/REGISTER
UP/DN
CONTROL
LOGIC
8
8
CLK
9-BIT SHIFT REGISTER
DO(LSB)
Q9
10 DOUT
LT1186F • BD
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Introduction
Current generation portable computers and instruments
use backlit Liquid Crystal Displays (LCDs). Cold Cathode
Fluorescent Lamps (CCFLs) provide the highest available
efficiency in back lighting the display. Providing the most
light out for the least amount of input power is the most
important goal. These lamps require high voltage AC to
operate, mandating an efficient high voltage DC/AC converter. The lamps operate from DC, but migration effects
damage the lamp and shorten its lifetime. Lamp drive
should contain zero DC component. In addition to good
efficiency, the converter should deliver the lamp drive in
the form of a sine wave. This minimizes EMI and RF
emissions. Such emissions can interfere with other devices and can also degrade overall operating efficiency.
Sinusoidal CCFL drive maximizes current-to-light conversion in the lamp. The circuit should also permit lamp
intensity control from zero to full brightness with no
hysteresis or “pop-on.”
The small size and battery-powered operation associated
with LCD equipped apparatus dictate low component
count and high efficiency for these circuits. Size constraints place severe limitations on circuit architecture and
long battery life is a priority. Laptop and handheld portable
computers offer an excellent example. The CCFL and its
power supply are responsible for almost 50% of the
battery drain. Additionally, all components, including PC
board and hardware, usually must fit within the LCD
enclosure with a height restriction of 5mm to 10mm.
The CCFL regulator drives an inductor that acts as a
switched-mode current source for a current-driven Royerclass converter with efficiencies as high as 90%. The
control loop forces the CCFL PWM to modulate the average inductor current to maintain constant current in the
lamp. The constant current value, and thus lamp intensity,
is programmable. This drive technique provides a wide
range of intensity control. A unique lamp-current programming block permits either grounded lamp or floating
lamp configurations. Grounded lamp circuits directly sense
one-half of average lamp current. Floating lamp circuits
directly sense the Royer’s primary-side converter current.
Floating-lamp circuits provide symmetric differential drive
to the lamp and reduce the parasitic loss from stray lampto-frame capacitance, extending illumination range.
Block Diagram Operation
The LT1186F is a fixed frequency, current mode switching
regulator. A fixed frequency, current mode switcher controls switch duty cycle directly by switch current rather
than by output voltage. Referring to the block diagram for
the LT1186F, the switch turns ON at the start of each
oscillator cycle. The switch turns OFF when switch current
reaches a predetermined level. The control of output lamp
current is obtained by using the output of a unique
programming block to set current trip level. The current
mode switching technique has several advantages. First,
it provides excellent rejection of input voltage variations.
Second, it reduces the 90° phase shift at mid-frequencies
in the energy storage inductor. This simplifies closed-loop
frequency compensation under widely varying input voltage or output load conditions. Finally, it allows simple
pulse-by-pulse current limiting to provide maximum switch
protection under output overload or short-circuit conditions.
The LT1186F incorporates a low dropout internal regulator that provides a 2.4V supply for most of the internal
circuitry. This low dropout design allows input voltage to
vary from 3V to 6.5V with little change in quiescent
current. An active low shutdown pin typically reduces total
supply current to 35µA by shutting off the 2.4V regulator
and locks out switching action for standby operation. The
IC incorporates undervoltage lockout by sensing regulator
dropout and locking out switching below about 2.5V. The
regulator also provides thermal shutdown protection that
locks out switching in the presence of excessive junction
temperatures.
A 200kHz oscillator is the basic clock for all internal timing.
The oscillator turns on the output switch via its own logic
and driver circuitry. Adaptive anti-sat circuitry detects the
onset of saturation in the power switch and adjusts base
drive current instantaneously to limit switch saturation.
This minimizes driver dissipation and provides rapid turnoff of the switch. The CCFL power switch is guaranteed to
provide a minimum of 1.25A in the LT1186F. The anti-sat
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circuitry provides a ratio of switch current to driver current
of about 50:1.
POWER ON
VCC
8-Bit Current Output DAC
CS ALWAYS HIGH
The 8-bit current output DAC is guaranteed monotonic and
is digitally adjustable by the 8-bit counter in 256 equal
steps. On power up, the counter resets to 80H and the DAC
assumes its mid-range value. The current output IOUT
drives the ICCFL pin and sets control current for the lamp
current programming block. The DAC has its own 1.24V
bandgap reference and a voltage to current converter that
is trimmed at wafer sort to provide the precision full-scale
current reference. Over temperature, the current output of
the DAC is 50µA ±6%.
DIN ALWAYS HIGH
LT1186F • F01c
Figure 1c. Pulse Mode Setup (Increment Only)
POWER ON
VCC
CS ALWAYS HIGH
UP/DN
Digital Interface
UP/DN EVER GOES LOW
On power-up, a logic high at CS configures the DAC into
pulse mode. If CS is ever pulled low, the chip configures
into SPI mode until VCC resets. On power-up in pulse
mode, a logic high at DIN puts the counter into incrementonly mode. If UP/DN (DIN) is ever pulled low, the counter
configures into increment/decrement mode until VCC resets. These modes are illustrated in Figure 1.
SINGLE DAC
CS STAYS
HIGH
CS EVER
GOES LOW
SPI MODE
PULSE MODE
DIN (UP/DN)
EVER GOES
LOW
DIN STAYS
HIGH
INCREMENT/
DECREMENT
INCREMENTONLY
LT1186F • F01a
Figure 1a. Tree Diagram (LT1186F DAC Operating Modes)
POWER ON
VCC
CS
CS EVER GOES LOW
Figure 1b. SPI Mode Setup
12
LT1186F • F01b
LT1186F • F01d
Figure 1d. Pulse Mode Setup (Increment/Decrement)
Standard SPI Mode
Refer to the serial interface operating sequence in Figure
2. A falling edge at CS initiates the data transfer. After the
falling CS is recognized, DOUT comes out of three-state.
The clock (CLK) synchronizes the data transfer. Each input
bit shifts into DIN beginning with the MSB on the rising CLK
edge and each previous data bit shifts out of DOUT beginning with the MSB on the falling CLK edge. After the 8-bit
serial input data is shifted in, a rising edge at CS transfers
the data into the counter, the DAC assumes the new value
IOUT = (8-bit serial input data)(50µA)/255 and the DOUT pin
returns to a high impedance state.
1-Wire Interface (Pulse Mode)
In increment-only pulse mode, each rising edge of CLK
increments the upper six bits of the counter by one count.
When incremented beyond 11111100B, the counter rolls
over and sets the DAC to the minimum value 00000000B.
Therefore, a single pulse applied to CLK increases the
upper 6-bit counter by one-step, and 63 pulse applied to
CLK decreases the counter by one-step. The last two LSBs
are always zero in this mode. IOUT = (B7B6B5B4B3B2B1B0)
(50µA)/255. The upper 6-bit counter = B7B6B5B4B3B2 and
B1 = B0 = 0. To configure the LT1186F into increment-only
mode, tie CS and DIN to VCC.
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tCSLO
tCSHI
CS
tCKS
tCSH
tCKHI
CLK
tCSS
DIN
tDS
D7
D6
D5
D4
D3
D2
DOUT
D7′
D1
D0
tDO
tDV
Hi-Z
tCKH
tCKLO
tDH
D6′
D5′
D4′
D3′
tDZ
D2′
D1′
D0′
D7
Hi-Z
LT1186F • F02
Figure 2. SPI Interface Timing Specification
2-Wire Interface (Pulse Mode)
In increment/decrement pulse mode, a logic high at UP/
DN programs the counter into increment mode and each
rising edge of CLK increments the upper six bits of the
counter by one. The counter stops incrementing at
11111100B. A logic low at UP/DN programs the counter
into decrement mode and each rising edge of CLK decrements the upper six bits of the counter by one. The counter
stops decrementing at 00000000B. The last two LSBs are
always zero in this mode. IOUT = (B7B6B5B4B3B2B1B0)
(50µA)/255. The upper 6-bit counter = B7B6B5B4B3B2 and
B1 = B0 = 0. To configure the LT1186F into increment/
decrement mode, tie CS to VCC and pulse the UP/DN pin
once on power-up.
Simplified Lamp Current Programming
A programming block in the LT1186F controls lamp
current, permitting either grounded lamp or floating lamp
configurations. Grounded configurations control lamp
current by directly controlling one-half of actual lamp
current and converting it to a feedback signal to close a
control loop. Floating configurations control lamp current
by directly controlling the Royer’s primary-side converter
current and generating a feedback signal to close a control
loop.
Previous backlighting solutions have used a traditional
error amplifier in the control loop to regulate lamp current.
This approach converted an RMS current into a DC voltage
for the input of the error amplifier. This approach used
several time constants in order to provide stable loop
frequency compensation. This compensation scheme
meant that the loop had to be fairly slow and that output
overshoot with start-up or overload conditions had to be
carefully evaluated in terms of transformer stress and
breakdown voltage requirements.
The LT1186F eliminates the error amplifier concept entirely and replaces it with a lamp current programming
block. This block provides an easy-to-use interface to
program lamp current. The programmer circuit also reduces the number of time constants in the control loop by
combining the error signal conversion scheme and frequency compensation into a single capacitor. The control
loop thus exhibits the response of a single pole system,
allows for faster loop transient response and virtually
eliminates overshoot under start-up or overload conditions.
Lamp current is programmed at the input of the programmer block, the ICCFL pin. This pin is the input of a shunt
regulator and accepts a DC input current signal of 0µA to
50µA from the DAC. This input signal is converted to a 0µA
to 250µA source current at the CCFL VC pin. The programmer circuit is simply a current-to-current converter with a
gain of five. The typical input current programming range
for 0mA to 6mA lamp current is 0µA to 50µA.
The ICCFL pin is sensitive to capacitive loading and will
oscillate with capacitance greater than 10pF. For example,
loading the ICCFL pin with a 1× or 10× scope probe causes
oscillation and erratic CCFL regulator operation because
of the probe’s respective input capacitance. A current
meter in series with the ICCFL pin will also produce oscil-
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lation due to its shunt capacitance. Use a decoupling
resistor of several kilohms between the ICCFL pin and the
IOUT pin if excessive trace stray capacitance exists. Normally, this resistor is not required.
In some applications, the maximum programming current
required at the ICCFL pin for a maximum lamp current will be
less than the full-scale output current of the DAC, which is
50µA. The system designer can either limit the maximum
programming current through software built into the system,
or use a current splitter which shunts a percentage of the fullscale current from the ICCFL pin. A splitter circuit is illustrated
in Figure 3. A divider string is used from a reference voltage
to set up a voltage level equal to the ICCFL summing voltage,
or 465mV. The main current flowing in the divider string
should be chosen to swamp out the effects of the shunted
current into the divider string.
IOUT FULL-SCALE
50µA
R1
V(ICCFL)
465mV
V1
XI
VREF
I
R2
I1
R3
V(ICCFL)
(1 – X)I
R4
I = 50µA
0<X<1
SELECT V1 WITHIN THE DAC IOUT
COMPLIANCE RANGE
(EX. V1 = 2V FOR VCC = 3.3V OR 5V)
CHOOSE I1 >> (1 – X)I
R1 = (V1 – 0.465)/(X)(50µA)
R2 = (V1 – 0.465)/(1 – X)(50µA)
R3 = (VREF – 0.465)/I1
R4 = 0.465R3/[(1 – X) 50µAR3
+ (VREF – 0.465)]
LT1186F • F03
Figure 3
Grounded Lamp Configuration
In a grounded lamp configuration, the low voltage side of
the lamp connects directly to the LT1186F DIO pin. This
pin is the common connection between the cathode and
anode of two internal diodes. In previous grounded lamp
solutions, these diodes were discrete units and are now
integrated onto the IC, saving cost and board space.
Bidirectional lamp current flows in the DIO pin and thus,
the diodes conduct alternately on half cycles. Lamp current is controlled by monitoring one-half of the average
lamp current. The diode conducting on negative half
cycles has one-tenth of its current diverted to the CCFL pin
and nulls against the source current provided by the lamp
current programmer circuit. The compensation capacitor
on the CCFL VC pin provides stable loop compensation and
an averaging function to the rectified sinusoidal lamp
current. Therefore, input programming current relates to
one-half of average lamp current.
14
The transfer function between lamp current and input
programming current must be empirically determined and
is dependent on the particular lamp/display housing combination used. The lamp and display housing are a distributed loss structure due to parasitic lamp-to-frame capacitance. This means that the current flowing at the highvoltage side of the lamp is higher than what is flowing at
the DIO pin side of the lamp. The input programming
current is set to control lamp current at the high-voltage
side of the lamp, even though the feedback signal is the
lamp current at the bottom of the lamp. This ensures that
the lamp is not overdriven which can degrade the lamp’s
operating lifetime. Therefore, the full scale current of the
DAC does not necessarily correspond to the current required to set maximum lamp current.
Floating Lamp Configuration
In a floating lamp configuration, the lamp is fully floating
with no galvanic connection to ground. This allows the
transformer to provide symmetric differential drive to the
lamp. Balanced drive eliminates the field imbalance associated with parasitic lamp-to-frame capacitance and reduces “thermometering” (uneven lamp intensity along the
lamp length) at low lamp currents.
Carefully evaluate display designs in relation to the physical layout of the lamp, its leads and the construction of the
display housing. Parasitic capacitance from any high
voltage point to DC or AC ground creates paths for
unwanted current flow. This parasitic current flow degrades electrical efficiency and losses up to 25% have
been observed in practice. As an example, at a Royer
operating frequency of 60kHz, 1pF of stray capacitance
represents an impedance of 2.65MΩ. With an operating
lamp voltage of 400V and an operating lamp current of
6mA, the parasitic current is 150µA. This additional current must be supplied by the transformer secondary.
Layout techniques that increase parasitic capacitance
include long high voltage lamp leads, reflective metal foil
around the lamp and displays supplied in metal enclosures. Losses for a good display are under 5%, whereas,
losses for a bad display range from 5% to 25%. Lossy
displays are the primary reason to use a floating lamp
configuration. Providing symmetric, differential drive to
the lamp reduces the total parasitic loss by one-half.
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Maintaining closed-loop control of lamp current in a
floating lamp configuration necessitates deriving a feedback signal from the primary side of the Royer transformer. Previous solutions have used an external precision shunt and high-side sense amplifier configuration.
This approach has been integrated onto the LT1186F for
simplicity of design and ease of use. An internal 0.1Ω
resistor monitors the Royer converter current and connects between the input terminals of a high-side sense
amplifier. A 0 – 1 Amp Royer primary-side, center-tap
current is translated to a 0µA to 500µA sink current at the
CCFL VC pin to null against the source current provided by
the lamp current programmer circuit. The compensation
capacitor on the CCFL VC pin provides stable loop compensation and an averaging function to the error sink
current. Therefore, input programming current is related
to average Royer converter current. Floating lamp circuits
operate similarly to grounded lamp circuits except for the
derivation of the feedback signal.
The transfer function between lamp current and input
programming current must be empirically determined and
is dependent upon a myriad of factors including lamp
characteristics, display construction, transformer turns
ratio and the tuning of the Royer oscillator. Once again,
lamp current will be slightly higher at one end of the lamp
and input programming current should be set for this
higher level to ensure that the lamp is not overdriven.
The internal 0.1Ω high-side sense resistor on the LT1186F
is rated for a maximum DC current of 1A. This resistor can
be damaged by extremely high surge currents at start-up.
The Royer converter typically uses a few microfarads of
bypass capacitance at the center tap of the transformer.
This capacitor charges up when the system is first powered by the battery pack or an AC wall adapter. The amount
of current delivered at start-up can be very large if the total
impedance in this path is small and the voltage source has
high current capability. Linear Technology recommends
the use of an aluminum electrolytic for the transformer
center-tap bypass capacitor with an ESR greater than or
equal to 0.5Ω. This lowers the peak surge currents to an
acceptable level. In general, the wire and trace inductance
in this path also help reduce the di/dt of the surge current.
This issue only exists with floating lamp circuits as
grounded lamp circuits do not make use of the high-side
sense resistor.
Input Capacitor Type
Caution must be used in selecting the input capacitor type
for switching regulators. Aluminum electrolytics are electrically rugged and the lowest cost, but are physically large
to meet required ripple current ratings, and size constraints (especially height) may preclude their use. Ceramic capacitors are now available in larger values and
their high ripple current and voltage rating make them
ideal for input bypassing. Cost is fairly high and footprint
can be large.
Solid tantalum capacitors would be a good choice except
for a history of occasional failure when subjected to large
current surges during start-up. The input bypass capacitor of regulators can see these high surges when a battery
or high capacitance source is connected. Some manufacturers have developed tantalum capacitor lines specially
tested for surge capability (AVX TPS series for instance),
but even these units may fail if the input voltage surge
approaches the capacitor’s maximum voltage rating. AVX
recommends derating the capacitor voltage by 2:1 for high
surge applications.
Applications Support
Linear Technology invests an enormous amount of time,
resources and technical expertise in understanding, designing and evaluating backlight/LCD contrast solutions
for system designers. The design of an efficient and
compact LCD backlight system is a study of compromise
in a transduced electronic system. Every aspect of the
design is interrelated and any design change requires
complete re-evaluation for all other critical design parameters. Linear Technology has engineered one of the most
complete test and evaluation setups for backlight designs
and understands the issues and tradeoffs in achieving a
compact, efficient and economical customer solution.
Linear Technology welcomes the opportunity to discuss,
design, evaluate and optimize any backlight/LCD contrast
system with a customer. For further information on backlight/LCD contrast designs, consult the References.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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References
1. Williams, Jim. August 1992. Illumination Circuitry for
Liquid Crystal Displays. Linear Technology Corporation,
Application Note 49.
4. Williams, Jim. April 1995. A Precision Wideband Current Probe for LCD Backlight Measurement. Linear Technology Corporation, Design Note 101.
2. Williams, Jim. August 1993. Techniques for 92% Efficient LCD Illumination. Linear Technology Corporation,
Application Note 55.
5. LT1182/LT1183/LT1184/LT1184F Data Sheet. CCFL/
LCD Contrast Switching Regulators. April 1995. Linear
Technology Corporation.
3. Bonte, Anthony. March 1995. LT1182 Floating CCFL
with Dual Polarity Contrast. Linear Technology Corporation, Design Note 99.
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
16
0.004 – 0.010
(0.101 – 0.254)
15
14
13
12
11
10
9
0° – 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
0.050
(1.270)
TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
5
4
6
7
8
S16 0695
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1107
Micropower DC/DC Converter for LCD Contrast Control
1A, 63kHz, Hysteretic
LT1172
Current Mode Switching Regulator for CCFL or LCD Contrast Control
1.25A, 100kHz
LT1173
Micropower DC/DC Converter for LCD Contrast Control
1A, 24kHz, Hysteretic
LT1182
Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control
1.25A, 0.625A, 200kHz
LT1183
Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control
1.25A, 0.625A, 200kHz
LT1184
Current Mode Switching Regulator for CCFL Control
1.25A, 200kHz
LT1184F
Current Mode Switching Regulator for CCFL Control
1.25A, 200kHz
LT1372
Current Mode Switching Regulator for CCFL or LCD Contrast Contol
1.5A, 500kHz
16
Linear Technology Corporation
LT/GP 1096 7K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1995