SBAS263 − NOVEMBER 2003
FEATURES
D Low Glitch: 1nV-s (typ)
D Low Power: 18mW
D Unipolar or Bipolar Operation
D Settling Time: 12µs to 0.003%
D 16-Bit Linearity and Monotonicity:
D
D
D
D
D
DESCRIPTION
The DAC7654 is a 16-bit, quad voltage output,
digital-to-analog converter (DAC) with 16-bit monotonic
performance over the specified temperature range. It
accepts 24-bit serial input data, has double-buffered DAC
input logic (allowing simultaneous update of all DACs),
and provides a serial data output for daisy-chaining
multiple DACs. Programmable asynchronous reset clears
all registers to a mid-scale code of 8000h or to a zero-scale
of 0000h. The DAC7654 can operate from a single +5V
supply or from +5V and –5V supplies.
–40°C to +85°C
Programmable Reset to Mid-Scale or
Zero-Scale
Double-Buffered Data Inputs
Internal Bandgap Voltage Reference
Power-On Reset
3V to 5V Logic Interface
APPLICATIONS
D Process Control
D Closed-Loop Servo-Control
D Motor Control
D Data Acquisition Systems
D DAC-per-Pin Programmers
Low power and small size per DAC make the DAC7654
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-loop
servo-control. The DAC7654 is available in an LQFP
package and is specified for operation over the –40°C to
+85°C temperature range.
IO V D D
V DD
V SS
V CC
DAC7654
VREFH A and B
VREFL
Bandgap
Voltage Reference
VREFH
VREFL A and B
VOUTA Sense 2
SDI
Shift
Register
Input
Register A
DAC
Register A
DAC A
VOUTA Sense 1
VOUTA
OFSR1A
OFSR2A
SDO
VOUTB Sense 2
Input
Register B
DAC
Register B
DAC B
VOUTB Sense 1
VOUTB
OFSR1B
OFSR2B
VOUTC Sense 2
Input
Register C
CS
DAC
Register C
DAC C
VOUTC Sense 1
VOUTC
CLOCK
RST
RSTSEL
OFSR1C
OFSR2C
Control
Logic
LDAC
VOUTD Sense 2
Input
Register D
DAC
Register D
DAC D
VOUTD Sense 1
VOUTD
LOAD
OFSR1D
OFSR2D
V REFL
C
and D
VREFH C and D
A GN D
D GN D
This device has ESD-CDM sensitivity and special handling precautions must be taken.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright 2003, Texas Instruments Incorporated
!"# ! $ % & ' & $ (' ) '&
' $ % &'$' & * %& $ !+ & "& %& & , -)
' '&& & '&& - ' & $ %&)
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SBAS263 − NOVEMBER 2003
ORDERING INFORMATION(1)
PRODUCT
PACKAGE−LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC7654Y
LQFP−64
PM
−40°C to +85°C
DAC7654Y
DAC7654YB
LQFP−64
PM
−40°C to +85°C
DAC7654YB
DAC7654YC
LQFP−64
PM
−40°C to +85°C
DAC7654YC
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC7654YT
Tape and Reel, 250
DAC7654YR
Tape and Reel, 1500
DAC7654YBT
Tape and Reel, 250
DAC7654YBR
Tape and Reel, 1500
DAC7654YCT
Tape and Reel, 250
DAC7654YCR
Tape and Reel, 1500
(1) For the most current specification and package information, see the Package Ordering Addendum at the end of this data sheet.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
DAC7654
UNIT
−0.3 to 11
V
−0.3 to 5.5
V
Digital Input Voltage to GND
−0.3 to VDD + 0.3
V
Digital Output Voltage to GND
−0.3 to VDD + 0.3
V
IOVDD, VCC and VDD to VSS
IOVDD, VCC and VDD to GND
ESD-CDM
200
V
Maximum Junction Temperature
+150
°C
Operating Temperature Range
−40 to +85
°C
Storage Temperature Range
−65 to +125
°C
Lead Temperature (soldering, 10s)
+300
°C
(1) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond
those specified is not implied.
2
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
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SBAS263 − NOVEMBER 2003
ELECTRICAL CHARACTERISTICS: VSS = 0V
All specifications at TA = TMIN to TMAX, IOVDD = VDD = VCC = +5V, and VSS = 0V, unless otherwise noted.
DAC7654Y
PARAMETER
TEST CONDITIONS
MIN
TYP
DAC7654YB
MAX
MIN
DAC7654YC
TYP
MAX
±2
±3
MIN
TYP
MAX
UNIT
[
[
LSB
Accuracy
Linearity error
±3
Linearity match
±4
Differential linearity error
±2
Monotonicity, TMIN to TMAX
±4
±2
±3
14
±1
[
±2
15
−1
LSB
+2
16
LSB
Bit
Unipolar zero error
±1
±5
[
[
[
[
mV
Unipolar zero error drift
5
10
[
[
[
[
ppm/°C
Full-scale error
±6
±20
±4
±12.5
[
[
mV
Full-scale error drift
7
15
[
[
[
[
ppm/°C
mV
Unipolar zero matching
Channel-to-channel matching
±3
±7
±2
±5
[
[
Full-Scale matching
Channel-to-channel matching
±4
±10
±2
±8
[
[
mV
Power-supply rejection ratio (PSRR)
At full-scale
10
100
[
[
[
[
ppm/V
Analog Output
Voltage output
RL = 10kΩ
Output current
Maximum load capacitance
0
2.5
[
[
[
[
V
−1.25
+1.25
[
[
[
[
mA
No oscillation
Short-circuit current
Short-circuit duration
GND or VCC
500
[
[
pF
±20
[
[
mA
Indefinite
[
[
Dynamic Performance
Settling time
To ±0.003%, 2.5V output step
12
Channel-to-channel crosstalk
f = 10kHz
DAC glitch
7FFFh to 8000h or
8000h to 7FFFh
[
[
[
µs
[
[
2
[
[
nV-s
130
[
[
nV/√Hz
Digital feedthrough
Output noise voltage
[
15
0.5
1
[
5
[
[
LSB
[
nV-s
Digital Input
0.7 × IOVDD
VIH
[
[
0.3 × IOVDD
VIL
V
[
[
V
IIH
±10
[
[
µA
IIL
±10
[
[
µA
Digital Output
VOH
IOH = −0.8mA, IOVDD = 5V
VOL
IOL = 1.6mA, IOVDD = 5V
VOH
IOH = −0.4mA, IOVDD = 3V
VOL
IOL = 0.8mA, IOVDD = 3V
3.6
0.3
2.4
[
4.5
[
2.6
0.3
0.4
[
[
0.4
[
[
[
[
[
[
[
[
V
[
[
V
V
[
[
V
Power Supply
VDD
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
IOVDD
+2.7
+5.0
+5.25
[
[
[
[
[
[
V
VCC
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
VSS
0
0
0
[
[
[
[
[
[
V
ICC
3.5
5
[
[
[
[
mA
IDD
50
[
[
I(IOVDD)
50
[
[
µA
Power
18
[
mW
[
25
[
µA
Temperature Range
Specified performance
−40
+85
[
[
[
[
°C
[ specifications same as the grade to the left
3
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SBAS263 − NOVEMBER 2003
ELECTRICAL CHARACTERISTICS: VSS = −5V
All specifications at TA = TMIN to TMAX, IOVDD = VDD = VCC = +5V, and VSS = −5V, unless otherwise noted.
DAC7654Y
PARAMETER
TEST CONDITIONS
MIN
TYP
DAC7654YB
MAX
MIN
DAC7654YC
TYP
MAX
±2
±3
MIN
TYP
MAX
UNIT
[
[
LSB
Accuracy
Linearity error
±3
Linearity match
±4
Differential linearity error
±2
±3
±1
±5
Monotonicity, TMIN to TMAX
±4
±2
14
Bipolar zero error
[
±1
±2
[
[
15
−1
LSB
+2
LSB
[
[
mV
ppm/°C
16
Bit
Bipolar zero error drift
5
10
[
[
[
[
Full-scale error
±6
±20
±4
±12.5
[
[
mV
Full-scale error drift
7
15
[
[
[
[
ppm/°C
mV
Bipolar zero matching
Channel-to-channel matching
±3
±7
±2
±5
[
[
Full-Scale matching
Channel-to-channel matching
±4
±10
±2
±8
[
[
mV
Power-supply rejection ratio (PSRR)
At full-scale
10
100
[
[
[
[
ppm/V
Analog Output
Voltage output
RL = 10kΩ
Output current
Maximum load capacitance
−2.5
+2.5
[
[
[
[
V
−1.25
+1.25
[
[
[
[
mA
No oscillation
Short-circuit current
Short-circuit duration
GND or VCC or VSS
500
[
[
pF
−15, +30
[
[
mA
Indefinite
[
[
Dynamic Performance
Settling time
To ±0.003%, 5V output step
12
Channel-to-channel crosstalk
Digital feedthrough
Output noise voltage
f = 10kHz
DAC glitch
7FFFh to 8000h or
8000h to 7FFFh
[
15
[
[
[
µs
0.5
[
[
2
[
[
nV-s
200
[
[
nV/√Hz
2
[
7
[
[
LSB
[
nV-s
Digital Input
0.7 × IOVDD
VIH
[
[
0.3 × IOVDD
V
[
[
V
IIH
±10
[
[
µA
IIL
±10
[
[
µA
VIL
Digital Output
VOH
IOH = −0.8mA, IOVDD = 5V
VOL
IOL = 1.6mA, IOVDD = 5V
VOH
IOH = −0.4mA, IOVDD = 3V
VOL
IOL = 0.8mA, IOVDD = 3V
3.6
0.3
2.4
[
4.5
[
0.4
[
2.6
0.3
0.4
[
[
[
[
[
[
[
[
[
V
[
[
V
V
[
[
V
Power Supply
VDD
IOVDD
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
+2.7
+5.0
+5.25
[
[
[
[
[
[
V
VCC
VSS
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
−5.25
−5.0
−4.75
[
[
[
[
[
[
V
4
5.5
[
[
[
[
mA
ICC
IDD
I(IOVDD)
ISS
−3.5
Power
50
[
[
50
[
[
µA
[
mA
[
mW
[
−2.0
30
[
[
45
[
[
µA
Temperature Range
Specified performance
[ specifications same as the grade to the left
4
−40
+85
[
[
[
[
°C
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SBAS263 − NOVEMBER 2003
PIN ASSIGNMENTS
NC
NC
NC
NC
NC
NC
NC
NC
NC
44
NC
45
NC
46
VOUTD Sense 2
47
VOUTD Sense 1
NC
48
VOUTD
NC
LQFP PACKAGE
(TOP VIEW)
43
42
41
40
39
38
37
36
35
34
33
Offset D Range 1 49
32 NC
Offset D Range 2 50
31 NC
Offset C Range 2 51
30 NC
Offset C Range 1 52
29 VDD
VOUTC Sense 2 53
28 DGND
VOUTC Sense 1 54
27 RSTSEL
VOUTC 55
26 RST
Reference GND 56
25 LDAC
DAC7654
Reference GND 57
24 LOAD
VOUTB 58
23 SDI
VOUTB Sense 1 59
22 CLK
VOUTB Sense 2 60
21 CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AGND
NC
NC
NC
NC
NC
NC
NC
NC
17 DGND
VOUTA Sense 2
Offset A Range 1 64
VOUTA Sense 1
18 VDD
VOUTA
Offset A Range 2 63
VCC
19 IOVDD
VSS
Offset B Range 2 62
NC
20 SDO
NC
Offset B Range 1 61
5
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SBAS263 − NOVEMBER 2003
Terminal Functions
PIN
NAME
1
NC
2
NC
3
VSS
VCC
4
5
6
7
PIN
NAME
No Connection
36
NC
No connection
No Connection
37
NC
No connection
Analog –5V power supply or 0V single supply
38
NC
No connection
Analog +5V power supply
39
NC
No connection
VOUTA
VOUTA
Sense 1
DAC A output voltage
40
NC
No connection
Connect to VOUTA for unipolar mode
41
NC
No connection
42
NC
No connection
VOUTA
Sense 2
Connect to VOUTA for bipolar mode
43
NC
No connection
44
VOUTD
Sense 2
Connect to VOUTD for bipolar mode
45
VOUTD
Sense 1
Connect to VOUTD for unipolar mode
8
AGND
Analog ground
9
NC
No connection
10
NC
No connection
DESCRIPTION
11
NC
No connection
46
NC
No connection
47
VOUTD
NC
DAC D output
12
13
NC
No connection
48
NC
No connection
14
NC
No connection
49
15
NC
No connection
Offset D
Range 1
Connect to Offset D Range 2 for unipolar
mode
16
NC
No connection
50
17
DGND
Digital ground
Offset D
Range 2
Connect to Offset D Range 1 for unipolar
mode
18
Digital +5V power supply
51
19
VDD
IOVDD
Offset C
Range 2
Connect to Offset C Range 1 for unipolar
mode
20
SDO
52
Offset C
Range 1
Connect to Offset C Range 2 for unipolar
mode
53
VOUTC
Sense 2
Connect to VOUTC for bipolar mode
54
VOUTC
Sense 1
Connect to VOUTC for unipolar mode
Interface power supply
Serial data output
No connection
21
CS
Chip select, active low
22
CLK
Data clock input
23
SDI
Serial data input
24
LOAD
DAC input register load control, active low
25
LDAC
DAC register load control, rising edge triggered
55
RST
Reset, rising edge triggered. Depending on
the state of RSTSEL, the DAC registers are
set to either mid-scale or zero.
56
VOUTC
REF GND
DAC C output
26
57
REF GND
Reference ground
58
VOUTB
VOUTB
Sense 1
DAC B output
60
VOUTB
Sense 2
Connect to VOUTB for bipolar mode
61
Offset B
Range 1
Connect to Offset B Range 2 for unipolar
mode
62
Offset B
Range 2
Connect to Offset B Range 1 for unipolar
mode
63
Offset A
Range 2
Connect to Offset A Range 1 for unipolar
mode
64
Offset A
Range 1
Connect to Offset A Range 2 for unipolar
mode
27
6
DESCRIPTION
RSTSEL
Reset select. Determines the action of RST.
If high, an RST command sets the DAC
registers to mid-scale (8000h). If low, an RST
command sets the DAC registers to zero
(0000h).
28
DGND
29
30
VDD
NC
Digital ground
31
NC
No connection
32
NC
No connection
33
NC
No connection
34
NC
No connection
35
NC
No connection
59
Digital +5V power supply
No connection
Reference ground
Connect to VOUTB for unipolar mode
www.ti.com
SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = 0V
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
+255C
DLE (LSB)
8000h A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h
6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 1
Figure 2
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25_ C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25_ C)
0000h 2000h 4000h
6000h
8000h A000h C000h E000h FFFFh
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
6000h
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25_ C)
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 3
Figure 4
7
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = 0V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
+855C
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h
Figure 5
Figure 6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85_ C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85_ C)
0000h 2000h 4000h
8
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
6000h 8000h A000h C000h E000h FFFFh
Digital Input Code
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
DLE (LSB)
Digital Input Code
6000h 8000h A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
8000h
A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 7
Figure 8
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = 0V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
−405C
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, −40_C)
6000h 8000h A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
8000h
A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 9
Figure 10
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, −40_ C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, −40_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
DLE (LSB)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, −40_C)
6000h 8000h A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 11
Figure 12
9
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = 0V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT vs DIGITAL INPUT CODE
5.0
5.0
All DACs at Midscale
No Load
4.5
4.0
4.0
ICC
3.5
3.5
3.0
ICC (mA)
ICC (mA)
All DACs
No Load
4.5
2.5
2.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
ICC
3.0
0
−40
−15
10
35
60
0000h
85
8000h
A000h C000h E000h FFFFh
Digital Input Code
Figure 13
Figure 14
ZERO−SCALE ERROR vs TEMPERATURE
POSITIVE FULL−SCALE ERROR vs TEMPERATURE
10
10
(Code 0000h)
8
Positive Full−Scale Error (mV)
8
6
Zero−Scale Error (mV)
2000h 4000h 6000h
Temperature (_C)
4
DAC B
DAC C
2
0
−2
DAC A
−4
DAC D
−6
−8
−10
−40
(Code FFFFh)
6
DAC D
4
DAC B
2
0
−2
DAC C
−4
DAC A
−6
−8
−10
−15
10
35
60
−40
85
−15
10
35
Temperature (_C)
Temperature (_ C)
Figure 15
Figure 16
BROADBAND NOISE
(Code = 8000h, BW = 10kHz)
60
85
OUTPUT NOISE VOLTAGE vs FREQUENCY
Noise (nV√Hz)
Noise Voltage (100µV/div)
1000
100
10
Time (10ms/div)
10
100
1k
10k
Frequency (Hz)
Figure 17
10
Figure 18
100k
1M
www.ti.com
SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = 0V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
SETTLING TIME
(0V to +2.5V)
SETTLING TIME
(+2.5V to 39mV)
Small Signal: 100µV/div
Output Voltage
Output Voltage
Large Signal: 1.0V/div
Large Signal: 1.0V/div
Small Signal: 100µV/div
Figure 19
Figure 20
MIDSCALE GLITCH PERFORMANCE
CODE 7FFFh to 8000h
MIDSCALE GLITCH PERFORMANCE
CODE 8000h to 7FFFh
Unfiltered DAC Output
DAC Output after
2K, 470pF Low−Pass Filter
Output Voltage (10mV/div)
Time (5µs/div)
Output Voltage (10mV/div)
Time (5µs/div)
Unfiltered DAC Output
DAC Output After
2K, 470pF Low−Pass Filter
Time (0.5µs/div)
Time (0.5µs/div)
Figure 21
Figure 22
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32750 to 32850
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32850 to 32750
DAC Output After
2K, 470pF Low−Pass Filter
100
Codes
Output Voltage (20mV/div)
Output Voltage (20mV/div)
Unfiltered DAC Output
DAC Output After
2K, 470pF Low−Pass Filter
Unfiltered DAC Output
Time (1.0µs/div)
Time (1.0µs/div)
Figure 23
Figure 24
11
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = 0V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
IOVDD SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS
VOUT vs RLOAD
5.0
0.8
4.5
Logic Supply Current (mA)
4.0
VOUT (V)
3.5
3.0
Source
2.5
2.0
1.5
1.0
Sink
0
0.1
1
RLOAD (kΩ)
Figure 25
12
0.6
0.5
0.4
0.3
0.2
0.1
0.5
0.01
Typical of One
Digital Input
IOVDD = 5V
0.7
10
0
100
0
1
2
3
4
Logic Input Level for Digital Inputs (V)
Figure 26
5
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = −5V
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted.
+255C
8000h
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
A000h C000h E000h FFFFh
0000h 2000h 4000h 6000h
8000h A000h C000h E000h FFFFh
Digital Input Code
Figure 27
Figure 28
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25_ C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
8000h A000h C000h E000h FFFFh
LE (LSB)
Digital Input Code
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
DLE (LSB)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 29
Figure 30
13
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = −5V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted.
+855C
14
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85_ C)
8000h A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h 6000h
8000h
A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 31
Figure 32
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85_ C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85_ C)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h
LE (LSB)
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
DLE (LSB)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85_ C)
6000h
8000h A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
2.0
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
−2.0
0000h 2000h 4000h
6000h
8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 33
Figure 34
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = −5V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted.
−405C
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
0000h 2000h 4000h 6000h
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, −40_C)
8000h A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
0000h 2000h 4000h 6000h
8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 35
Figure 36
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, −40_C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, −40_C)
LE (LSB)
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
0000h 2000h 4000h 6000h
DLE (LSB)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, −40_C)
8000h
A000h C000h E000h FFFFh
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
2.0
1.5
1.0
0.5
0
− 0.5
− 1.0
− 1.5
− 2.0
0000h 2000h 4000h 6000h
8000h A000h C000h E000h FFFFh
Digital Input Code
Digital Input Code
Figure 37
Figure 38
15
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = −5V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT vs DIGITAL INPUT CODE
5
4
3
3
2
2
1
1
0
−1
ISS
−2
−5
0
−1
ISS
−2
−3
−4
ICC
4
ICC (mA)
ICC (mA)
5
ICC
−3
All DACs at Midscale
No Load
All DACs
No Load
−4
−5
−40
−15
10
35
60
85
0000h
A000h C000h E000h FFFFh
Figure 39
Figure 40
BIPLOAR ZERO ERROR vs TEMPERATURE
POSITIVE FULL−SCALE ERROR vs TEMPERATURE
10
(Code 8000h)
6
4
DAC C
DAC D
2
0
−2
−4
DAC A
−6
DAC B
−8
−10
−40
(Code FFFFh)
8
Positive Full−Scale Error (mV)
8
6
DAC C
4
DAC D
2
0
−2
DAC B
−4
DAC A
−6
−8
−10
−15
10
35
60
−40
85
−15
10
35
Temperature (_C)
Temperature (_C)
Figure 41
Figure 42
NEGATIVE FULL−SCALE ERROR vs TEMPERATURE
Negative Full−Scale Error (mV)
10
8
(Code 0000h)
6
DAC B
4
2
DAC A
0
−2
DAC C
−4
−6
DAC D
−8
−10
−40
−15
10
35
Temperature (_C)
Figure 43
16
8000h
Digital Input Code
10
Bipolar Zero Error (mV)
2000h 4000h 6000h
Temperature (_C)
60
85
60
85
www.ti.com
SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = −5V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted.
OUTPUT NOISE VOLTAGE vs FREQUENCY
1000
Noise (nV√Hz)
Noise Voltage (100µV/div)
BROADBAND NOISE
(Code = 8000h, BW = 10kHz)
100
10
10
Time (10ms/div)
100
1k
10k
100k
1M
Frequency (Hz)
Figure 44
Figure 45
SETTLING TIME
(−2.5V to +2.5V)
SETTLING TIME
(+2.5V to −2.5V)
Small Signal: 100µV/div
Output Voltage
Output Voltage
Large Signal: 1.0V/div
Small Signal: 100µV/div
Time (5µs/div)
Time (5µs/div)
Figure 46
Figure 47
MIDSCALE GLITCH PERFORMANCE
CODE 7FFFh to 8000h
MIDSCALE GLITCH PERFORMANCE
CODE 8000h to 7FFFh
Unfiltered DAC Output
DAC Output after
2K, 470pF Low−Pass Filter
Output Voltage (10mV/div)
Output Voltage (10mV/div)
Large Signal: 1.0V/div
Unfiltered DAC Output
DAC Output After
2K, 470pF Low−Pass Filter
Time (0.5µs/div)
Time (0.5µs/div)
Figure 48
Figure 49
17
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SBAS263 − NOVEMBER 2003
TYPICAL CHARACTERISTICS: VSS = −5V (continued)
All specifications at TA = 25°C, IOVDD = VDD = VCC = +5V, VSS = −5V, representative unit, unless otherwise noted.
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32750 to 32850
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32850 to 32750
Output Voltage (20mV/div)
Output Voltage (20mV/div)
Unfiltered DAC Output
DAC Output After
2K, 470pF Low−Pass Filter
100
Codes
DAC Output After
2K, 470pF Low−Pass Filter
Unfiltered DAC Output
Time (1.0µs/div)
Time (1.0µs/div)
Figure 50
Figure 51
VOUT vs RLOAD
5
4
Source
3
VOUT (V)
2
1
0
−1
Sink
−2
−3
−4
−5
0.01
0.1
1
RLOAD (kΩ)
Figure 52
18
10
100
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SBAS263 − NOVEMBER 2003
THEORY OF OPERATION
The DAC7654 is a quad voltage output, 16-bit DAC. The
architecture is an R−2R ladder configuration with the three
most significant bits (MSBs) segmented, followed by an
operational amplifier that serves as a buffer. Each DAC
has its own R−2R ladder network, segmented MSBs, and
output op amp, as shown in Figure 53. The minimum
voltage output (zero-scale) and maximum voltage output
(full-scale) are set by the internal voltage references and
the resistors associated with the output operational
amplifier.
The digital input is a 24-bit serial word that contains a 2-bit
address code for selecting one of four DACs, a quick load
bit, five unused bits, and the 16-bit DAC code (MSB first).
The converters can be powered from either a single +5V
supply or a dual ±5V supply. The device offers a reset
function that immediately sets all DAC output voltages and
DAC registers to mid-scale (code 8000h) or to zero-scale
(code 0000h). See Figure 54 and Figure 55 for basic
single- and dual-supply operation of the DAC7654.
VOUTS1
13KΩ
13KΩ
VOUTS2
100Ω
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
OFSR2
13KΩ
11KΩ
OFSR1
12KΩ
VREFH
VREFL
Figure 53. DAC7654 Architecture
19
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SBAS263 − NOVEMBER 2003
0V to +2.5V
NC
0V to +2.5V
43
42
41
40
39
38
37
36
35
34
33
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
44
NC
45
V O UT D Sense 2
NC
NC NC NC NC NC NC NC NC NC NC NC NC
46
V O UT D Sense 1
47
VO U T D
48
NC
NC NC
NC
32
NC
NC
31
NC
NC
30
NC
V DD
29
V O U T C Sense 2
DGND
28
V O U T C Sense 1
RSTSEL
27
RST
26
Reset DAC Register
LDAC
25
Load DAC Registers
49
Offset D Range 1
50
Offset D Range 2
51
Offset C Range 2
52
Offset C Range 1
53
54
55
VO U T C
DAC7654
Single Supply
56
Reference GND
57
Reference GND
LOAD
24
Load
58
VO U T B
SDI
23
Serial Data In
59
V O U T B Sense 1
CLK
22
Clock
60
V O U T B Sense 2
CS
21
Chip Select
61
Offset B Range 1
SDO
20
Serial Data Out
62
Offset B Range 2
IOV DD
19
NC
NC
NC
8
NC
7
NC
NC
6
17
NC
5
18
NC
4
V DD
DGND
NC
3
AGND
2
NC NC
V O U T A Sense 2
1
V O U T A Sense 1
Offset A Range 1
VO U T A
Offset A Range 2
64
VS S
63
NC
NC
NC
0V to +2.5V
VC C
NC = No Connection
9
10
11
12
13
14
15
16
NC NC NC NC NC NC NC NC
0V to +2.5V
+5V
+
1µ F
0.1µF
Figure 54. Basic Single-Supply Operation of the DAC7654
20
+3V to +5V
0.1µF
+
1µF
www.ti.com
SBAS263 − NOVEMBER 2003
−2.5V to +2.5V
−2.5V to +2.5V
NC 49
Offset D Range 1
NC 50
Offset D Range 2
NC 51
NC 52
43
42
41
40
39
38
37
36
35
34
33
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC NC NC NC NC NC NC NC NC NC
44
NC
45
V O UT D Sense 2
NC
NC
46
V O U TD
47
V O UT D Sense 1
48
NC
NC NC
NC
32
NC
NC
31
NC
Offset C Range 2
NC
30
NC
Offset C Range 1
VD D
29
53
V OU T C Sense 2
DGND
28
NC 54
V OU T C Sense 1
RSTSEL
27
RST
26
Reset DAC Register
LDAC
25
Load DAC Registers
55
V OU T C
DAC7654
Dual Supply
56
Reference GND
57
Reference GND
LOAD
24
Load
58
V OU T B
SDI
23
Serial Data In
NC 59
V OU T B Sense 1
CLK
22
Clock
60
V OU T B Sense 2
NC = No Connection
20
Serial Data Out
NC 62
Offset B Range 2
IOV D D
19
8
NC
7
NC
6
NC
NC
5
NC
4
NC
3
17
NC
2
18
NC
VO U T A
1
NC NC
VD D
DGND
NC
VC C
Offset A Range 1
VS S
Offset A Range 2
NC 64
NC
NC 63
AGND
Chip Select
SDO
VO U T A Sense 2
21
Offset B Range 1
VO U T A Sense 1
CS
NC 61
NC
−2.5V to +2.5V
9
10
11
12
13
14
15
16
+3V to +5V
0.1µF
+
1µF
NC NC NC NC NC NC NC NC
−5V
+
1µF
0.1µ F
−2.5V to +2.5V
+5V
+
1µF
0.1µF
Figure 55. Basic Dual-Supply Operation of the DAC7654
21
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SBAS263 − NOVEMBER 2003
ANALOG OUTPUTS
The DAC7654 offers a force and sense output
configuration for the high open-loop gain output amplifier.
This feature allows the loop around the output amplifier to
be closed at the load (as shown in Figure 56), thus
ensuring an accurate output voltage.
When VSS = –5V (dual-supply operation), the output
amplifier can swing to within 2.25V of the supply rails over
a range of –40°C to +85°C. When VSS = 0V (single-supply
operation), and with RLOAD also connected to ground, the
output can swing to within 5mV of ground. Care must be
taken when measuring the zero-scale error when
VSS = 0V. Since the output voltage cannot swing below
ground, the output voltage may not change for the first few
digital input codes (0000h, 0001h, 0002h, etc.) if the output
amplifier has a negative offset.
DIGITAL INTERFACE
Table 1 shows the basic control logic for the DAC7654.
The interface consists of a signal data clock (CLK) input,
serial data in (SDI), DAC input register load control signal
(LOAD), and DAC register load control signal (LDAC). In
addition, a chip select (CS) input is available to enable
serial communication when there are multiple serial
devices. An asynchronous reset (RST) input, by the rising
edge, is provided to simplify startup conditions, periodic
resets, or emergency resets to a known state, depending
on the status of the reset select (RSTSEL) signal.
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance are
very important. A 16-bit converter with a 2.5V full-scale
range has a 1LSB value of 38µV. With a load current of
1mA, series wiring and connector resistance of only 40mΩ
(RW2) will cause a voltage drop of 40µV, as shown in
Figure 56. To understand what this means in terms of
system layout, the resistivity of a typical 1-ounce
copper-clad printed circuit board is 1/2 mΩ per square. For
a 1mA load, a 0.01-inch-wide printed circuit conductor 0.6
inches long will result in a voltage drop of 30µV.
RW1
VOUTA Sense1
6
VOUTA
5
AGND
8
DAC7654
RW2
VOUT
RW1
VOUTB Sense1
59
VOUTB
58
RW2
VOUT
Figure 56. Analog Output Closed-Loop Configuration (1/2 DAC7654). RW represents wiring resistances.
Table 1. DAC7654 Logic Truth Table
A1
22
A0
CS
RST
RSTSEL
LDAC
LOAD
INPUT REGISTER
DAC REGISTER
MODE
DAC
L
L
L
H
X
X
L
Write
Hold
Write input
A
L
H
L
H
X
X
L
Write
Hold
Write input
B
H
L
L
H
X
X
L
Write
Hold
Write input
C
H
H
L
H
X
X
L
Write
Hold
Write input
D
X
X
H
H
X
↑
H
Hold
Write
Update
All
X
X
H
H
X
H
H
Hold
Hold
Hold
All
X
X
X
↑
L
X
X
Reset to zero
Reset to zero
Reset to zero
All
X
X
X
↑
H
X
X
Reset to mid-scale
Reset to mid-scale
Reset to mid-scale
All
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SBAS263 − NOVEMBER 2003
The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Table 3; also see Figure 58,
page 25). The first two bits select the input register that will
be updated when LOAD goes low. The third bit is a Quick
Load bit; if high, the code in the shift register is loaded into
all of the DAC input registers when the LOAD signal goes
low. If the Quick Load bit is low, the content of shift register
is loaded only to the DAC input register that is addressed.
The Quick Load bit is followed by five unused bits. The last
16 bits (MSB first) are the DAC code.
The internal DAC register is edge triggered and not level
triggered. When the LDAC signal is transitioned from low
to high, the digital word currently in the DAC input register
is latched. The first set of registers (the DAC input
registers) are level triggered via the LOAD signal. This
double-buffered architecture has been designed so that
new data can be entered for each DAC without disturbing
the analog outputs. When the new data has been entered
into the device, all of the DAC outputs can be updated
simultaneously by the rising edge of LDAC. Additionally, it
allows writing to the DAC input registers at any point,
which permits the DAC output voltages to be
synchronously changed via a trigger signal (LDAC).
CS and CLK are used, CS should rise only when CLK is high.
If not, then either CS or CLK can be used to operate the shift
register. Table 2 shows more information.
Table 2. Serial Shift Register Truth Table
CS(1)
CLK(1)
LOAD
RST
SERIAL SHIFT REGISTER
H(2)
X(2)
H
H
No change
L(2)
L
H
H
No change
L
↑(2)
H
H
Advanced one bit
↑
L
H
H
Advanced one bit
H(3)
X
L(4)
H
No change
H
↑(5)
No change
H(3)
X
(1) CS and CLK are interchangeable.
(2) H = logic high. X = don’t care. L = logic low. ↑ = positive logic
transition.
(3) A high value is suggested in order to avoid a false clock from
advancing and changing the shift register.
(4) If data are clocked into the serial register while LOAD is low, the
selected DAC register will change as the shift register bits flow
through A1 and A0. This will corrupt the data in each DAC register
that has been erroneously selected.
(5) Rising edge of RST causes no change in the contents of the serial
shift register.
3V TO 5V LOGIC INTERFACE
GLITCH SUPPRESSION CIRCUIT
All of the digital input and output pins are compatible with
any logic supply voltage between 3V and 5V. Connect the
interface logic supply voltage to the IOVDD pin. Note that
the internal digital logic operates from 5V, so the VDD pin
must connect to a 5V supply.
CS AND CLK INPUTS
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. However, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is low when CS rises, the OR gate will
provide a rising edge to the shift register, shifting the internal
data by one additional bit. The result will be incorrect data and
the possible selection of the wrong input register(s). If both
Figure 21, Figure 22, Figure 48, and Figure 49 show the
typical DAC output when switching between codes 7FFFh
and 8000h. For R-2R ladder DACs, this is potentially the
worst-case glitch condition, since every switch in the DAC
changes state. To minimize the glitch energy at this and
other code pairs with possible high-glitch outputs, an
internal track-and-hold circuit is used to maintain the DAC
ouput voltage at a nearly constant level during the internal
switching interval. This track-and-hold circuit is activated
only when the transition is at, or close to, one of the code
pairs with the high-glitch possibility.
It is advisable to avoid digital transitions within 1µs of the
rising edge of the LDAC signal. These signals can affect
the charge on the track-and-hold capacitor, thus
increasing the glitch energy.
Table 3. 24-Bit Data and Command Word
B23
B22
B21
A1
A0
Quick
Load
B20 B19
X
X
B18 B17
X
X
B16 B15
X
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
D15 D14 D13 D12 D11 D10 D9
B14 B13
B12
B11
B10
D8
D7
D6
D5
D4
D3
D2
D1
D0
23
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SBAS263 − NOVEMBER 2003
SERIAL DATA OUTPUT
DIGITAL INPUT CODING
The serial-data output (SDO) is the internal shift register
output. For the DAC7654, the SDO is a driven output and
does not require an external pull-up. Any number of
DAC7654s can be daisy-chained by connecting the SDO
pin of one device to the SDI pin of the following device in
the chain, as shown in Figure 57.
The DAC7654 input data is in straight binary format. The
output voltage for single-supply operation is given by
Equation 1:
V OUT + 2.5 N
65, 536
(1)
where N is the digital input code.
DIGITAL TIMING
Figure 58 and Table 4 provide detailed timing for the digital
interface of the DAC7654.
This equation does not include the effects of offset
(zero-scale) or gain (full-scale) errors.
The output for the dual supply operation is given by
Equation 2:
V OUT + 5 N * 2.5
65, 536
DAC7654
SCK
CLK
DIN
SDI
CS
CS
DAC7654
CLK
SDO
SDI
CS
DAC7654
CLK
SDO
SDI
SDO
CS
Figure 57. Daisy-Chaining the DAC7654
24
(2)
To
Other
Serial
Devices
www.ti.com
SBAS263 − NOVEMBER 2003
(LSB)
(MSB)
SDI
A0
A1
QUICK
LOAD
X
X
X
X
X
D15
D1
D0
CLK
tcss
tCSH
tLD1
tLD2
CS
tLDDD
LOAD
tLDRW
LDAC
t DS
tDH
SDI
tCL
tCH
CLK
t LDDL
t LDDH
LDAC
tS
tS
±1 LSB
ERROR BAND
VOUT
tRSTL
±1 LSB
ERROR BAND
tRSTH
RST
t RSSH
tRSSS
RSTSEL
Figure 58. Digital Input and Output Timing
Table 4. Timing Specifications for Figure 58
SYMBOL
DESCRIPTION
MIN
UNITS
tDS
tDH
tCH
Data valid to CLK rising
10
ns
Data held valid after CLK rises
20
ns
CLK high
25
ns
tCL
CLK low
25
ns
tCSS
tCSH
CS low to CLK rising
15
ns
CLK high to CS rising
0
ns
tLD1
tLD2
LOAD high to CLK rising
10
ns
CLK rising to LOAD low
30
ns
tLDRW
tLDDL
LOAD low time
30
ns
LDAC low time
100
ns
tLDDH
tRSSS
LDAC high time
150
ns
RSTSEL valid to RST high
0
ns
tRSSH
tRSTL
RST high to RSTSEL not valid
100
ns
RST low time
10
ns
tRSTH
tS
RST high time
10
ns
Settling time
10
µs
25
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC7654YBR
ACTIVE
LQFP
PM
64
1500
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YBT
ACTIVE
LQFP
PM
64
250
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YCR
ACTIVE
LQFP
PM
64
1500
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YCT
ACTIVE
LQFP
PM
64
250
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YR
ACTIVE
LQFP
PM
64
1500
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YT
ACTIVE
LQFP
PM
64
250
TBD
CU SNPB
Level-3-240C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
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• DALLAS, TEXAS 75265
1
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