H7N1005LD, H7N1005LS, H7N1005LM Silicon N Channel MOS FET High Speed Power Switching REJ03G0391-0200 Rev.2.00 Oct 16, 2006 Features • Low on-resistance RDS (on) = 85 mΩ typ. • Low drive current • Capable of 4.5 V gate drive Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) 4 4 1 1 2 1. Gate 2. Drain 3. Source 4. Drain 2 3 3 H7N1005LD H7N1005LS RENESAS Package code: PRSS0004AE-C (Package name: LDPAK (S)-(2) ) D 4 G 1 2 3 H7N1005LM Rev.2.00 Oct 16, 2006 page 1 of 8 S H7N1005LD, H7N1005LS, H7N1005LM Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Symbol VDSS VGSS ID Value 100 ±20 15 30 30 8 6.4 30 150 –55 to +150 ID (pulse) Note 1 IDR IAP Note 3 EAR Note 3 Pch Note 2 Tch Tstg Unit V V A A A A mJ W °C °C Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body to drain diode forward voltage Body to drain diode reverse recovery time Note: 4. Pulse test Rev.2.00 Oct 16, 2006 page 2 of 8 Symbol V (BR) DSS V (BR) GSS IGSS IDSS VGS (off) RDS (on) |yfs| Ciss Coss Crss Qg Qgs Qgd td (on) tr td (off) tf VDF trr Min 100 ±20 — — 1.5 — — 6.5 — — — — — — — — — — — — Typ — — — — — 85 105 11 830 90 55 15 3 4 15 85 42 6.8 0.93 41 Max — — ±10 10 2.5 110 155 — — — — — — — — — — — — — Unit V V µA µA V mΩ mΩ S pF pF pF nC nC nC ns ns ns ns V ns Test Conditions ID = 10 mA, VGS = 0 IG = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 VDS = 100 V, VGS = 0 ID = 1 mA, VDS = 10 V Note 4 ID = 7.5 A, VGS = 10 V Note 4 ID = 7.5 A, VGS = 4.5 V Note 4 ID = 7.5 A, VGS = 10 V Note 4 VDS = 10 V VGS = 0 f = 1 MHz VDD = 50 V VGS = 10 V ID = 15 A VGS = 10 V, ID = 7.5 A RL = 4 Ω Rg = 4.7 Ω IF = 15 A, VGS = 0 IF = 15 A, VGS = 0 diF/dt = 100 A/µs H7N1005LD, H7N1005LS, H7N1005LM Main Characteristics Power vs. Temperature Derating Maximum Safe Operation Area (A) 100 1 s 10 30 20 10 0 0 50 100 150 Case Temperature 200 Tc (°C) µs µs 5V 16 10 30 100 300 VDS (V) Typical Transfer Characteristics 20 Pulse Test 6V 3 Drain to Source Voltage 4.5 V VDS = 10 V Pulse Test ID (A) 10 V 8V ID (A) 0 PW = 10 ms Operation in (1shot) this area is 0.1 limited by RDS (on) Ta = 25°C 0.01 0.1 0.3 1 15 4V 12 8 3.5 V 4 Drain Current 20 10 Tc = 75°C 5 25°C VGS = 3 V –25°C 0 0 0 2 4 6 Drain to Source Voltage 8 10 0 VDS (V) Pulse Test 1.5 1.0 ID = 10 A 5A 0.5 2A 0 0 4 8 12 Gate to Source Voltage Rev.2.00 Oct 16, 2006 page 3 of 8 16 20 VGS (V) 2 3 4 5 6 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Drain to Source On State Resistance RDS(on) (mΩ) 2.0 1 Gate to Source Voltage Drain to Source Saturation Voltage vs. Gate to Source Voltage Drain to Source Saturation Voltage VDS(on) (V) 10 10 DC Operation (Tc = 25°C) 1 Typical Output Characteristics Drain Current m ID 40 Drain Current Channel Dissipation Pch (W) 50 1000 Pulse Test 500 200 VGS = 4.5 V 100 10 V 50 20 10 1 2 5 10 Drain Current 20 50 ID (A) 100 Static Drain to Source on State Resistance vs. Temperature 500 Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS(on) (mΩ) H7N1005LD, H7N1005LS, H7N1005LM Pulse Test 400 300 10 A ID = 2 A, 5 A 200 VGS = 4.5 V 100 2 A, 5 A 10 V 0 –25 0 25 50 75 10 A 100 125 150 Case Temperature Tc 100 30 10 Tc = –25°C 3 75°C 1 0.3 25°C 0.1 0.03 VDS = 10 V Pulse Test 0.01 0.01 0.03 0.1 0.3 Capacitance C (pF) Reverse Recovery Time trr (ns) 10000 50 20 VGS = 0 f = 1 MHz 3000 Ciss 1000 300 100 Coss Crss 30 di / dt = 100 A / µs VGS = 0, Ta = 25°C 10 0.5 1 2 5 Reverse Drain Current 10 20 0 10 12 80 8 40 4 VDD = 100 V 50 V 25 V 0 0 0 4 8 Gate Charge Rev.2.00 Oct 16, 2006 page 4 of 8 12 16 Qg (nc) 40 50 20 1000 Switching Time t (ns) VDD = 25 V 50 V 100 V VGS (V) 16 VGS Gate to Source Voltage (V) VDS Drain to Source Voltage 20 VDS 30 Switching Characteristics ID = 12 A 120 20 Drain to Source Voltage VDS (V) IDR (A) Dynamic Input Characteristics 160 10 30 100 Typical Capacitance vs. Drain to Source Voltage 100 200 3 Drain Current ID (A) (°C) Body to Drain Diode Reverse Recovery Time 10 0.1 0.2 1 VGS = 10 V, VDD = 30 V PW = 5 µs, duty ≤ 1 % 300 Rg = 4.7 Ω 100 td(off) 30 td(on) 10 3 1 0.1 tf tr 0.3 1 3 Drain Current 10 30 ID (A) 100 H7N1005LD, H7N1005LS, H7N1005LM Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) Reverse Drain Current IDR (A) Reverse Drain Current vs. Source to Drain Voltage 20 10 V 16 12 8 VGS = 0, –5 V 4 5V Pulse Test 0 0 0.4 0.8 1.2 1.6 Source to Drain Voltage 2.0 8 IAP = 8 A VDD = 50 V duty < 0.1 % Rg ≥ 50 Ω 7 6 5 4 3 2 1 0 25 VSD (V) 50 75 100 125 150 Channel Temperature Tch (°C) Normalized Transient Thermal Impedance γ s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C D=1 1 0.5 0.2 0.3 0.1 0.05 θch – c (t) = γ s (t) • θch – c 0.1 0.0 .01 0 0.03 1s t ho pu θch – c = 4.17°C/W, Tc = 25°C 2 PDM lse D= PW T PW T 0.01 10 µ 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (S) Avalanche Test Circuit VDS Monitor Avalanche Waveform L EAR = 1 • L • IAP2 • 2 VDSS VDSS – VDD IAP Monitor Rg V(BR)DSS IAP D.U.T VDD VDS ID Vin 15 V 50 Ω 0 Rev.2.00 Oct 16, 2006 page 5 of 8 VDD H7N1005LD, H7N1005LS, H7N1005LM Switching Time Test Circuit Waveform 90% Vout Monitor Vin Monitor D.U.T. Rg Vin Vout Vin 10 V VDS = 30 V 10% 10% 90% td(on) Rev.2.00 Oct 16, 2006 page 6 of 8 10% RL tr 90% td(off) tf H7N1005LD, H7N1005LS, H7N1005LM Package Dimensions RENESAS Code PRSS0004AE-A MASS[Typ.] 1.40g 4.44 ± 0.2 1.3 ± 0.15 1.3 ± 0.2 1.37 ± 0.2 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 JEITA Package Code SC-83 RENESAS Code PRSS0004AE-B 2.49 ± 0.2 11.0 ± 0.5 0.2 0.86 +– 0.1 Package Name LDPAK(S)-(1) Unit: mm 10.2 ± 0.3 8.6 ± 0.3 11.3 ± 0.5 0.3 10.0 +– 0.5 Previous Code LDPAK(L) / LDPAK(L)V Previous Code LDPAK(S)-(1) / LDPAK(S)-(1)V 0.4 ± 0.1 MASS[Typ.] 1.30g (1.5) 10.0 Rev.2.00 Oct 16, 2006 page 7 of 8 2.54 ± 0.5 0.4 ± 0.1 0.3 3.0 +– 0.5 2.54 ± 0.5 0.2 0.86 +– 0.1 7.8 7.0 2.49 ± 0.2 0.2 0.1 +– 0.1 1.37 ± 0.2 1.3 ± 0.2 7.8 6.6 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 Unit: mm 1.7 JEITA Package Code (1.4) Package Name LDPAK(L) 2.2 H7N1005LD, H7N1005LS, H7N1005LM JEITA Package Code RENESAS Code PRSS0004AE-C Previous Code LDPAK(S)-(2) / LDPAK(S)-(2)V MASS[Typ.] 1.35g 7.8 6.6 (2.3) 10.0 2.49 ± 0.2 0.2 0.1 +– 0.1 7.8 7.0 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 (1.5) (1.4) 4.44 ± 0.2 10.2 ± 0.3 Unit: mm 1.7 Package Name LDPAK(S)-(2) 2.2 1.37 ± 0.2 2.54 ± 0.5 0.2 0.86 +– 0.1 2.54 ± 0.5 0.4 ± 0.1 0.3 5.0 +– 0.5 1.3 ± 0.2 Ordering Information Part Name H7N1005LD-E H7N1005LSTL-E H7N1005LMTL-E Quantity 500 pcs 1000 pcs 1000 pcs Shipping Container Box (Conductive Sack) Taping Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Oct 16, 2006 page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. 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