FINAL Am27C2048 2 Megabit (128 K x 16-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS ■ ±10% power supply tolerance standard ■ Fast access time ■ 100% Flashrite programming — Speed options as fast as 55 ns ■ Low power consumption — Typical programming time of 16 seconds — 100 µA maximum CMOS standby current ■ JEDEC-approved pinout ■ Latch-up protected to 100 mA from –1 V to VCC + 1 V ■ Versatile features for simple interfacing — Plug-in upgrade of 1 Mbit EPROM — 40-pin DIP/PDIP — Both CMOS and TTL input/output compatibility — 44-pin PLCC — Two line control functions ■ High noise immunity ■ Single +5 V power supply GENERAL DESCRIPTION The Am27C2048 is a 2 Mbit, ultraviolet erasable programmable read-only memory. It is organized as 128 K words, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The Am27C2048 is ideal for use in 16-bit microprocessor systems. The device is available in windowed ceramic DIP packages, and plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 125 mW in active mode, and 100 µW in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 µs pulses), resulting in a typical programming time of 16 seconds. BLOCK DIAGRAM VCC VSS Data Outputs DQ0–DQ15 VPP OE# CE# PGM# A0–A16 Address Inputs Output Enable Chip Enable and Prog Logic Output Buffers Y Decoder Y Gating X Decoder 2,097,152 Bit Cell Matrix 11407G-1 Publication# 11407 Rev: G Amendment/0 Issue Date: May 1998 PRODUCT SELECTOR GUIDE Family Part Number Am27C2048 VCC = 5.0 V ± 5% -55 VCC = 5.0 V ± 10% -55 -70 -90 -120 -150 -200 Max Access Time (ns) 55 70 90 120 150 200 250 CE# (E#) Access (ns) 55 70 90 120 150 200 250 OE# (G#) Access (ns) 40 40 40 50 65 75 75 Speed Options -255 CONNECTION DIAGRAMS Top View A15 DQ13 5 36 A14 DQ12 6 35 A13 DQ11 7 34 A12 DQ10 8 33 A11 DQ9 9 32 A10 DQ8 10 31 A9 2 1 44 43 42 41 40 DQ8 11 35 A9 VSS 12 34 VSS NC 13 33 NC DQ7 14 32 A8 DQ6 15 31 A7 A5 DQ5 16 30 A6 DQ4 29 17 18 19 20 21 22 23 24 25 26 27 28 A5 12 29 A8 DQ6 13 28 A7 DQ5 14 27 A6 VSS DQ3 16 25 A4 DQ2 17 24 A3 DQ1 18 23 A2 DQ0 19 22 A1 OE# (G#) 20 21 A0 11407G-2 A4 A10 A3 36 A2 10 A1 A11 DQ9 A0 37 DU (Note 2) 9 OE# (G#) A12 DQ10 DQ0 A13 38 DQ1 39 8 DQ2 7 DQ7 26 3 DQ11 11 15 4 DQ12 VSS DQ4 5 DQ3 30 6 A14 A16 37 A15 38 4 A16 3 DQ14 PGM# (P#) DQ15 VCC PGM# (P#) DU (Note 2) VCC 39 VPP 40 2 CE (E) 1 DQ15 VPP CE# (E#) DQ14 PLCC DQ13 DIP 11407G-3 Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don’t use (DU) for PLCC. PIN DESIGNATIONS A0–A16 = Address Inputs CE# (E#) = Chip Enable Input LOGIC SYMBOL 17 DQ0–DQ15 = Data Input/Outputs 16 A0–A16 OE# (G#) = Output Enable Input PGM# (P#) = Program Enable Input VCC = VCC Supply Voltage PMG (P#) VPP = Program Voltage Input OE# (G#) VSS = Ground DQ0–DQ15 CE# (E#) 11407G-4 2 Am27C2048 ORDERING INFORMATION UV EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM27C2048 -55 D C 5 B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In VOLTAGE TOLERANCE 5 = VCC ± 5%, 55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C2048 2 Megabit (128 K x 16-Bit) CMOS UV EPROM Valid Combinations Valid Combinations AM27C2048-55 VCC = 5.0 V ± 5% Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DC5, DC5B, DI5, DI5B AM27C2048-55 VCC = 5.0 V ± 10% AM27C2048-70 DC, DCB, DI, DIB AM27C2048-90 AM27C2048-120 AM27C2048-150 DC, DCB, DE, DEB, DI, DIB AM27C2048-200 AM27C2048-255 VCC = 5.0 V ± 5% DC, DCB, DI, DIB Am27C2048 3 ORDERING INFORMATION OTP EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM27C2048 -55 J C 5 OPTIONAL PROCESSING Blank = Standard Processing VOLTAGE TOLERANCE 5 = VCC ± 5%, -55 ns only See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Square Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C2048 2 Megabit (128 K x 16-Bit) CMOS OTP EPROM Valid Combinations Valid Combinations AM27C2048-55 VCC = 5.0 V ± 5% PC5, PI5, JC5, JI5 AM27C2048-55 VCC = 5.0 V ± 10% Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM27C2048-70 AM27C2048-90 AM27C2048-120 PC, PI, JC, JI AM27C2048-150 AM27C2048-200 AM27C2048-255 VCC = 5.0 V ± 5% 4 Am27C2048 FUNCTIONAL DESCRIPTION Device Erasure In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp—wavelength of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 Å, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exposure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance. Device Programming Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into the device through the programming procedure. that particular device. A high-level CE# input inhibits the other devices from being programmed. Program Verify A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# and CE#, at VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V. Autoselect Mode The autoselect mode provides manufacturer and device identification through identifier codes on DQ0– DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. The device enters the programming mode when 12.75 V ± 0.25 V is applied to the VPP pin, and CE# and PGM# are at VIL. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit. For programming, the data to be programmed is applied 16 bits in parallel to the data pins. Read Mode The flowchart in the Programming section (Section 5, Figure 5-1) shows AMD’s Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 µs programming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least tACC –tOE. Refer to the Switching Waveforms section for the timing diagram. Standby Mode The device enters the CMOS standby mode when CE# is at VCC ± 0.3 V. Maximum VCC current is reduced to 100 µA. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input. Please refer to Section 5 for additional programming information and specifications. Output OR-Tieing Program Inhibit To accommodate multiple memory connections, a two-line control function provides: Programming different data to multiple devices in parallel is easily accomplished. Except for CE#, all like inputs of the devices may be common. A TTL low-level program pulse applied to one device’s CE# input with VPP = 12.75 V ± 0.25 V and PGM# LOW will program ■ low memory power dissipation, and ■ assurance that output bus contention will not occur. CE# should be decoded and used as the primary device-selecting function, while OE# be made a common connection to all devices in the array and connected to Am27C2048 5 the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1 µF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Mode CE# OE# PGM# A0 A9 VPP Outputs Read VIL VIL X X X X DOUT Output Disable VIL VIH X X X X High Z Standby (TTL) VIH X X X X X High Z VCC ± 0.3 V X X X X X High Z Program VIL X VIL X X VPP DIN Program Verify VIL VIL VIH X X VPP DOUT Program Inhibit VIH X X X X VPP High Z Manufacturer Code VIL VIL X VIL VH X 01h Device Code VIL VIL X VIH VH X 98h Standby (CMOS) Autoselect (Note 3) Notes: 1. VH = 12.0 V ± 0.5 V. 2. X = Either VIH or VIL. 3. A1–A8 and A10–16 = VIL. 4. See DC Programming Characteristics for VPP voltage during programming. 6 Am27C2048 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C All Other Products . . . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C Voltage with Respect to VSS All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V Extended (E) Devices A9 and VPP (Note 2) . . . . . . . . . . . . . –0.6 V to 13.5 V Supply Read Voltages VCC (Note 1). . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V Notes: 1. Minimum DC voltage on input or I/O pins –0.5 V. During voltage transitions, the input may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. Ambient Temperature (TA) . . . . . . . .–55°C to +125°C Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on A9 is –0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. A9 and VPP must not exceed+13.5 V at any time. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability. Am27C2048 7 DC CHARACTERISTICS OVER OPERATING RANGE (unless otherwise specified) Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –400 µA VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Load Current Min Max 2.4 VIN = 0 V to VCC ILO Output Leakage Current VOUT = 0 V to VCC ICC1 VCC Active Current (Note 2) CE# = VIL, f = 5 MHz, IOUT = 0 mA Unit V 0.45 V 2.0 VCC + 0.5 V –0.5 +0.8 V C/I Devices 1.0 µA E Devices 5.0 5.0 C/I Devices 50 E Devices 60 µA mA ICC2 VCC TTL Standby Current CE# = VIH 1.0 mA ICC3 VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA IPP1 VPP Supply Current (Read) CE# = OE# = VIL, VPP = VCC 100 µA Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied. Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 35 35 30 30 Supply Current in mA Supply Current in mA 3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. 25 20 Figure 1. 8 2 3 4 5 6 7 Frequency in MHz 8 9 20 15 –75 –50 –55 0 25 50 75 100 125 150 Temperature in °C 15 1 25 10 11407G-5 11407G-6 Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25°C Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 5 MHz Am27C2048 TEST CONDITIONS Table 1. 5.0 V Test Condition 2.7 kΩ Device Under Test Test Specifications Output Load CL 30 Input Pulse Levels 11407G-7 Figure 3. 100 pF ≤ 20 Input Rise and Fall Times Note: Diodes are IN3064 or equivalents. Unit 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 6.2 kΩ All others -55 ns 0.0–3.0 0.45–2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement reference levels 1.5 0.8, 2.0 V Test Setup SWITCHING TEST WAVEFORM 3V 2.4 V 2.0 V 2.0 V Test Points 1.5 V Test Points 1.5 V 0.8 V 0V 0.8 V 0.45 V Input Output Output Input Note: For CL = 30 pF. Note: For CL = 100 pF. 11407G-8 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) KS000010-PAL Am27C2048 9 AC CHARACTERISTICS Parameter Symbols JEDEC Standard tAVQV tACC tELQV Am27C2048 Description Test Setup -55 -70 -90 -120 -150 -200 -255 Unit Address to Output Delay CE#, Max OE# = VIL 55 70 90 120 150 200 250 ns tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 200 250 ns tGLQV tOE Output Enable to Output Delay CE# = VIL Max 40 40 40 50 65 75 75 ns tEHQZ tGHQZ tDF (Note 2) Chip Enable High or Output Enable High to Output High Z, Whichever Occurs First Max 25 25 25 30 30 40 60 ns tAXQX tOH Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First Min 0 0 0 0 0 0 0 ns Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied. Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is sampled and not 100% tested. 3. Switching characteristics are over operating range, unless otherwise specified. 4. See Figure 3 and Table 1 for test specifications. SWITCHING WAVEFORMS 2.4 Addresses 0.45 2.0 0.8 2.0 0.8 Addresses Valid CE# tCE OE# tDF (Note 2) tOE High Z Output tACC (Note 1) tOH High Z Valid Output 11407G-9 Notes: 1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE# or CE#, whichever occurs first. PACKAGE CAPACITANCE Parameter Symbol CIN COUT Parameter Description CDV040 Test Conditions PL 044 Typ Max Typ Max Typ Max Unit Input Capacitance VIN = 0 10 12 10 12 7 10 pF Output Capacitance VOUT = 0 12 15 12 15 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25°C, f = 1 MHz. 10 PD 040 Am27C2048 PHYSICAL DIMENSIONS* CDV040—40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches) DATUM D CENTER PLANE UV Lens .565 .605 1 INDEX AND TERMINAL NO. 1 I.D. AREA TOP VIEW DATUM D CENTER PLANE 2.035 2.080 .160 .220 BASE PLANE SEATING PLANE .015 .060 .700 MAX 94° 105° .125 .200 .300 BSC .005 MIN .600 BSC .045 .065 .008 .018 .100 BSC .014 .026 END VIEW SIDE VIEW 16-000038H-3 CDV040 DF11 3-30-95 ae * For reference only. BSC is an ANSI standard for Basic Space Centering. PD 040—40-Pin Plastic Dual In-Line Package (measured in inches) 2.040 2.080 .600 .625 21 40 .008 .015 .530 .580 Pin 1 I.D. .630 .700 20 .045 .065 0° 10° .005 MIN .140 .225 SEATING PLANE .120 .160 .090 .110 .014 .022 .015 .060 Am27C2048 16-038-SC_AF PD 040 DG76 2-28-95 ae 11 PHYSICAL DIMENSIONS PL 044—44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .042 .056 .650 .656 .062 .083 Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630 .013 .021 .026 .032 .009 .015 .050 REF TOP VIEW .090 .120 .165 .180 SEATING PLANE SIDE VIEW REVISION SUMMARY FOR AM27C2048 Revision G Global Changed formatting to match current data sheets. Connection Diagrams Corrected designation for pin 38 on PDIP connection diagram to A16. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Flashrite is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 12 Am27C2048 16-038-SQ PL 044 EC80 11.3.97 lv